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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Tony Lindgren45c3eb72012-11-30 08:41:50 -080031#include <linux/omap-dma.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070032#include <linux/platform_data/gpio-omap.h>
33
Jean Pihet5e7c58d2011-03-03 11:25:43 +010034#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070035
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070036#include <asm/fncpy.h>
Russell King2c74a0c2011-06-22 17:41:48 +010037#include <asm/suspend.h>
David Howells9f97da72012-03-28 18:30:01 +010038#include <asm/system_misc.h>
Russell King2c74a0c2011-06-22 17:41:48 +010039
Paul Walmsley1540f2142010-12-21 21:05:15 -070040#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070041#include "powerdomain.h"
Tony Lindgrene4c060d2012-10-05 13:25:59 -070042#include "soc.h"
Tony Lindgren4e653312011-11-10 22:45:17 +010043#include "common.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060044#include "cm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070045#include "cm-regbits-34xx.h"
Tony Lindgren99f0b8d2012-10-17 11:07:18 -070046#include "gpmc.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070047#include "prm-regbits-34xx.h"
Paul Walmsley139563a2012-10-21 01:01:10 -060048#include "prm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070049#include "pm.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030050#include "sdrc.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070051#include "sram.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030053
Nishanth Menon8cdfd832010-12-20 14:05:05 -060054/* pm34xx errata defined in pm.h */
55u16 pm34xx_errata;
56
Kevin Hilman8bd22942009-05-28 10:56:16 -070057struct power_state {
58 struct powerdomain *pwrdm;
59 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070060#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070061 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070062#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070063 struct list_head node;
64};
65
66static LIST_HEAD(pwrst_list);
67
Tero Kristo27d59a42008-10-13 13:15:00 +030068static int (*_omap_save_secure_sram)(u32 *addr);
Jean Pihet46e130d2011-06-29 18:40:23 +020069void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030070
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053071static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72static struct powerdomain *core_pwrdm, *per_pwrdm;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020073
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053074static void omap3_core_save_context(void)
75{
Paul Walmsley596efe42010-12-21 21:05:16 -070076 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +020077
78 /*
79 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +010080 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +020081 */
82 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
83 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
84
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053085 /* Save the Interrupt controller context */
86 omap_intc_save_context();
87 /* Save the GPMC context */
88 omap3_gpmc_save_context();
89 /* Save the system control module context, padconf already save above*/
90 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +000091 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053092}
93
94static void omap3_core_restore_context(void)
95{
96 /* Restore the control module context, padconf restored by h/w */
97 omap3_control_restore_context();
98 /* Restore the GPMC context */
99 omap3_gpmc_restore_context();
100 /* Restore the interrupt controller context */
101 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000102 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530103}
104
Tero Kristo9d971402008-12-12 11:20:05 +0200105/*
106 * FIXME: This function should be called before entering off-mode after
107 * OMAP3 secure services have been accessed. Currently it is only called
108 * once during boot sequence, but this works as we are not using secure
109 * services.
110 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800111static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300112{
113 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800114 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300115
116 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300117 /*
118 * MPU next state must be set to POWER_ON temporarily,
119 * otherwise the WFI executed inside the ROM code
120 * will hang the system.
121 */
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *)
124 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300126 /* Following is for error tracking, it should not happen */
127 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700128 pr_err("save_secure_sram() returns %08x\n", ret);
Tero Kristo27d59a42008-10-13 13:15:00 +0300129 while (1)
130 ;
131 }
132 }
133}
134
Jon Hunter77da2d92009-06-27 00:07:25 -0500135/*
136 * PRCM Interrupt Handler Helper Function
137 *
138 * The purpose of this function is to clear any wake-up events latched
139 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
140 * may occur whilst attempting to clear a PM_WKST_x register and thus
141 * set another bit in this register. A while loop is used to ensure
142 * that any peripheral wake-up events occurring while attempting to
143 * clear the PM_WKST_x are detected and cleared.
144 */
Tero Kristo22f51372011-12-16 14:36:59 -0700145static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
Jon Hunter77da2d92009-06-27 00:07:25 -0500146{
Vikram Pandita71a80772009-07-17 19:33:09 -0500147 u32 wkst, fclk, iclk, clken;
Jon Hunter77da2d92009-06-27 00:07:25 -0500148 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
149 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
150 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
Paul Walmsley5d805972009-07-22 10:18:07 -0700151 u16 grpsel_off = (regs == 3) ?
152 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700153 int c = 0;
Jon Hunter77da2d92009-06-27 00:07:25 -0500154
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700155 wkst = omap2_prm_read_mod_reg(module, wkst_off);
156 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700157 wkst &= ~ignore_bits;
Jon Hunter77da2d92009-06-27 00:07:25 -0500158 if (wkst) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700159 iclk = omap2_cm_read_mod_reg(module, iclk_off);
160 fclk = omap2_cm_read_mod_reg(module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500161 while (wkst) {
Vikram Pandita71a80772009-07-17 19:33:09 -0500162 clken = wkst;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700163 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
Vikram Pandita71a80772009-07-17 19:33:09 -0500164 /*
165 * For USBHOST, we don't know whether HOST1 or
166 * HOST2 woke us up, so enable both f-clocks
167 */
168 if (module == OMAP3430ES2_USBHOST_MOD)
169 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700170 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
171 omap2_prm_write_mod_reg(wkst, module, wkst_off);
172 wkst = omap2_prm_read_mod_reg(module, wkst_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700173 wkst &= ~ignore_bits;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700174 c++;
Jon Hunter77da2d92009-06-27 00:07:25 -0500175 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700176 omap2_cm_write_mod_reg(iclk, module, iclk_off);
177 omap2_cm_write_mod_reg(fclk, module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500178 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700179
180 return c;
181}
182
Tero Kristo22f51372011-12-16 14:36:59 -0700183static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700184{
185 int c;
186
Tero Kristo22f51372011-12-16 14:36:59 -0700187 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
188 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700189
Tero Kristo22f51372011-12-16 14:36:59 -0700190 return c ? IRQ_HANDLED : IRQ_NONE;
Jon Hunter77da2d92009-06-27 00:07:25 -0500191}
192
Tero Kristo22f51372011-12-16 14:36:59 -0700193static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700194{
Tero Kristo22f51372011-12-16 14:36:59 -0700195 int c;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700196
Tero Kristo22f51372011-12-16 14:36:59 -0700197 /*
198 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
199 * these are handled in a separate handler to avoid acking
200 * IO events before parsing in mux code
201 */
202 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
203 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
204 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
205 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
206 if (omap_rev() > OMAP3430_REV_ES1_0) {
207 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
208 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
209 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700210
Tero Kristo22f51372011-12-16 14:36:59 -0700211 return c ? IRQ_HANDLED : IRQ_NONE;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700212}
213
Russell Kingcbe26342011-06-30 08:45:49 +0100214static void omap34xx_save_context(u32 *save)
215{
216 u32 val;
217
218 /* Read Auxiliary Control Register */
219 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
220 *save++ = 1;
221 *save++ = val;
222
223 /* Read L2 AUX ctrl register */
224 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
225 *save++ = 1;
226 *save++ = val;
227}
228
Russell King29cb3cd2011-07-02 09:54:01 +0100229static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530230{
Russell Kingcbe26342011-06-30 08:45:49 +0100231 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100232 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530233}
234
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530235void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700236{
237 /* Variable to tell what needs to be saved and restored
238 * in omap_sram_idle*/
239 /* save_state = 0 => Nothing to save and restored */
240 /* save_state = 1 => Only L1 and logic lost */
241 /* save_state = 2 => Only L2 lost */
242 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530243 int save_state = 0;
244 int mpu_next_state = PWRDM_POWER_ON;
245 int per_next_state = PWRDM_POWER_ON;
246 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700247 int per_going_off;
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600248 int core_prev_state;
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300249 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700250
Kevin Hilman8bd22942009-05-28 10:56:16 -0700251 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
252 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530253 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700254 case PWRDM_POWER_RET:
255 /* No need to save context */
256 save_state = 0;
257 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530258 case PWRDM_POWER_OFF:
259 save_state = 3;
260 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700261 default:
262 /* Invalid state */
Mark A. Greer98179852012-03-17 18:22:48 -0700263 pr_err("Invalid mpu state in sram_idle\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700264 return;
265 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300266
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530267 /* NEON control */
268 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200269 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530270
Mike Chan40742fa2010-05-03 16:04:06 -0700271 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Mike Chan40742fa2010-05-03 16:04:06 -0700274
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700275 pwrdm_pre_transition(NULL);
Charulatha Vff2f8e52011-09-13 18:32:37 +0530276
Mike Chan40742fa2010-05-03 16:04:06 -0700277 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800278 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700279 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700280 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilman658ce972008-11-04 20:50:52 -0800281 }
282
283 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530284 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530285 if (core_next_state == PWRDM_POWER_OFF) {
286 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700287 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530288 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530289 }
Mike Chan40742fa2010-05-03 16:04:06 -0700290
Tero Kristof18cc2f2009-10-23 19:03:50 +0300291 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700292
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530293 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600294 * On EMU/HS devices ROM code restores a SRDC value
295 * from scratchpad which has automatic self refresh on timeout
296 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
297 * Hence store/restore the SDRC_POWER register here.
298 */
299 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
300 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
301 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530302 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300303 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300304
305 /*
Russell King076f2cc2011-06-22 15:42:54 +0100306 * omap3_arm_context is the location where some ARM context
307 * get saved. The rest is placed on the stack, and restored
308 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530309 */
Russell Kingcbe26342011-06-30 08:45:49 +0100310 if (save_state)
311 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100312 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100313 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100314 else
315 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700316
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530317 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600318 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
319 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
320 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300321 core_next_state == PWRDM_POWER_OFF)
322 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
323
Kevin Hilman658ce972008-11-04 20:50:52 -0800324 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530325 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530326 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
327 if (core_prev_state == PWRDM_POWER_OFF) {
328 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700329 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530330 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300331 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530332 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800333 if (core_next_state == PWRDM_POWER_OFF)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700334 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
Kevin Hilman658ce972008-11-04 20:50:52 -0800335 OMAP3430_GR_MOD,
336 OMAP3_PRM_VOLTCTRL_OFFSET);
337 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300338 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800339
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700340 pwrdm_post_transition(NULL);
Kevin Hilman658ce972008-11-04 20:50:52 -0800341
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700342 /* PER */
343 if (per_next_state < PWRDM_POWER_ON)
344 omap2_gpio_resume_after_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700345}
346
Kevin Hilman8bd22942009-05-28 10:56:16 -0700347static void omap3_pm_idle(void)
348{
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500349 if (omap_irq_pending())
Santosh Shilimkar6b856382013-02-11 19:29:45 +0530350 return;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700351
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100352 trace_cpu_idle(1, smp_processor_id());
353
Kevin Hilman8bd22942009-05-28 10:56:16 -0700354 omap_sram_idle();
355
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100356 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
Kevin Hilman8bd22942009-05-28 10:56:16 -0700357}
358
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700359#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700360static int omap3_pm_suspend(void)
361{
362 struct power_state *pwrst;
363 int state, ret = 0;
364
365 /* Read current next_pwrsts */
366 list_for_each_entry(pwrst, &pwrst_list, node)
367 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
368 /* Set ones wanted by suspend */
369 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530370 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700371 goto restore;
372 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
373 goto restore;
374 }
375
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300376 omap3_intc_suspend();
377
Kevin Hilman8bd22942009-05-28 10:56:16 -0700378 omap_sram_idle();
379
380restore:
381 /* Restore next_pwrsts */
382 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700383 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
384 if (state > pwrst->next_state) {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600385 pr_info("Powerdomain (%s) didn't enter target state %d\n",
386 pwrst->pwrdm->name, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700387 ret = -1;
388 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530389 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700390 }
391 if (ret)
Mark A. Greer98179852012-03-17 18:22:48 -0700392 pr_err("Could not enter target state in pm_suspend\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700393 else
Mark A. Greer98179852012-03-17 18:22:48 -0700394 pr_info("Successfully put all powerdomains to target state\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700395
396 return ret;
397}
398
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700399#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700400
Kevin Hilman1155e422008-11-25 11:48:24 -0800401
402/**
403 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
404 * retention
405 *
406 * In cases where IVA2 is activated by bootcode, it may prevent
407 * full-chip retention or off-mode because it is not idle. This
408 * function forces the IVA2 into idle state so it can go
409 * into retention/off and thus allow full-chip retention/off.
410 *
411 **/
412static void __init omap3_iva_idle(void)
413{
414 /* ensure IVA2 clock is disabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700415 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800416
417 /* if no clock activity, nothing else to do */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700418 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
Kevin Hilman1155e422008-11-25 11:48:24 -0800419 OMAP3430_CLKACTIVITY_IVA2_MASK))
420 return;
421
422 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700423 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600424 OMAP3430_RST2_IVA2_MASK |
425 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700426 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800427
428 /* Enable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700429 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
Kevin Hilman1155e422008-11-25 11:48:24 -0800430 OMAP3430_IVA2_MOD, CM_FCLKEN);
431
432 /* Set IVA2 boot mode to 'idle' */
433 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
434 OMAP343X_CONTROL_IVA2_BOOTMOD);
435
436 /* Un-reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700437 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800438
439 /* Disable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700440 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800441
442 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700443 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600444 OMAP3430_RST2_IVA2_MASK |
445 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700446 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800447}
448
Kevin Hilman8111b222009-04-28 15:27:44 -0700449static void __init omap3_d2d_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700450{
Kevin Hilman8111b222009-04-28 15:27:44 -0700451 u16 mask, padconf;
452
453 /* In a stand alone OMAP3430 where there is not a stacked
454 * modem for the D2D Idle Ack and D2D MStandby must be pulled
455 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
456 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
457 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
458 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
459 padconf |= mask;
460 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
461
462 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
463 padconf |= mask;
464 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
465
Kevin Hilman8bd22942009-05-28 10:56:16 -0700466 /* reset modem */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700467 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600468 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700469 CORE_MOD, OMAP2_RM_RSTCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700470 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman8111b222009-04-28 15:27:44 -0700471}
Kevin Hilman8bd22942009-05-28 10:56:16 -0700472
Kevin Hilman8111b222009-04-28 15:27:44 -0700473static void __init prcm_setup_regs(void)
474{
Govindraj.Re5863682010-09-27 20:20:25 +0530475 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
476 OMAP3630_EN_UART4_MASK : 0;
477 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
478 OMAP3630_GRPSEL_UART4_MASK : 0;
479
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700480 /* XXX This should be handled by hwmod code or SCM init code */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600481 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
Tero Kristob296c812009-10-23 19:03:49 +0300482
Kevin Hilman8bd22942009-05-28 10:56:16 -0700483 /*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700484 * Enable control of expternal oscillator through
485 * sys_clkreq. In the long run clock framework should
486 * take care of this.
487 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700488 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700489 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
490 OMAP3430_GR_MOD,
491 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
492
493 /* setup wakup source */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700494 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600495 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700496 WKUP_MOD, PM_WKEN);
497 /* No need to write EN_IO, that is always enabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700498 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600499 OMAP3430_GRPSEL_GPT1_MASK |
500 OMAP3430_GRPSEL_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700501 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800502
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530503 /* Enable PM_WKEN to support DSS LPR */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700504 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530505 OMAP3430_DSS_MOD, PM_WKEN);
506
Kevin Hilmanb427f922009-10-22 14:48:13 -0700507 /* Enable wakeups in PER */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700508 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530509 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600510 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
511 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
512 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
513 OMAP3430_EN_MCBSP4_MASK,
Kevin Hilmanb427f922009-10-22 14:48:13 -0700514 OMAP3430_PER_MOD, PM_WKEN);
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000515 /* and allow them to wake up MPU */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700516 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530517 OMAP3430_GRPSEL_GPIO2_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600518 OMAP3430_GRPSEL_GPIO3_MASK |
519 OMAP3430_GRPSEL_GPIO4_MASK |
520 OMAP3430_GRPSEL_GPIO5_MASK |
521 OMAP3430_GRPSEL_GPIO6_MASK |
522 OMAP3430_GRPSEL_UART3_MASK |
523 OMAP3430_GRPSEL_MCBSP2_MASK |
524 OMAP3430_GRPSEL_MCBSP3_MASK |
525 OMAP3430_GRPSEL_MCBSP4_MASK,
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000526 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
527
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700528 /* Don't attach IVA interrupts */
Mark A. Greera819c4f2012-04-19 11:17:45 -0700529 if (omap3_has_iva()) {
530 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
531 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
532 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
533 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
534 OMAP3430_PM_IVAGRPSEL);
535 }
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700536
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700537 /* Clear any pending 'reset' flags */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700538 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
539 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
540 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
541 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
542 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
543 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
544 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700545
Kevin Hilman014c46d2009-04-27 07:50:23 -0700546 /* Clear any pending PRCM interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman014c46d2009-04-27 07:50:23 -0700548
Tony Lindgren2d403f72013-05-30 12:44:47 -0700549 /*
550 * We need to idle iva2_pwrdm even on am3703 with no iva2.
551 */
552 omap3_iva_idle();
Mark A. Greera819c4f2012-04-19 11:17:45 -0700553
Kevin Hilman8111b222009-04-28 15:27:44 -0700554 omap3_d2d_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700555}
556
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700557void omap3_pm_off_mode_enable(int enable)
558{
559 struct power_state *pwrst;
560 u32 state;
561
562 if (enable)
563 state = PWRDM_POWER_OFF;
564 else
565 state = PWRDM_POWER_RET;
566
567 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600568 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
569 pwrst->pwrdm == core_pwrdm &&
570 state == PWRDM_POWER_OFF) {
571 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200572 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600573 __func__);
574 } else {
575 pwrst->next_state = state;
576 }
577 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700578 }
579}
580
Tero Kristo68d47782008-11-26 12:26:24 +0200581int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
582{
583 struct power_state *pwrst;
584
585 list_for_each_entry(pwrst, &pwrst_list, node) {
586 if (pwrst->pwrdm == pwrdm)
587 return pwrst->next_state;
588 }
589 return -EINVAL;
590}
591
592int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
593{
594 struct power_state *pwrst;
595
596 list_for_each_entry(pwrst, &pwrst_list, node) {
597 if (pwrst->pwrdm == pwrdm) {
598 pwrst->next_state = state;
599 return 0;
600 }
601 }
602 return -EINVAL;
603}
604
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300605static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700606{
607 struct power_state *pwrst;
608
609 if (!pwrdm->pwrsts)
610 return 0;
611
Ming Leid3d381c2009-08-22 21:20:26 +0800612 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700613 if (!pwrst)
614 return -ENOMEM;
615 pwrst->pwrdm = pwrdm;
616 pwrst->next_state = PWRDM_POWER_RET;
617 list_add(&pwrst->node, &pwrst_list);
618
619 if (pwrdm_has_hdwr_sar(pwrdm))
620 pwrdm_enable_hdwr_sar(pwrdm);
621
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530622 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700623}
624
625/*
Jean Pihet46e130d2011-06-29 18:40:23 +0200626 * Push functions to SRAM
627 *
628 * The minimum set of functions is pushed to SRAM for execution:
629 * - omap3_do_wfi for erratum i581 WA,
630 * - save_secure_ram_context for security extensions.
631 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530632void omap_push_sram_idle(void)
633{
Jean Pihet46e130d2011-06-29 18:40:23 +0200634 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
635
Tero Kristo27d59a42008-10-13 13:15:00 +0300636 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
637 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
638 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530639}
640
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600641static void __init pm_errata_configure(void)
642{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600643 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600644 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600645 /* Enable the l2 cache toggling in sleep logic */
646 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600647 if (omap_rev() < OMAP3630_REV_ES1_2)
Paul Walmsley856c3c52012-10-16 00:08:53 -0600648 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
649 PM_PER_MEMORIES_ERRATUM_i582);
650 } else if (cpu_is_omap34xx()) {
651 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600652 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600653}
654
Shawn Guobbd707a2012-04-26 16:06:50 +0800655int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700656{
657 struct power_state *pwrst, *tmp;
Paul Walmsley856c3c52012-10-16 00:08:53 -0600658 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700659 int ret;
660
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600661 if (!omap3_has_io_chain_ctrl())
662 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
663
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600664 pm_errata_configure();
665
Kevin Hilman8bd22942009-05-28 10:56:16 -0700666 /* XXX prcm_setup_regs needs to be before enabling hw
667 * supervised mode for powerdomains */
668 prcm_setup_regs();
669
Tero Kristo22f51372011-12-16 14:36:59 -0700670 ret = request_irq(omap_prcm_event_to_irq("wkup"),
671 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
672
Kevin Hilman8bd22942009-05-28 10:56:16 -0700673 if (ret) {
Tero Kristo22f51372011-12-16 14:36:59 -0700674 pr_err("pm: Failed to request pm_wkup irq\n");
675 goto err1;
676 }
677
678 /* IO interrupt is shared with mux code */
679 ret = request_irq(omap_prcm_event_to_irq("io"),
680 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
681 omap3_pm_init);
Kevin Hilman99b59df2012-04-27 16:05:51 -0700682 enable_irq(omap_prcm_event_to_irq("io"));
Tero Kristo22f51372011-12-16 14:36:59 -0700683
684 if (ret) {
685 pr_err("pm: Failed to request pm_io irq\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700686 goto err2;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700687 }
688
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300689 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700690 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700691 pr_err("Failed to setup powerdomains\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700692 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700693 }
694
Paul Walmsley92206fd2012-02-02 02:38:50 -0700695 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700696
697 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
698 if (mpu_pwrdm == NULL) {
Mark A. Greer98179852012-03-17 18:22:48 -0700699 pr_err("Failed to get mpu_pwrdm\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700700 ret = -EINVAL;
701 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700702 }
703
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530704 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
705 per_pwrdm = pwrdm_lookup("per_pwrdm");
706 core_pwrdm = pwrdm_lookup("core_pwrdm");
707
Paul Walmsley55ed9692010-01-26 20:12:59 -0700708 neon_clkdm = clkdm_lookup("neon_clkdm");
709 mpu_clkdm = clkdm_lookup("mpu_clkdm");
Paul Walmsley856c3c52012-10-16 00:08:53 -0600710 per_clkdm = clkdm_lookup("per_clkdm");
711 wkup_clkdm = clkdm_lookup("wkup_clkdm");
Paul Walmsley55ed9692010-01-26 20:12:59 -0700712
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700713#ifdef CONFIG_SUSPEND
Paul Walmsley14164082012-02-02 02:30:50 -0700714 omap_pm_suspend = omap3_pm_suspend;
715#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -0700716
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500717 arm_pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300718 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700719
Nishanth Menon458e9992010-12-20 14:05:06 -0600720 /*
721 * RTA is disabled during initialization as per erratum i608
722 * it is safer to disable RTA by the bootloader, but we would like
723 * to be doubly sure here and prevent any mishaps.
724 */
725 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
726 omap3630_ctrl_disable_rta();
727
Paul Walmsley856c3c52012-10-16 00:08:53 -0600728 /*
729 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
730 * not correctly reset when the PER powerdomain comes back
731 * from OFF or OSWR when the CORE powerdomain is kept active.
732 * See OMAP36xx Erratum i582 "PER Domain reset issue after
733 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
734 * complete workaround. The kernel must also prevent the PER
735 * powerdomain from going to OSWR/OFF while the CORE
736 * powerdomain is not going to OSWR/OFF. And if PER last
737 * power state was off while CORE last power state was ON, the
738 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
739 * self-test using their loopback tests; if that fails, those
740 * devices are unusable until the PER/CORE can complete a transition
741 * from ON to OSWR/OFF and then back to ON.
742 *
743 * XXX Technically this workaround is only needed if off-mode
744 * or OSWR is enabled.
745 */
746 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
747 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
748
Paul Walmsley55ed9692010-01-26 20:12:59 -0700749 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300750 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
751 omap3_secure_ram_storage =
752 kmalloc(0x803F, GFP_KERNEL);
753 if (!omap3_secure_ram_storage)
Paul Walmsley7852ec02012-07-26 00:54:26 -0600754 pr_err("Memory allocation failed when allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300755
Tero Kristo9d971402008-12-12 11:20:05 +0200756 local_irq_disable();
Tero Kristo9d971402008-12-12 11:20:05 +0200757
758 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800759 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200760 omap_dma_global_context_restore();
761
762 local_irq_enable();
Tero Kristo9d971402008-12-12 11:20:05 +0200763 }
764
765 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700766 return ret;
Mark A. Greerce229c52012-03-17 18:22:47 -0700767
768err3:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700769 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
770 list_del(&pwrst->node);
771 kfree(pwrst);
772 }
Mark A. Greerce229c52012-03-17 18:22:47 -0700773 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
774err2:
775 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
776err1:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700777 return ret;
778}