| Changhwan Youn | 2b12b5c | 2010-07-26 21:08:52 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s5pv310/include/mach/map.h |
| 2 | * |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ |
| 5 | * |
| 6 | * S5PV310 - Memory map definitions |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MAP_H |
| 14 | #define __ASM_ARCH_MAP_H __FILE__ |
| 15 | |
| 16 | #include <plat/map-base.h> |
| 17 | |
| 18 | /* |
| 19 | * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400. |
| 20 | * So need to define it, and here is to avoid redefinition warning. |
| 21 | */ |
| 22 | #define S3C_UART_OFFSET (0x10000) |
| 23 | |
| 24 | #include <plat/map-s5p.h> |
| 25 | |
| Changhwan Youn | 766211e | 2010-08-27 17:57:44 +0900 | [diff] [blame] | 26 | #define S5PV310_PA_SYSRAM (0x02025000) |
| 27 | |
| Kukjin Kim | 13904fb | 2010-08-27 13:56:54 +0900 | [diff] [blame] | 28 | #define S5PC210_PA_ONENAND (0x0C000000) |
| 29 | #define S5P_PA_ONENAND S5PC210_PA_ONENAND |
| 30 | |
| 31 | #define S5PC210_PA_ONENAND_DMA (0x0C600000) |
| 32 | #define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA |
| 33 | |
| Changhwan Youn | 2b12b5c | 2010-07-26 21:08:52 +0900 | [diff] [blame] | 34 | #define S5PV310_PA_CHIPID (0x10000000) |
| 35 | #define S5P_PA_CHIPID S5PV310_PA_CHIPID |
| 36 | |
| 37 | #define S5PV310_PA_SYSCON (0x10020000) |
| 38 | #define S5P_PA_SYSCON S5PV310_PA_SYSCON |
| 39 | |
| Kukjin Kim | c598c47 | 2010-08-18 21:45:49 +0900 | [diff] [blame] | 40 | #define S5PV310_PA_CMU (0x10030000) |
| 41 | |
| Changhwan Youn | 2b12b5c | 2010-07-26 21:08:52 +0900 | [diff] [blame] | 42 | #define S5PV310_PA_WATCHDOG (0x10060000) |
| 43 | |
| 44 | #define S5PV310_PA_COMBINER (0x10448000) |
| 45 | |
| 46 | #define S5PV310_PA_COREPERI (0x10500000) |
| 47 | #define S5PV310_PA_GIC_CPU (0x10500100) |
| 48 | #define S5PV310_PA_TWD (0x10500600) |
| 49 | #define S5PV310_PA_GIC_DIST (0x10501000) |
| 50 | #define S5PV310_PA_L2CC (0x10502000) |
| 51 | |
| Kyungmin Park | 4d91470 | 2010-08-20 20:41:31 +0900 | [diff] [blame] | 52 | #define S5PV310_PA_GPIO1 (0x11400000) |
| 53 | #define S5PV310_PA_GPIO2 (0x11000000) |
| 54 | #define S5PV310_PA_GPIO3 (0x03860000) |
| Kyungmin Park | 4d91470 | 2010-08-20 20:41:31 +0900 | [diff] [blame] | 55 | |
| 56 | #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) |
| Changhwan Youn | 2b12b5c | 2010-07-26 21:08:52 +0900 | [diff] [blame] | 57 | |
| 58 | #define S5PV310_PA_UART (0x13800000) |
| 59 | |
| 60 | #define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) |
| 61 | #define S5P_PA_UART0 S5P_PA_UART(0) |
| 62 | #define S5P_PA_UART1 S5P_PA_UART(1) |
| 63 | #define S5P_PA_UART2 S5P_PA_UART(2) |
| 64 | #define S5P_PA_UART3 S5P_PA_UART(3) |
| 65 | #define S5P_PA_UART4 S5P_PA_UART(4) |
| 66 | |
| 67 | #define S5P_SZ_UART SZ_256 |
| 68 | |
| 69 | #define S5PV310_PA_IIC0 (0x13860000) |
| 70 | |
| 71 | #define S5PV310_PA_TIMER (0x139D0000) |
| 72 | #define S5P_PA_TIMER S5PV310_PA_TIMER |
| 73 | |
| 74 | #define S5PV310_PA_SDRAM (0x40000000) |
| 75 | #define S5P_PA_SDRAM S5PV310_PA_SDRAM |
| 76 | |
| 77 | /* compatibiltiy defines. */ |
| 78 | #define S3C_PA_UART S5PV310_PA_UART |
| Kyungmin Park | 4d91470 | 2010-08-20 20:41:31 +0900 | [diff] [blame] | 79 | #define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) |
| 80 | #define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) |
| 81 | #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) |
| 82 | #define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3) |
| Changhwan Youn | 2b12b5c | 2010-07-26 21:08:52 +0900 | [diff] [blame] | 83 | #define S3C_PA_IIC S5PV310_PA_IIC0 |
| 84 | #define S3C_PA_WDT S5PV310_PA_WATCHDOG |
| 85 | |
| 86 | #endif /* __ASM_ARCH_MAP_H */ |