| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. |
| 5 | * |
| 6 | * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) |
| 7 | */ |
| 8 | |
| 9 | /****************************************************************************/ |
| 10 | #ifndef m528xsim_h |
| 11 | #define m528xsim_h |
| 12 | /****************************************************************************/ |
| 13 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * Define the 5280/5282 SIM register set addresses. |
| 17 | */ |
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ |
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 26 | #define MCFINTC_IRLR 0x18 /* */ |
| 27 | #define MCFINTC_IACKL 0x19 /* */ |
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 29 | |
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ |
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 32 | #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ |
| 33 | |
| 34 | /* |
| 35 | * SDRAM configuration registers. |
| 36 | */ |
| 37 | #define MCFSIM_DCR 0x44 /* SDRAM control */ |
| 38 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ |
| 39 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ |
| 40 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ |
| 41 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ |
| 42 | |
| Greg Ungerer | 7ce4d42 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 43 | /* |
| sfking@fdwdc.com | 6da6e63 | 2009-06-19 18:11:08 -0700 | [diff] [blame^] | 44 | * GPIO registers |
| 45 | */ |
| 46 | #define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) |
| 47 | #define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001) |
| 48 | #define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002) |
| 49 | #define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003) |
| 50 | #define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004) |
| 51 | #define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005) |
| 52 | #define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006) |
| 53 | #define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007) |
| 54 | #define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008) |
| 55 | #define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009) |
| 56 | #define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A) |
| 57 | #define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B) |
| 58 | #define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C) |
| 59 | #define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D) |
| 60 | #define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E) |
| 61 | #define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F) |
| 62 | #define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010) |
| 63 | #define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011) |
| 64 | |
| 65 | #define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014) |
| 66 | #define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015) |
| 67 | #define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016) |
| 68 | #define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017) |
| 69 | #define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018) |
| 70 | #define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019) |
| 71 | #define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A) |
| 72 | #define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B) |
| 73 | #define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C) |
| 74 | #define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D) |
| 75 | #define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E) |
| 76 | #define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F) |
| 77 | #define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020) |
| 78 | #define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021) |
| 79 | #define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022) |
| 80 | #define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023) |
| 81 | #define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024) |
| 82 | #define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025) |
| 83 | |
| 84 | #define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028) |
| 85 | #define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029) |
| 86 | #define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A) |
| 87 | #define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B) |
| 88 | #define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C) |
| 89 | #define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D) |
| 90 | #define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E) |
| 91 | #define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F) |
| 92 | #define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030) |
| 93 | #define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031) |
| 94 | #define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032) |
| 95 | #define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033) |
| 96 | #define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034) |
| 97 | #define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035) |
| 98 | #define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036) |
| 99 | #define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037) |
| 100 | #define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038) |
| 101 | #define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039) |
| 102 | |
| 103 | #define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028) |
| 104 | #define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029) |
| 105 | #define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A) |
| 106 | #define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B) |
| 107 | #define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C) |
| 108 | #define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D) |
| 109 | #define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E) |
| 110 | #define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F) |
| 111 | #define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030) |
| 112 | #define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031) |
| 113 | #define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032) |
| 114 | #define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033) |
| 115 | #define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034) |
| 116 | #define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035) |
| 117 | #define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036) |
| 118 | #define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037) |
| 119 | #define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038) |
| 120 | #define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039) |
| 121 | |
| 122 | #define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C) |
| 123 | #define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D) |
| 124 | #define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E) |
| 125 | #define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F) |
| 126 | #define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040) |
| 127 | #define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041) |
| 128 | #define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042) |
| 129 | #define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043) |
| 130 | #define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044) |
| 131 | #define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045) |
| 132 | #define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046) |
| 133 | #define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047) |
| 134 | #define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048) |
| 135 | #define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049) |
| 136 | #define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A) |
| 137 | #define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B) |
| 138 | #define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C) |
| 139 | #define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D) |
| 140 | |
| 141 | #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) |
| 142 | #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) |
| 143 | #define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052) |
| 144 | #define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054) |
| 145 | #define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055) |
| 146 | #define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056) |
| 147 | #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058) |
| 148 | #define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059) |
| 149 | #define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A) |
| 150 | #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) |
| 151 | #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) |
| 152 | |
| 153 | /* |
| 154 | * Edge Port registers |
| 155 | */ |
| 156 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) |
| 157 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002) |
| 158 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003) |
| 159 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004) |
| 160 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005) |
| 161 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006) |
| 162 | |
| 163 | /* |
| 164 | * Queued ADC registers |
| 165 | */ |
| 166 | #define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006) |
| 167 | #define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007) |
| 168 | #define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008) |
| 169 | #define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009) |
| 170 | |
| 171 | /* |
| 172 | * General Purpose Timers registers |
| 173 | */ |
| 174 | #define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D) |
| 175 | #define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E) |
| 176 | #define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D) |
| 177 | #define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E) |
| 178 | /* |
| 179 | * |
| 180 | * definitions for generic gpio support |
| 181 | * |
| 182 | */ |
| 183 | #define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */ |
| 184 | #define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */ |
| 185 | #define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */ |
| 186 | #define MCFGPIO_SETR MCFGPIO_SETA /* set output */ |
| 187 | #define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */ |
| 188 | |
| 189 | #define MCFGPIO_IRQ_MAX 8 |
| 190 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 191 | #define MCFGPIO_PIN_MAX 180 |
| 192 | |
| 193 | |
| 194 | /* |
| Greg Ungerer | 7ce4d42 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 195 | * Derek Cheung - 6 Feb 2005 |
| 196 | * add I2C and QSPI register definition using Freescale's MCF5282 |
| 197 | */ |
| 198 | /* set Port AS pin for I2C or UART */ |
| 199 | #define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) |
| 200 | |
| Greg Ungerer | 8bb2518 | 2007-03-07 11:28:13 +1000 | [diff] [blame] | 201 | /* Port UA Pin Assignment Register (8 Bit) */ |
| 202 | #define MCF5282_GPIO_PUAPAR 0x10005C |
| 203 | |
| Greg Ungerer | 7ce4d42 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 204 | /* Interrupt Mask Register Register Low */ |
| 205 | #define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) |
| 206 | /* Interrupt Control Register 7 */ |
| 207 | #define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) |
| 208 | |
| 209 | |
| Greg Ungerer | dd65b1d | 2009-04-30 23:15:56 +1000 | [diff] [blame] | 210 | /* |
| 211 | * Reset Control Unit (relative to IPSBAR). |
| 212 | */ |
| 213 | #define MCF_RCR 0x110000 |
| 214 | #define MCF_RSR 0x110001 |
| 215 | |
| 216 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 217 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| Greg Ungerer | 7ce4d42 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 218 | |
| 219 | /********************************************************************* |
| 220 | * |
| 221 | * Inter-IC (I2C) Module |
| 222 | * |
| 223 | *********************************************************************/ |
| 224 | /* Read/Write access macros for general use */ |
| 225 | #define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address |
| 226 | #define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider |
| 227 | #define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control |
| 228 | #define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status |
| 229 | #define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O |
| 230 | |
| 231 | /* Bit level definitions and macros */ |
| 232 | #define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) |
| 233 | |
| 234 | #define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) |
| 235 | |
| 236 | #define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable |
| 237 | #define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable |
| 238 | #define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode |
| 239 | #define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode |
| 240 | #define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable |
| 241 | #define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start |
| 242 | |
| 243 | #define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit |
| 244 | #define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave |
| 245 | #define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy |
| 246 | #define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost |
| 247 | #define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write |
| 248 | #define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt |
| 249 | #define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge |
| 250 | |
| 251 | |
| 252 | |
| 253 | /********************************************************************* |
| 254 | * |
| 255 | * Queued Serial Peripheral Interface (QSPI) Module |
| 256 | * |
| 257 | *********************************************************************/ |
| 258 | /* Derek - 21 Feb 2005 */ |
| 259 | /* change to the format used in I2C */ |
| 260 | /* Read/Write access macros for general use */ |
| 261 | #define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 |
| 262 | #define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 |
| 263 | #define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 |
| 264 | #define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C |
| 265 | #define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 |
| 266 | #define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 |
| 267 | #define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 |
| 268 | |
| 269 | /* Bit level definitions and macros */ |
| 270 | #define MCF5282_QSPI_QMR_MSTR (0x8000) |
| 271 | #define MCF5282_QSPI_QMR_DOHIE (0x4000) |
| 272 | #define MCF5282_QSPI_QMR_BITS_16 (0x0000) |
| 273 | #define MCF5282_QSPI_QMR_BITS_8 (0x2000) |
| 274 | #define MCF5282_QSPI_QMR_BITS_9 (0x2400) |
| 275 | #define MCF5282_QSPI_QMR_BITS_10 (0x2800) |
| 276 | #define MCF5282_QSPI_QMR_BITS_11 (0x2C00) |
| 277 | #define MCF5282_QSPI_QMR_BITS_12 (0x3000) |
| 278 | #define MCF5282_QSPI_QMR_BITS_13 (0x3400) |
| 279 | #define MCF5282_QSPI_QMR_BITS_14 (0x3800) |
| 280 | #define MCF5282_QSPI_QMR_BITS_15 (0x3C00) |
| 281 | #define MCF5282_QSPI_QMR_CPOL (0x0200) |
| 282 | #define MCF5282_QSPI_QMR_CPHA (0x0100) |
| 283 | #define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) |
| 284 | |
| 285 | #define MCF5282_QSPI_QDLYR_SPE (0x80) |
| 286 | #define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) |
| 287 | #define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) |
| 288 | |
| 289 | #define MCF5282_QSPI_QWR_HALT (0x8000) |
| 290 | #define MCF5282_QSPI_QWR_WREN (0x4000) |
| 291 | #define MCF5282_QSPI_QWR_WRTO (0x2000) |
| 292 | #define MCF5282_QSPI_QWR_CSIV (0x1000) |
| 293 | #define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) |
| 294 | #define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) |
| 295 | #define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) |
| 296 | |
| 297 | #define MCF5282_QSPI_QIR_WCEFB (0x8000) |
| 298 | #define MCF5282_QSPI_QIR_ABRTB (0x4000) |
| 299 | #define MCF5282_QSPI_QIR_ABRTL (0x1000) |
| 300 | #define MCF5282_QSPI_QIR_WCEFE (0x0800) |
| 301 | #define MCF5282_QSPI_QIR_ABRTE (0x0400) |
| 302 | #define MCF5282_QSPI_QIR_SPIFE (0x0100) |
| 303 | #define MCF5282_QSPI_QIR_WCEF (0x0008) |
| 304 | #define MCF5282_QSPI_QIR_ABRT (0x0004) |
| 305 | #define MCF5282_QSPI_QIR_SPIF (0x0001) |
| 306 | |
| 307 | #define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) |
| 308 | |
| 309 | #define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) |
| 310 | #define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) |
| 311 | #define MCF5282_QSPI_QCR_CONT (0x8000) |
| 312 | #define MCF5282_QSPI_QCR_BITSE (0x4000) |
| 313 | #define MCF5282_QSPI_QCR_DT (0x2000) |
| 314 | #define MCF5282_QSPI_QCR_DSCK (0x1000) |
| 315 | #define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) |
| 316 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | /****************************************************************************/ |
| 318 | #endif /* m528xsim_h */ |