Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 1993-2003 NVIDIA, Corporation |
| 3 | * Copyright 2006 Dave Airlie |
| 4 | * Copyright 2007 Maarten Maathuis |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "drmP.h" |
| 27 | #include "drm_crtc_helper.h" |
| 28 | |
| 29 | #include "nouveau_drv.h" |
| 30 | #include "nouveau_encoder.h" |
| 31 | #include "nouveau_connector.h" |
| 32 | #include "nouveau_crtc.h" |
| 33 | #include "nouveau_fb.h" |
| 34 | #include "nouveau_hw.h" |
| 35 | #include "nvreg.h" |
| 36 | |
| 37 | static int |
| 38 | nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 39 | struct drm_framebuffer *old_fb); |
| 40 | |
| 41 | static void |
| 42 | crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) |
| 43 | { |
| 44 | NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, |
| 45 | crtcstate->CRTC[index]); |
| 46 | } |
| 47 | |
| 48 | static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) |
| 49 | { |
| 50 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 51 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 52 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 53 | |
| 54 | regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; |
| 55 | if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { |
| 56 | regp->CRTC[NV_CIO_CRE_CSB] = 0x80; |
| 57 | regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; |
| 58 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); |
| 59 | } |
| 60 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); |
| 61 | } |
| 62 | |
| 63 | static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) |
| 64 | { |
| 65 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 66 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 67 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 68 | |
| 69 | nv_crtc->sharpness = level; |
| 70 | if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ |
| 71 | level += 0x40; |
| 72 | regp->ramdac_634 = level; |
| 73 | NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); |
| 74 | } |
| 75 | |
| 76 | #define PLLSEL_VPLL1_MASK \ |
| 77 | (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ |
| 78 | | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) |
| 79 | #define PLLSEL_VPLL2_MASK \ |
| 80 | (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ |
| 81 | | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) |
| 82 | #define PLLSEL_TV_MASK \ |
| 83 | (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ |
| 84 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ |
| 85 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ |
| 86 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) |
| 87 | |
| 88 | /* NV4x 0x40.. pll notes: |
| 89 | * gpu pll: 0x4000 + 0x4004 |
| 90 | * ?gpu? pll: 0x4008 + 0x400c |
| 91 | * vpll1: 0x4010 + 0x4014 |
| 92 | * vpll2: 0x4018 + 0x401c |
| 93 | * mpll: 0x4020 + 0x4024 |
| 94 | * mpll: 0x4038 + 0x403c |
| 95 | * |
| 96 | * the first register of each pair has some unknown details: |
| 97 | * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) |
| 98 | * bits 20-23: (mpll) something to do with post divider? |
| 99 | * bits 28-31: related to single stage mode? (bit 8/12) |
| 100 | */ |
| 101 | |
| 102 | static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) |
| 103 | { |
| 104 | struct drm_device *dev = crtc->dev; |
| 105 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 106 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 107 | struct nv04_mode_state *state = &dev_priv->mode_reg; |
| 108 | struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; |
| 109 | struct nouveau_pll_vals *pv = ®p->pllvals; |
| 110 | struct pll_lims pll_lim; |
| 111 | |
| 112 | if (get_pll_limits(dev, nv_crtc->index ? VPLL2 : VPLL1, &pll_lim)) |
| 113 | return; |
| 114 | |
| 115 | /* NM2 == 0 is used to determine single stage mode on two stage plls */ |
| 116 | pv->NM2 = 0; |
| 117 | |
| 118 | /* for newer nv4x the blob uses only the first stage of the vpll below a |
| 119 | * certain clock. for a certain nv4b this is 150MHz. since the max |
| 120 | * output frequency of the first stage for this card is 300MHz, it is |
| 121 | * assumed the threshold is given by vco1 maxfreq/2 |
| 122 | */ |
| 123 | /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, |
| 124 | * not 8, others unknown), the blob always uses both plls. no problem |
| 125 | * has yet been observed in allowing the use a single stage pll on all |
| 126 | * nv43 however. the behaviour of single stage use is untested on nv40 |
| 127 | */ |
| 128 | if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2)) |
| 129 | memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); |
| 130 | |
| 131 | if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv)) |
| 132 | return; |
| 133 | |
| 134 | state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; |
| 135 | |
| 136 | /* The blob uses this always, so let's do the same */ |
| 137 | if (dev_priv->card_type == NV_40) |
| 138 | state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; |
| 139 | /* again nv40 and some nv43 act more like nv3x as described above */ |
| 140 | if (dev_priv->chipset < 0x41) |
| 141 | state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | |
| 142 | NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; |
| 143 | state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; |
| 144 | |
| 145 | if (pv->NM2) |
| 146 | NV_TRACE(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", |
| 147 | pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); |
| 148 | else |
| 149 | NV_TRACE(dev, "vpll: n %d m %d log2p %d\n", |
| 150 | pv->N1, pv->M1, pv->log2P); |
| 151 | |
| 152 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); |
| 153 | } |
| 154 | |
| 155 | static void |
| 156 | nv_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 157 | { |
| 158 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 159 | struct drm_device *dev = crtc->dev; |
| 160 | unsigned char seq1 = 0, crtc17 = 0; |
| 161 | unsigned char crtc1A; |
| 162 | |
| 163 | NV_TRACE(dev, "Setting dpms mode %d on CRTC %d\n", mode, |
| 164 | nv_crtc->index); |
| 165 | |
| 166 | if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ |
| 167 | return; |
| 168 | |
| 169 | nv_crtc->last_dpms = mode; |
| 170 | |
| 171 | if (nv_two_heads(dev)) |
| 172 | NVSetOwner(dev, nv_crtc->index); |
| 173 | |
| 174 | /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ |
| 175 | crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, |
| 176 | NV_CIO_CRE_RPC1_INDEX) & ~0xC0; |
| 177 | switch (mode) { |
| 178 | case DRM_MODE_DPMS_STANDBY: |
| 179 | /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ |
| 180 | seq1 = 0x20; |
| 181 | crtc17 = 0x80; |
| 182 | crtc1A |= 0x80; |
| 183 | break; |
| 184 | case DRM_MODE_DPMS_SUSPEND: |
| 185 | /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ |
| 186 | seq1 = 0x20; |
| 187 | crtc17 = 0x80; |
| 188 | crtc1A |= 0x40; |
| 189 | break; |
| 190 | case DRM_MODE_DPMS_OFF: |
| 191 | /* Screen: Off; HSync: Off, VSync: Off */ |
| 192 | seq1 = 0x20; |
| 193 | crtc17 = 0x00; |
| 194 | crtc1A |= 0xC0; |
| 195 | break; |
| 196 | case DRM_MODE_DPMS_ON: |
| 197 | default: |
| 198 | /* Screen: On; HSync: On, VSync: On */ |
| 199 | seq1 = 0x00; |
| 200 | crtc17 = 0x80; |
| 201 | break; |
| 202 | } |
| 203 | |
| 204 | NVVgaSeqReset(dev, nv_crtc->index, true); |
| 205 | /* Each head has it's own sequencer, so we can turn it off when we want */ |
| 206 | seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); |
| 207 | NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); |
| 208 | crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); |
| 209 | mdelay(10); |
| 210 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); |
| 211 | NVVgaSeqReset(dev, nv_crtc->index, false); |
| 212 | |
| 213 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); |
| 214 | } |
| 215 | |
| 216 | static bool |
| 217 | nv_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 218 | struct drm_display_mode *adjusted_mode) |
| 219 | { |
| 220 | return true; |
| 221 | } |
| 222 | |
| 223 | static void |
| 224 | nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) |
| 225 | { |
| 226 | struct drm_device *dev = crtc->dev; |
| 227 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 228 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 229 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 230 | struct drm_framebuffer *fb = crtc->fb; |
| 231 | |
| 232 | /* Calculate our timings */ |
| 233 | int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; |
| 234 | int horizStart = (mode->crtc_hsync_start >> 3) - 1; |
| 235 | int horizEnd = (mode->crtc_hsync_end >> 3) - 1; |
| 236 | int horizTotal = (mode->crtc_htotal >> 3) - 5; |
| 237 | int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; |
| 238 | int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; |
| 239 | int vertDisplay = mode->crtc_vdisplay - 1; |
| 240 | int vertStart = mode->crtc_vsync_start - 1; |
| 241 | int vertEnd = mode->crtc_vsync_end - 1; |
| 242 | int vertTotal = mode->crtc_vtotal - 2; |
| 243 | int vertBlankStart = mode->crtc_vdisplay - 1; |
| 244 | int vertBlankEnd = mode->crtc_vtotal - 1; |
| 245 | |
| 246 | struct drm_encoder *encoder; |
| 247 | bool fp_output = false; |
| 248 | |
| 249 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 250 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 251 | |
| 252 | if (encoder->crtc == crtc && |
| 253 | (nv_encoder->dcb->type == OUTPUT_LVDS || |
| 254 | nv_encoder->dcb->type == OUTPUT_TMDS)) |
| 255 | fp_output = true; |
| 256 | } |
| 257 | |
| 258 | if (fp_output) { |
| 259 | vertStart = vertTotal - 3; |
| 260 | vertEnd = vertTotal - 2; |
| 261 | vertBlankStart = vertStart; |
| 262 | horizStart = horizTotal - 5; |
| 263 | horizEnd = horizTotal - 2; |
| 264 | horizBlankEnd = horizTotal + 4; |
| 265 | #if 0 |
| 266 | if (dev->overlayAdaptor && dev_priv->card_type >= NV_10) |
| 267 | /* This reportedly works around some video overlay bandwidth problems */ |
| 268 | horizTotal += 2; |
| 269 | #endif |
| 270 | } |
| 271 | |
| 272 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 273 | vertTotal |= 1; |
| 274 | |
| 275 | #if 0 |
| 276 | ErrorF("horizDisplay: 0x%X \n", horizDisplay); |
| 277 | ErrorF("horizStart: 0x%X \n", horizStart); |
| 278 | ErrorF("horizEnd: 0x%X \n", horizEnd); |
| 279 | ErrorF("horizTotal: 0x%X \n", horizTotal); |
| 280 | ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); |
| 281 | ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); |
| 282 | ErrorF("vertDisplay: 0x%X \n", vertDisplay); |
| 283 | ErrorF("vertStart: 0x%X \n", vertStart); |
| 284 | ErrorF("vertEnd: 0x%X \n", vertEnd); |
| 285 | ErrorF("vertTotal: 0x%X \n", vertTotal); |
| 286 | ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); |
| 287 | ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); |
| 288 | #endif |
| 289 | |
| 290 | /* |
| 291 | * compute correct Hsync & Vsync polarity |
| 292 | */ |
| 293 | if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) |
| 294 | && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { |
| 295 | |
| 296 | regp->MiscOutReg = 0x23; |
| 297 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 298 | regp->MiscOutReg |= 0x40; |
| 299 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 300 | regp->MiscOutReg |= 0x80; |
| 301 | } else { |
| 302 | int vdisplay = mode->vdisplay; |
| 303 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 304 | vdisplay *= 2; |
| 305 | if (mode->vscan > 1) |
| 306 | vdisplay *= mode->vscan; |
| 307 | if (vdisplay < 400) |
| 308 | regp->MiscOutReg = 0xA3; /* +hsync -vsync */ |
| 309 | else if (vdisplay < 480) |
| 310 | regp->MiscOutReg = 0x63; /* -hsync +vsync */ |
| 311 | else if (vdisplay < 768) |
| 312 | regp->MiscOutReg = 0xE3; /* -hsync -vsync */ |
| 313 | else |
| 314 | regp->MiscOutReg = 0x23; /* +hsync +vsync */ |
| 315 | } |
| 316 | |
| 317 | regp->MiscOutReg |= (mode->clock_index & 0x03) << 2; |
| 318 | |
| 319 | /* |
| 320 | * Time Sequencer |
| 321 | */ |
| 322 | regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; |
| 323 | /* 0x20 disables the sequencer */ |
| 324 | if (mode->flags & DRM_MODE_FLAG_CLKDIV2) |
| 325 | regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; |
| 326 | else |
| 327 | regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; |
| 328 | regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; |
| 329 | regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; |
| 330 | regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; |
| 331 | |
| 332 | /* |
| 333 | * CRTC |
| 334 | */ |
| 335 | regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; |
| 336 | regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; |
| 337 | regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; |
| 338 | regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | |
| 339 | XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); |
| 340 | regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; |
| 341 | regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | |
| 342 | XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); |
| 343 | regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; |
| 344 | regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | |
| 345 | XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | |
| 346 | XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | |
| 347 | (1 << 4) | |
| 348 | XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | |
| 349 | XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | |
| 350 | XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | |
| 351 | XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); |
| 352 | regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; |
| 353 | regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | |
| 354 | 1 << 6 | |
| 355 | XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); |
| 356 | regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; |
| 357 | regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; |
| 358 | regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; |
| 359 | regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; |
| 360 | regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; |
| 361 | regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; |
| 362 | regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; |
| 363 | regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); |
| 364 | regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; |
| 365 | /* framebuffer can be larger than crtc scanout area. */ |
| 366 | regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8; |
| 367 | regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; |
| 368 | regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; |
| 369 | regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; |
| 370 | regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; |
| 371 | regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; |
| 372 | |
| 373 | /* |
| 374 | * Some extended CRTC registers (they are not saved with the rest of the vga regs). |
| 375 | */ |
| 376 | |
| 377 | /* framebuffer can be larger than crtc scanout area. */ |
| 378 | regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); |
| 379 | regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? |
| 380 | MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; |
| 381 | regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | |
| 382 | XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | |
| 383 | XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | |
| 384 | XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | |
| 385 | XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); |
| 386 | regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | |
| 387 | XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | |
| 388 | XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | |
| 389 | XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); |
| 390 | regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | |
| 391 | XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | |
| 392 | XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | |
| 393 | XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); |
| 394 | |
| 395 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 396 | horizTotal = (horizTotal >> 1) & ~1; |
| 397 | regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; |
| 398 | regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); |
| 399 | } else |
| 400 | regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ |
| 401 | |
| 402 | /* |
| 403 | * Graphics Display Controller |
| 404 | */ |
| 405 | regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; |
| 406 | regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; |
| 407 | regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; |
| 408 | regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; |
| 409 | regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; |
| 410 | regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ |
| 411 | regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ |
| 412 | regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; |
| 413 | regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; |
| 414 | |
| 415 | regp->Attribute[0] = 0x00; /* standard colormap translation */ |
| 416 | regp->Attribute[1] = 0x01; |
| 417 | regp->Attribute[2] = 0x02; |
| 418 | regp->Attribute[3] = 0x03; |
| 419 | regp->Attribute[4] = 0x04; |
| 420 | regp->Attribute[5] = 0x05; |
| 421 | regp->Attribute[6] = 0x06; |
| 422 | regp->Attribute[7] = 0x07; |
| 423 | regp->Attribute[8] = 0x08; |
| 424 | regp->Attribute[9] = 0x09; |
| 425 | regp->Attribute[10] = 0x0A; |
| 426 | regp->Attribute[11] = 0x0B; |
| 427 | regp->Attribute[12] = 0x0C; |
| 428 | regp->Attribute[13] = 0x0D; |
| 429 | regp->Attribute[14] = 0x0E; |
| 430 | regp->Attribute[15] = 0x0F; |
| 431 | regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ |
| 432 | /* Non-vga */ |
| 433 | regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; |
| 434 | regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ |
| 435 | regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; |
| 436 | regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; |
| 437 | } |
| 438 | |
| 439 | /** |
| 440 | * Sets up registers for the given mode/adjusted_mode pair. |
| 441 | * |
| 442 | * The clocks, CRTCs and outputs attached to this CRTC must be off. |
| 443 | * |
| 444 | * This shouldn't enable any clocks, CRTCs, or outputs, but they should |
| 445 | * be easily turned on/off after this. |
| 446 | */ |
| 447 | static void |
| 448 | nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) |
| 449 | { |
| 450 | struct drm_device *dev = crtc->dev; |
| 451 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 452 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 453 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 454 | struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index]; |
| 455 | struct drm_encoder *encoder; |
| 456 | bool lvds_output = false, tmds_output = false, tv_output = false, |
| 457 | off_chip_digital = false; |
| 458 | |
| 459 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 460 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 461 | bool digital = false; |
| 462 | |
| 463 | if (encoder->crtc != crtc) |
| 464 | continue; |
| 465 | |
| 466 | if (nv_encoder->dcb->type == OUTPUT_LVDS) |
| 467 | digital = lvds_output = true; |
| 468 | if (nv_encoder->dcb->type == OUTPUT_TV) |
| 469 | tv_output = true; |
| 470 | if (nv_encoder->dcb->type == OUTPUT_TMDS) |
| 471 | digital = tmds_output = true; |
| 472 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) |
| 473 | off_chip_digital = true; |
| 474 | } |
| 475 | |
| 476 | /* Registers not directly related to the (s)vga mode */ |
| 477 | |
| 478 | /* What is the meaning of this register? */ |
| 479 | /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ |
| 480 | regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); |
| 481 | |
| 482 | regp->crtc_eng_ctrl = 0; |
| 483 | /* Except for rare conditions I2C is enabled on the primary crtc */ |
| 484 | if (nv_crtc->index == 0) |
| 485 | regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; |
| 486 | #if 0 |
| 487 | /* Set overlay to desired crtc. */ |
| 488 | if (dev->overlayAdaptor) { |
| 489 | NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); |
| 490 | if (pPriv->overlayCRTC == nv_crtc->index) |
| 491 | regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; |
| 492 | } |
| 493 | #endif |
| 494 | |
| 495 | /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ |
| 496 | regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | |
| 497 | NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | |
| 498 | NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; |
| 499 | if (dev_priv->chipset >= 0x11) |
| 500 | regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; |
| 501 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 502 | regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; |
| 503 | |
| 504 | /* Unblock some timings */ |
| 505 | regp->CRTC[NV_CIO_CRE_53] = 0; |
| 506 | regp->CRTC[NV_CIO_CRE_54] = 0; |
| 507 | |
| 508 | /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ |
| 509 | if (lvds_output) |
| 510 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; |
| 511 | else if (tmds_output) |
| 512 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; |
| 513 | else |
| 514 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; |
| 515 | |
| 516 | /* These values seem to vary */ |
| 517 | /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ |
| 518 | regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; |
| 519 | |
| 520 | nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); |
| 521 | |
| 522 | /* probably a scratch reg, but kept for cargo-cult purposes: |
| 523 | * bit0: crtc0?, head A |
| 524 | * bit6: lvds, head A |
| 525 | * bit7: (only in X), head A |
| 526 | */ |
| 527 | if (nv_crtc->index == 0) |
| 528 | regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; |
| 529 | |
| 530 | /* The blob seems to take the current value from crtc 0, add 4 to that |
| 531 | * and reuse the old value for crtc 1 */ |
| 532 | regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; |
| 533 | if (!nv_crtc->index) |
| 534 | regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; |
| 535 | |
| 536 | /* the blob sometimes sets |= 0x10 (which is the same as setting |= |
| 537 | * 1 << 30 on 0x60.830), for no apparent reason */ |
| 538 | regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; |
| 539 | |
| 540 | regp->crtc_830 = mode->crtc_vdisplay - 3; |
| 541 | regp->crtc_834 = mode->crtc_vdisplay - 1; |
| 542 | |
| 543 | if (dev_priv->card_type == NV_40) |
| 544 | /* This is what the blob does */ |
| 545 | regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); |
| 546 | |
| 547 | if (dev_priv->card_type >= NV_30) |
| 548 | regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); |
| 549 | |
| 550 | regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC; |
| 551 | |
| 552 | /* Some misc regs */ |
| 553 | if (dev_priv->card_type == NV_40) { |
| 554 | regp->CRTC[NV_CIO_CRE_85] = 0xFF; |
| 555 | regp->CRTC[NV_CIO_CRE_86] = 0x1; |
| 556 | } |
| 557 | |
| 558 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8; |
| 559 | /* Enable slaved mode (called MODE_TV in nv4ref.h) */ |
| 560 | if (lvds_output || tmds_output || tv_output) |
| 561 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); |
| 562 | |
| 563 | /* Generic PRAMDAC regs */ |
| 564 | |
| 565 | if (dev_priv->card_type >= NV_10) |
| 566 | /* Only bit that bios and blob set. */ |
| 567 | regp->nv10_cursync = (1 << 25); |
| 568 | |
| 569 | regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | |
| 570 | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | |
| 571 | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; |
| 572 | if (crtc->fb->depth == 16) |
| 573 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
| 574 | if (dev_priv->chipset >= 0x11) |
| 575 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; |
| 576 | |
| 577 | regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ |
| 578 | regp->tv_setup = 0; |
| 579 | |
| 580 | nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); |
| 581 | |
| 582 | /* Some values the blob sets */ |
| 583 | regp->ramdac_8c0 = 0x100; |
| 584 | regp->ramdac_a20 = 0x0; |
| 585 | regp->ramdac_a24 = 0xfffff; |
| 586 | regp->ramdac_a34 = 0x1; |
| 587 | } |
| 588 | |
| 589 | /** |
| 590 | * Sets up registers for the given mode/adjusted_mode pair. |
| 591 | * |
| 592 | * The clocks, CRTCs and outputs attached to this CRTC must be off. |
| 593 | * |
| 594 | * This shouldn't enable any clocks, CRTCs, or outputs, but they should |
| 595 | * be easily turned on/off after this. |
| 596 | */ |
| 597 | static int |
| 598 | nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 599 | struct drm_display_mode *adjusted_mode, |
| 600 | int x, int y, struct drm_framebuffer *old_fb) |
| 601 | { |
| 602 | struct drm_device *dev = crtc->dev; |
| 603 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 604 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 605 | |
| 606 | NV_DEBUG(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); |
| 607 | drm_mode_debug_printmodeline(adjusted_mode); |
| 608 | |
| 609 | /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ |
| 610 | nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); |
| 611 | |
| 612 | nv_crtc_mode_set_vga(crtc, adjusted_mode); |
| 613 | /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ |
| 614 | if (dev_priv->card_type == NV_40) |
| 615 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); |
| 616 | nv_crtc_mode_set_regs(crtc, adjusted_mode); |
| 617 | nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); |
| 618 | return 0; |
| 619 | } |
| 620 | |
| 621 | static void nv_crtc_save(struct drm_crtc *crtc) |
| 622 | { |
| 623 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 624 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 625 | struct nv04_mode_state *state = &dev_priv->mode_reg; |
| 626 | struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; |
| 627 | struct nv04_mode_state *saved = &dev_priv->saved_reg; |
| 628 | struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; |
| 629 | |
| 630 | if (nv_two_heads(crtc->dev)) |
| 631 | NVSetOwner(crtc->dev, nv_crtc->index); |
| 632 | |
| 633 | nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); |
| 634 | |
| 635 | /* init some state to saved value */ |
| 636 | state->sel_clk = saved->sel_clk & ~(0x5 << 16); |
| 637 | crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; |
| 638 | state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); |
| 639 | crtc_state->gpio_ext = crtc_saved->gpio_ext; |
| 640 | } |
| 641 | |
| 642 | static void nv_crtc_restore(struct drm_crtc *crtc) |
| 643 | { |
| 644 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 645 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 646 | int head = nv_crtc->index; |
| 647 | uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; |
| 648 | |
| 649 | if (nv_two_heads(crtc->dev)) |
| 650 | NVSetOwner(crtc->dev, head); |
| 651 | |
| 652 | nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg); |
| 653 | nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); |
| 654 | |
| 655 | nv_crtc->last_dpms = NV_DPMS_CLEARED; |
| 656 | } |
| 657 | |
| 658 | static void nv_crtc_prepare(struct drm_crtc *crtc) |
| 659 | { |
| 660 | struct drm_device *dev = crtc->dev; |
| 661 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 662 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 663 | struct drm_crtc_helper_funcs *funcs = crtc->helper_private; |
| 664 | |
| 665 | if (nv_two_heads(dev)) |
| 666 | NVSetOwner(dev, nv_crtc->index); |
| 667 | |
| 668 | funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 669 | |
| 670 | NVBlankScreen(dev, nv_crtc->index, true); |
| 671 | |
| 672 | /* Some more preperation. */ |
| 673 | NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); |
| 674 | if (dev_priv->card_type == NV_40) { |
| 675 | uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); |
| 676 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | static void nv_crtc_commit(struct drm_crtc *crtc) |
| 681 | { |
| 682 | struct drm_device *dev = crtc->dev; |
| 683 | struct drm_crtc_helper_funcs *funcs = crtc->helper_private; |
| 684 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 685 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 686 | |
| 687 | nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg); |
| 688 | nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); |
| 689 | |
| 690 | #ifdef __BIG_ENDIAN |
| 691 | /* turn on LFB swapping */ |
| 692 | { |
| 693 | uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); |
| 694 | tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); |
| 695 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); |
| 696 | } |
| 697 | #endif |
| 698 | |
| 699 | funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 700 | } |
| 701 | |
| 702 | static void nv_crtc_destroy(struct drm_crtc *crtc) |
| 703 | { |
| 704 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 705 | |
| 706 | NV_DEBUG(crtc->dev, "\n"); |
| 707 | |
| 708 | if (!nv_crtc) |
| 709 | return; |
| 710 | |
| 711 | drm_crtc_cleanup(crtc); |
| 712 | |
| 713 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
| 714 | kfree(nv_crtc); |
| 715 | } |
| 716 | |
| 717 | static void |
| 718 | nv_crtc_gamma_load(struct drm_crtc *crtc) |
| 719 | { |
| 720 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 721 | struct drm_device *dev = nv_crtc->base.dev; |
| 722 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 723 | struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; |
| 724 | int i; |
| 725 | |
| 726 | rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC; |
| 727 | for (i = 0; i < 256; i++) { |
| 728 | rgbs[i].r = nv_crtc->lut.r[i] >> 8; |
| 729 | rgbs[i].g = nv_crtc->lut.g[i] >> 8; |
| 730 | rgbs[i].b = nv_crtc->lut.b[i] >> 8; |
| 731 | } |
| 732 | |
| 733 | nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg); |
| 734 | } |
| 735 | |
| 736 | static void |
| 737 | nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t size) |
| 738 | { |
| 739 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 740 | int i; |
| 741 | |
| 742 | if (size != 256) |
| 743 | return; |
| 744 | |
| 745 | for (i = 0; i < 256; i++) { |
| 746 | nv_crtc->lut.r[i] = r[i]; |
| 747 | nv_crtc->lut.g[i] = g[i]; |
| 748 | nv_crtc->lut.b[i] = b[i]; |
| 749 | } |
| 750 | |
| 751 | /* We need to know the depth before we upload, but it's possible to |
| 752 | * get called before a framebuffer is bound. If this is the case, |
| 753 | * mark the lut values as dirty by setting depth==0, and it'll be |
| 754 | * uploaded on the first mode_set_base() |
| 755 | */ |
| 756 | if (!nv_crtc->base.fb) { |
| 757 | nv_crtc->lut.depth = 0; |
| 758 | return; |
| 759 | } |
| 760 | |
| 761 | nv_crtc_gamma_load(crtc); |
| 762 | } |
| 763 | |
| 764 | static int |
| 765 | nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 766 | struct drm_framebuffer *old_fb) |
| 767 | { |
| 768 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 769 | struct drm_device *dev = crtc->dev; |
| 770 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 771 | struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; |
| 772 | struct drm_framebuffer *drm_fb = nv_crtc->base.fb; |
| 773 | struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); |
| 774 | int arb_burst, arb_lwm; |
| 775 | int ret; |
| 776 | |
| 777 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); |
| 778 | if (ret) |
| 779 | return ret; |
| 780 | |
| 781 | if (old_fb) { |
| 782 | struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb); |
| 783 | nouveau_bo_unpin(ofb->nvbo); |
| 784 | } |
| 785 | |
| 786 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
| 787 | |
| 788 | if (nv_crtc->lut.depth != drm_fb->depth) { |
| 789 | nv_crtc->lut.depth = drm_fb->depth; |
| 790 | nv_crtc_gamma_load(crtc); |
| 791 | } |
| 792 | |
| 793 | /* Update the framebuffer format. */ |
| 794 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; |
| 795 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; |
| 796 | regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
| 797 | if (crtc->fb->depth == 16) |
| 798 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
| 799 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); |
| 800 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, |
| 801 | regp->ramdac_gen_ctrl); |
| 802 | |
| 803 | regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3; |
| 804 | regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = |
| 805 | XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); |
| 806 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); |
| 807 | crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); |
| 808 | |
| 809 | /* Update the framebuffer location. */ |
| 810 | regp->fb_start = nv_crtc->fb.offset & ~3; |
| 811 | regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8); |
| 812 | NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_START, regp->fb_start); |
| 813 | |
| 814 | /* Update the arbitration parameters. */ |
| 815 | nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, |
| 816 | &arb_burst, &arb_lwm); |
| 817 | |
| 818 | regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; |
| 819 | regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; |
| 820 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); |
| 821 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); |
| 822 | |
| 823 | if (dev_priv->card_type >= NV_30) { |
| 824 | regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; |
| 825 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); |
| 826 | } |
| 827 | |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, |
| 832 | struct nouveau_bo *dst) |
| 833 | { |
| 834 | int width = nv_cursor_width(dev); |
| 835 | uint32_t pixel; |
| 836 | int i, j; |
| 837 | |
| 838 | for (i = 0; i < width; i++) { |
| 839 | for (j = 0; j < width; j++) { |
| 840 | pixel = nouveau_bo_rd32(src, i*64 + j); |
| 841 | |
| 842 | nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 |
| 843 | | (pixel & 0xf80000) >> 9 |
| 844 | | (pixel & 0xf800) >> 6 |
| 845 | | (pixel & 0xf8) >> 3); |
| 846 | } |
| 847 | } |
| 848 | } |
| 849 | |
| 850 | static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, |
| 851 | struct nouveau_bo *dst) |
| 852 | { |
| 853 | uint32_t pixel; |
| 854 | int alpha, i; |
| 855 | |
| 856 | /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha |
| 857 | * cursors (though NPM in combination with fp dithering may not work on |
| 858 | * nv11, from "nv" driver history) |
| 859 | * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the |
| 860 | * blob uses, however we get given PM cursors so we use PM mode |
| 861 | */ |
| 862 | for (i = 0; i < 64 * 64; i++) { |
| 863 | pixel = nouveau_bo_rd32(src, i); |
| 864 | |
| 865 | /* hw gets unhappy if alpha <= rgb values. for a PM image "less |
| 866 | * than" shouldn't happen; fix "equal to" case by adding one to |
| 867 | * alpha channel (slightly inaccurate, but so is attempting to |
| 868 | * get back to NPM images, due to limits of integer precision) |
| 869 | */ |
| 870 | alpha = pixel >> 24; |
| 871 | if (alpha > 0 && alpha < 255) |
| 872 | pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); |
| 873 | |
| 874 | #ifdef __BIG_ENDIAN |
| 875 | { |
| 876 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 877 | |
| 878 | if (dev_priv->chipset == 0x11) { |
| 879 | pixel = ((pixel & 0x000000ff) << 24) | |
| 880 | ((pixel & 0x0000ff00) << 8) | |
| 881 | ((pixel & 0x00ff0000) >> 8) | |
| 882 | ((pixel & 0xff000000) >> 24); |
| 883 | } |
| 884 | } |
| 885 | #endif |
| 886 | |
| 887 | nouveau_bo_wr32(dst, i, pixel); |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | static int |
| 892 | nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
| 893 | uint32_t buffer_handle, uint32_t width, uint32_t height) |
| 894 | { |
| 895 | struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; |
| 896 | struct drm_device *dev = dev_priv->dev; |
| 897 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 898 | struct nouveau_bo *cursor = NULL; |
| 899 | struct drm_gem_object *gem; |
| 900 | int ret = 0; |
| 901 | |
| 902 | if (width != 64 || height != 64) |
| 903 | return -EINVAL; |
| 904 | |
| 905 | if (!buffer_handle) { |
| 906 | nv_crtc->cursor.hide(nv_crtc, true); |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
| 911 | if (!gem) |
| 912 | return -EINVAL; |
| 913 | cursor = nouveau_gem_object(gem); |
| 914 | |
| 915 | ret = nouveau_bo_map(cursor); |
| 916 | if (ret) |
| 917 | goto out; |
| 918 | |
| 919 | if (dev_priv->chipset >= 0x11) |
| 920 | nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); |
| 921 | else |
| 922 | nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); |
| 923 | |
| 924 | nouveau_bo_unmap(cursor); |
| 925 | nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; |
| 926 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); |
| 927 | nv_crtc->cursor.show(nv_crtc, true); |
| 928 | out: |
| 929 | mutex_lock(&dev->struct_mutex); |
| 930 | drm_gem_object_unreference(gem); |
| 931 | mutex_unlock(&dev->struct_mutex); |
| 932 | return ret; |
| 933 | } |
| 934 | |
| 935 | static int |
| 936 | nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 937 | { |
| 938 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 939 | |
| 940 | nv_crtc->cursor.set_pos(nv_crtc, x, y); |
| 941 | return 0; |
| 942 | } |
| 943 | |
| 944 | static const struct drm_crtc_funcs nv04_crtc_funcs = { |
| 945 | .save = nv_crtc_save, |
| 946 | .restore = nv_crtc_restore, |
| 947 | .cursor_set = nv04_crtc_cursor_set, |
| 948 | .cursor_move = nv04_crtc_cursor_move, |
| 949 | .gamma_set = nv_crtc_gamma_set, |
| 950 | .set_config = drm_crtc_helper_set_config, |
| 951 | .destroy = nv_crtc_destroy, |
| 952 | }; |
| 953 | |
| 954 | static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { |
| 955 | .dpms = nv_crtc_dpms, |
| 956 | .prepare = nv_crtc_prepare, |
| 957 | .commit = nv_crtc_commit, |
| 958 | .mode_fixup = nv_crtc_mode_fixup, |
| 959 | .mode_set = nv_crtc_mode_set, |
| 960 | .mode_set_base = nv04_crtc_mode_set_base, |
| 961 | .load_lut = nv_crtc_gamma_load, |
| 962 | }; |
| 963 | |
| 964 | int |
| 965 | nv04_crtc_create(struct drm_device *dev, int crtc_num) |
| 966 | { |
| 967 | struct nouveau_crtc *nv_crtc; |
| 968 | int ret, i; |
| 969 | |
| 970 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); |
| 971 | if (!nv_crtc) |
| 972 | return -ENOMEM; |
| 973 | |
| 974 | for (i = 0; i < 256; i++) { |
| 975 | nv_crtc->lut.r[i] = i << 8; |
| 976 | nv_crtc->lut.g[i] = i << 8; |
| 977 | nv_crtc->lut.b[i] = i << 8; |
| 978 | } |
| 979 | nv_crtc->lut.depth = 0; |
| 980 | |
| 981 | nv_crtc->index = crtc_num; |
| 982 | nv_crtc->last_dpms = NV_DPMS_CLEARED; |
| 983 | |
| 984 | drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); |
| 985 | drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); |
| 986 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); |
| 987 | |
| 988 | ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
| 989 | 0, 0x0000, false, true, &nv_crtc->cursor.nvbo); |
| 990 | if (!ret) { |
| 991 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); |
| 992 | if (!ret) |
| 993 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); |
| 994 | if (ret) |
| 995 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
| 996 | } |
| 997 | |
| 998 | nv04_cursor_init(nv_crtc); |
| 999 | |
| 1000 | return 0; |
| 1001 | } |
| 1002 | |