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Jiri Pirkoc1a38312016-10-21 16:07:23 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/resources.h
Jiri Pirko8708ecf2017-02-03 10:29:04 +01003 * Copyright (c) 2016-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2016-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirkoc1a38312016-10-21 16:07:23 +02005 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _MLXSW_RESOURCES_H
36#define _MLXSW_RESOURCES_H
37
38#include <linux/kernel.h>
39#include <linux/types.h>
40
41enum mlxsw_res_id {
42 MLXSW_RES_ID_KVD_SIZE,
43 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
44 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
Nogah Frankel23432cb2016-11-25 10:33:41 +010045 MLXSW_RES_ID_MAX_TRAP_GROUPS,
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010046 MLXSW_RES_ID_COUNTER_POOL_SIZE,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020047 MLXSW_RES_ID_MAX_SPAN,
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +010048 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
Arkadi Sharshevskye0c0afd2017-03-28 17:24:15 +020049 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020050 MLXSW_RES_ID_MAX_SYSTEM_PORT,
51 MLXSW_RES_ID_MAX_LAG,
52 MLXSW_RES_ID_MAX_LAG_MEMBERS,
Ido Schimmelf414b482016-11-28 18:01:23 +010053 MLXSW_RES_ID_MAX_BUFFER_SIZE,
Ido Schimmel18281f22017-03-24 08:02:51 +010054 MLXSW_RES_ID_CELL_SIZE,
Jiri Pirko8708ecf2017-02-03 10:29:04 +010055 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
56 MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
57 MLXSW_RES_ID_ACL_MAX_REGIONS,
58 MLXSW_RES_ID_ACL_MAX_GROUPS,
59 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
60 MLXSW_RES_ID_ACL_FLEX_KEYS,
61 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
62 MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
Nogah Frankel2b779582016-11-25 10:33:45 +010063 MLXSW_RES_ID_MAX_CPU_POLICERS,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020064 MLXSW_RES_ID_MAX_VRS,
65 MLXSW_RES_ID_MAX_RIFS,
Ido Schimmel8494ab02017-03-24 08:02:47 +010066 MLXSW_RES_ID_MAX_LPM_TREES,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020067
68 /* Internal resources.
69 * Determined by the SW, not queried from the HW.
70 */
71 MLXSW_RES_ID_KVD_SINGLE_SIZE,
72 MLXSW_RES_ID_KVD_DOUBLE_SIZE,
73 MLXSW_RES_ID_KVD_LINEAR_SIZE,
74
75 __MLXSW_RES_ID_MAX,
76};
77
78static u16 mlxsw_res_ids[] = {
79 [MLXSW_RES_ID_KVD_SIZE] = 0x1001,
80 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
81 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
Nogah Frankel23432cb2016-11-25 10:33:41 +010082 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010083 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020084 [MLXSW_RES_ID_MAX_SPAN] = 0x2420,
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +010085 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
Arkadi Sharshevskye0c0afd2017-03-28 17:24:15 +020086 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
Jiri Pirkoc1a38312016-10-21 16:07:23 +020087 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
88 [MLXSW_RES_ID_MAX_LAG] = 0x2520,
89 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
Ido Schimmelf414b482016-11-28 18:01:23 +010090 [MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802, /* Bytes */
Ido Schimmel18281f22017-03-24 08:02:51 +010091 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */
Jiri Pirko8708ecf2017-02-03 10:29:04 +010092 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
93 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
94 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
95 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
96 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
97 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
98 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
99 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
Nogah Frankel2b779582016-11-25 10:33:45 +0100100 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200101 [MLXSW_RES_ID_MAX_VRS] = 0x2C01,
102 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
Ido Schimmel8494ab02017-03-24 08:02:47 +0100103 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200104};
105
106struct mlxsw_res {
107 bool valid[__MLXSW_RES_ID_MAX];
108 u64 values[__MLXSW_RES_ID_MAX];
109};
110
111static inline bool mlxsw_res_valid(struct mlxsw_res *res,
112 enum mlxsw_res_id res_id)
113{
114 return res->valid[res_id];
115}
116
117#define MLXSW_RES_VALID(res, short_res_id) \
118 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
119
120static inline u64 mlxsw_res_get(struct mlxsw_res *res,
121 enum mlxsw_res_id res_id)
122{
123 if (WARN_ON(!res->valid[res_id]))
124 return 0;
125 return res->values[res_id];
126}
127
128#define MLXSW_RES_GET(res, short_res_id) \
129 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
130
131static inline void mlxsw_res_set(struct mlxsw_res *res,
132 enum mlxsw_res_id res_id, u64 value)
133{
134 res->valid[res_id] = true;
135 res->values[res_id] = value;
136}
137
138#define MLXSW_RES_SET(res, short_res_id, value) \
139 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
140
141static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
142{
143 int i;
144
145 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
146 if (mlxsw_res_ids[i] == id) {
147 mlxsw_res_set(res, i, value);
148 return;
149 }
150 }
151}
152
153#endif