| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-ep93xx/include/mach/hardware.h |
| 3 | */ |
| 4 | #ifndef __ASM_ARCH_HARDWARE_H |
| 5 | #define __ASM_ARCH_HARDWARE_H |
| 6 | |
| 7 | #include "ep93xx-regs.h" |
| 8 | |
| 9 | #define pcibios_assign_all_busses() 0 |
| 10 | |
| 11 | #include "platform.h" |
| 12 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 13 | #include "ts72xx.h" |
| 14 | |
| Hartley Sweeten | 701fac8 | 2009-06-30 23:06:43 +0100 | [diff] [blame^] | 15 | /* |
| 16 | * The EP93xx has two external crystal oscillators. To generate the |
| 17 | * required high-frequency clocks, the processor uses two phase-locked- |
| 18 | * loops (PLLs) to multiply the incoming external clock signal to much |
| 19 | * higher frequencies that are then divided down by programmable dividers |
| 20 | * to produce the needed clocks. The PLLs operate independently of one |
| 21 | * another. |
| 22 | */ |
| 23 | #define EP93XX_EXT_CLK_RATE 14745600 |
| 24 | #define EP93XX_EXT_RTC_RATE 32768 |
| 25 | |
| 26 | #define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) |
| 27 | #define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) |
| 28 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 29 | #endif |