blob: ba45739bdfe8ad508f7ed0a4be7f4845c64dc6a3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#undef DEBUG
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110022#undef DEBUG_LOW
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/sched.h>
27#include <linux/proc_fs.h>
28#include <linux/stat.h>
29#include <linux/sysctl.h>
Paul Gortmaker66b15db2011-05-27 10:46:24 -040030#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <linux/ctype.h>
32#include <linux/cache.h>
33#include <linux/init.h>
34#include <linux/signal.h>
Yinghai Lu95f72d12010-07-12 14:36:09 +100035#include <linux/memblock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/processor.h>
38#include <asm/pgtable.h>
39#include <asm/mmu.h>
40#include <asm/mmu_context.h>
41#include <asm/page.h>
42#include <asm/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <asm/uaccess.h>
44#include <asm/machdep.h>
David S. Millerd9b2b2a2008-02-13 16:56:49 -080045#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/tlbflush.h>
47#include <asm/io.h>
48#include <asm/eeh.h>
49#include <asm/tlb.h>
50#include <asm/cacheflush.h>
51#include <asm/cputable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052#include <asm/sections.h>
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +100053#include <asm/spu.h>
will schmidtaa39be02007-10-30 06:24:19 +110054#include <asm/udbg.h>
Anton Blanchardb68a70c2011-04-04 23:56:18 +000055#include <asm/code-patching.h>
Mahesh Salgaonkar3ccc00a2012-02-20 02:15:03 +000056#include <asm/fadump.h>
Stephen Rothwellf5339272012-03-15 18:18:00 +000057#include <asm/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
59#ifdef DEBUG
60#define DBG(fmt...) udbg_printf(fmt)
61#else
62#define DBG(fmt...)
63#endif
64
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110065#ifdef DEBUG_LOW
66#define DBG_LOW(fmt...) udbg_printf(fmt)
67#else
68#define DBG_LOW(fmt...)
69#endif
70
71#define KB (1024)
72#define MB (1024*KB)
Jon Tollefson658013e2008-07-23 21:27:54 -070073#define GB (1024L*MB)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110074
Linus Torvalds1da177e2005-04-16 15:20:36 -070075/*
76 * Note: pte --> Linux PTE
77 * HPTE --> PowerPC Hashed Page Table Entry
78 *
79 * Execution context:
80 * htab_initialize is called with the MMU off (of course), but
81 * the kernel has been copied down to zero so it can directly
82 * reference global data. At this point it is very difficult
83 * to print debug info.
84 *
85 */
86
87#ifdef CONFIG_U3_DART
88extern unsigned long dart_tablebase;
89#endif /* CONFIG_U3_DART */
90
Paul Mackerras799d6042005-11-10 13:37:51 +110091static unsigned long _SDR1;
92struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
93
David Gibson8e561e72007-06-13 14:52:56 +100094struct hash_pte *htab_address;
Michael Ellerman337a7122006-02-21 17:22:55 +110095unsigned long htab_size_bytes;
David Gibson96e28442005-07-13 01:11:42 -070096unsigned long htab_hash_mask;
Alexander Graf4ab79aa2009-10-30 05:47:19 +000097EXPORT_SYMBOL_GPL(htab_hash_mask);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110098int mmu_linear_psize = MMU_PAGE_4K;
99int mmu_virtual_psize = MMU_PAGE_4K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000100int mmu_vmalloc_psize = MMU_PAGE_4K;
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000101#ifdef CONFIG_SPARSEMEM_VMEMMAP
102int mmu_vmemmap_psize = MMU_PAGE_4K;
103#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000104int mmu_io_psize = MMU_PAGE_4K;
Paul Mackerras1189be62007-10-11 20:37:10 +1000105int mmu_kernel_ssize = MMU_SEGSIZE_256M;
106int mmu_highuser_ssize = MMU_SEGSIZE_256M;
Michael Neuling584f8b72007-12-06 17:24:48 +1100107u16 mmu_slb_size = 64;
Alexander Graf4ab79aa2009-10-30 05:47:19 +0000108EXPORT_SYMBOL_GPL(mmu_slb_size);
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000109#ifdef CONFIG_PPC_64K_PAGES
110int mmu_ci_restrictions;
111#endif
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000112#ifdef CONFIG_DEBUG_PAGEALLOC
113static u8 *linear_map_hash_slots;
114static unsigned long linear_map_hash_count;
Michael Ellermaned166692007-04-18 11:50:09 +1000115static DEFINE_SPINLOCK(linear_map_hash_lock);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000116#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100118/* There are definitions of page sizes arrays to be used when none
119 * is provided by the firmware.
120 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100122/* Pre-POWER4 CPUs (4k pages only)
123 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000124static struct mmu_psize_def mmu_psize_defaults_old[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100125 [MMU_PAGE_4K] = {
126 .shift = 12,
127 .sllp = 0,
128 .penc = 0,
129 .avpnm = 0,
130 .tlbiel = 0,
131 },
132};
133
134/* POWER4, GPUL, POWER5
135 *
136 * Support for 16Mb large pages
137 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000138static struct mmu_psize_def mmu_psize_defaults_gp[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100139 [MMU_PAGE_4K] = {
140 .shift = 12,
141 .sllp = 0,
142 .penc = 0,
143 .avpnm = 0,
144 .tlbiel = 1,
145 },
146 [MMU_PAGE_16M] = {
147 .shift = 24,
148 .sllp = SLB_VSID_L,
149 .penc = 0,
150 .avpnm = 0x1UL,
151 .tlbiel = 0,
152 },
153};
154
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000155static unsigned long htab_convert_pte_flags(unsigned long pteflags)
156{
157 unsigned long rflags = pteflags & 0x1fa;
158
159 /* _PAGE_EXEC -> NOEXEC */
160 if ((pteflags & _PAGE_EXEC) == 0)
161 rflags |= HPTE_R_N;
162
163 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
164 * need to add in 0x1 if it's a read-only user page
165 */
166 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
167 (pteflags & _PAGE_DIRTY)))
168 rflags |= 1;
169
170 /* Always add C */
171 return rflags | HPTE_R_C;
172}
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100173
174int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000175 unsigned long pstart, unsigned long prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000176 int psize, int ssize)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100178 unsigned long vaddr, paddr;
179 unsigned int step, shift;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100180 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100182 shift = mmu_psize_defs[psize].shift;
183 step = 1 << shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000185 prot = htab_convert_pte_flags(prot);
186
187 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
188 vstart, vend, pstart, prot, psize, ssize);
189
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100190 for (vaddr = vstart, paddr = pstart; vaddr < vend;
191 vaddr += step, paddr += step) {
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000192 unsigned long hash, hpteg;
Paul Mackerras1189be62007-10-11 20:37:10 +1000193 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
194 unsigned long va = hpt_va(vaddr, vsid, ssize);
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000195 unsigned long tprot = prot;
196
197 /* Make kernel text executable */
Paul Mackerras549e8152008-08-30 11:43:47 +1000198 if (overlaps_kernel_text(vaddr, vaddr + step))
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000199 tprot &= ~HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200
Paul Mackerras1189be62007-10-11 20:37:10 +1000201 hash = hpt_hash(va, shift, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
203
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000204 BUG_ON(!ppc_md.hpte_insert);
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000205 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000206 HPTE_V_BOLTED, psize, ssize);
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000207
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100208 if (ret < 0)
209 break;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000210#ifdef CONFIG_DEBUG_PAGEALLOC
211 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
212 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
213#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100215 return ret < 0 ? ret : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216}
217
Stephen Rothwellae86f002008-03-27 16:08:57 +1100218#ifdef CONFIG_MEMORY_HOTPLUG
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100219static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100220 int psize, int ssize)
221{
222 unsigned long vaddr;
223 unsigned int step, shift;
224
225 shift = mmu_psize_defs[psize].shift;
226 step = 1 << shift;
227
228 if (!ppc_md.hpte_removebolted) {
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100229 printk(KERN_WARNING "Platform doesn't implement "
230 "hpte_removebolted\n");
231 return -EINVAL;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100232 }
233
234 for (vaddr = vstart; vaddr < vend; vaddr += step)
235 ppc_md.hpte_removebolted(vaddr, psize, ssize);
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100236
237 return 0;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100238}
Stephen Rothwellae86f002008-03-27 16:08:57 +1100239#endif /* CONFIG_MEMORY_HOTPLUG */
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100240
Paul Mackerras1189be62007-10-11 20:37:10 +1000241static int __init htab_dt_scan_seg_sizes(unsigned long node,
242 const char *uname, int depth,
243 void *data)
244{
245 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
246 u32 *prop;
247 unsigned long size = 0;
248
249 /* We are scanning "cpu" nodes only */
250 if (type == NULL || strcmp(type, "cpu") != 0)
251 return 0;
252
253 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
254 &size);
255 if (prop == NULL)
256 return 0;
257 for (; size >= 4; size -= 4, ++prop) {
258 if (prop[0] == 40) {
259 DBG("1T segment support detected\n");
Matt Evans44ae3ab2011-04-06 19:48:50 +0000260 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
Olof Johanssonf5534002007-10-12 16:44:55 +1000261 return 1;
Paul Mackerras1189be62007-10-11 20:37:10 +1000262 }
Paul Mackerras1189be62007-10-11 20:37:10 +1000263 }
Matt Evans44ae3ab2011-04-06 19:48:50 +0000264 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
Paul Mackerras1189be62007-10-11 20:37:10 +1000265 return 0;
266}
267
268static void __init htab_init_seg_sizes(void)
269{
270 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
271}
272
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100273static int __init htab_dt_scan_page_sizes(unsigned long node,
274 const char *uname, int depth,
275 void *data)
276{
277 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
278 u32 *prop;
279 unsigned long size = 0;
280
281 /* We are scanning "cpu" nodes only */
282 if (type == NULL || strcmp(type, "cpu") != 0)
283 return 0;
284
285 prop = (u32 *)of_get_flat_dt_prop(node,
286 "ibm,segment-page-sizes", &size);
287 if (prop != NULL) {
288 DBG("Page sizes from device-tree:\n");
289 size /= 4;
Matt Evans44ae3ab2011-04-06 19:48:50 +0000290 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100291 while(size > 0) {
292 unsigned int shift = prop[0];
293 unsigned int slbenc = prop[1];
294 unsigned int lpnum = prop[2];
295 unsigned int lpenc = 0;
296 struct mmu_psize_def *def;
297 int idx = -1;
298
299 size -= 3; prop += 3;
300 while(size > 0 && lpnum) {
301 if (prop[0] == shift)
302 lpenc = prop[1];
303 prop += 2; size -= 2;
304 lpnum--;
305 }
306 switch(shift) {
307 case 0xc:
308 idx = MMU_PAGE_4K;
309 break;
310 case 0x10:
311 idx = MMU_PAGE_64K;
312 break;
313 case 0x14:
314 idx = MMU_PAGE_1M;
315 break;
316 case 0x18:
317 idx = MMU_PAGE_16M;
Matt Evans44ae3ab2011-04-06 19:48:50 +0000318 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100319 break;
320 case 0x22:
321 idx = MMU_PAGE_16G;
322 break;
323 }
324 if (idx < 0)
325 continue;
326 def = &mmu_psize_defs[idx];
327 def->shift = shift;
328 if (shift <= 23)
329 def->avpnm = 0;
330 else
331 def->avpnm = (1 << (shift - 23)) - 1;
332 def->sllp = slbenc;
333 def->penc = lpenc;
334 /* We don't know for sure what's up with tlbiel, so
335 * for now we only set it for 4K and 64K pages
336 */
337 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
338 def->tlbiel = 1;
339 else
340 def->tlbiel = 0;
341
Sachin P. Sant5c339912009-12-13 21:15:12 +0000342 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100343 "tlbiel=%d, penc=%d\n",
344 idx, shift, def->sllp, def->avpnm, def->tlbiel,
345 def->penc);
346 }
347 return 1;
348 }
349 return 0;
350}
351
Tony Breedse16a9c02008-07-31 13:51:42 +1000352#ifdef CONFIG_HUGETLB_PAGE
Jon Tollefson658013e2008-07-23 21:27:54 -0700353/* Scan for 16G memory blocks that have been set aside for huge pages
354 * and reserve those blocks for 16G huge pages.
355 */
356static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
357 const char *uname, int depth,
358 void *data) {
359 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
360 unsigned long *addr_prop;
361 u32 *page_count_prop;
362 unsigned int expected_pages;
363 long unsigned int phys_addr;
364 long unsigned int block_size;
365
366 /* We are scanning "memory" nodes only */
367 if (type == NULL || strcmp(type, "memory") != 0)
368 return 0;
369
370 /* This property is the log base 2 of the number of virtual pages that
371 * will represent this memory block. */
372 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
373 if (page_count_prop == NULL)
374 return 0;
375 expected_pages = (1 << page_count_prop[0]);
376 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
377 if (addr_prop == NULL)
378 return 0;
379 phys_addr = addr_prop[0];
380 block_size = addr_prop[1];
381 if (block_size != (16 * GB))
382 return 0;
383 printk(KERN_INFO "Huge page(16GB) memory: "
384 "addr = 0x%lX size = 0x%lX pages = %d\n",
385 phys_addr, block_size, expected_pages);
Yinghai Lu95f72d12010-07-12 14:36:09 +1000386 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
387 memblock_reserve(phys_addr, block_size * expected_pages);
Jon Tollefson4792adb2008-10-21 15:27:36 +0000388 add_gpage(phys_addr, block_size, expected_pages);
389 }
Jon Tollefson658013e2008-07-23 21:27:54 -0700390 return 0;
391}
Tony Breedse16a9c02008-07-31 13:51:42 +1000392#endif /* CONFIG_HUGETLB_PAGE */
Jon Tollefson658013e2008-07-23 21:27:54 -0700393
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100394static void __init htab_init_page_sizes(void)
395{
396 int rc;
397
398 /* Default to 4K pages only */
399 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
400 sizeof(mmu_psize_defaults_old));
401
402 /*
403 * Try to find the available page sizes in the device-tree
404 */
405 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
406 if (rc != 0) /* Found */
407 goto found;
408
409 /*
410 * Not in the device-tree, let's fallback on known size
411 * list for 16M capable GP & GR
412 */
Matt Evans44ae3ab2011-04-06 19:48:50 +0000413 if (mmu_has_feature(MMU_FTR_16M_PAGE))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100414 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
415 sizeof(mmu_psize_defaults_gp));
416 found:
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000417#ifndef CONFIG_DEBUG_PAGEALLOC
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100418 /*
419 * Pick a size for the linear mapping. Currently, we only support
420 * 16M, 1M and 4K which is the default
421 */
422 if (mmu_psize_defs[MMU_PAGE_16M].shift)
423 mmu_linear_psize = MMU_PAGE_16M;
424 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
425 mmu_linear_psize = MMU_PAGE_1M;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000426#endif /* CONFIG_DEBUG_PAGEALLOC */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100427
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000428#ifdef CONFIG_PPC_64K_PAGES
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100429 /*
430 * Pick a size for the ordinary pages. Default is 4K, we support
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000431 * 64K for user mappings and vmalloc if supported by the processor.
432 * We only use 64k for ioremap if the processor
433 * (and firmware) support cache-inhibited large pages.
434 * If not, we use 4k and set mmu_ci_restrictions so that
435 * hash_page knows to switch processes that use cache-inhibited
436 * mappings to 4k pages.
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100437 */
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000438 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100439 mmu_virtual_psize = MMU_PAGE_64K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000440 mmu_vmalloc_psize = MMU_PAGE_64K;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000441 if (mmu_linear_psize == MMU_PAGE_4K)
442 mmu_linear_psize = MMU_PAGE_64K;
Matt Evans44ae3ab2011-04-06 19:48:50 +0000443 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
Paul Mackerrascfe666b2008-03-24 17:41:22 +1100444 /*
445 * Don't use 64k pages for ioremap on pSeries, since
446 * that would stop us accessing the HEA ethernet.
447 */
448 if (!machine_is(pseries))
449 mmu_io_psize = MMU_PAGE_64K;
450 } else
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000451 mmu_ci_restrictions = 1;
452 }
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000453#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100454
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000455#ifdef CONFIG_SPARSEMEM_VMEMMAP
456 /* We try to use 16M pages for vmemmap if that is supported
457 * and we have at least 1G of RAM at boot
458 */
459 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
Yinghai Lu95f72d12010-07-12 14:36:09 +1000460 memblock_phys_mem_size() >= 0x40000000)
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000461 mmu_vmemmap_psize = MMU_PAGE_16M;
462 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
463 mmu_vmemmap_psize = MMU_PAGE_64K;
464 else
465 mmu_vmemmap_psize = MMU_PAGE_4K;
466#endif /* CONFIG_SPARSEMEM_VMEMMAP */
467
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000468 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000469 "virtual = %d, io = %d"
470#ifdef CONFIG_SPARSEMEM_VMEMMAP
471 ", vmemmap = %d"
472#endif
473 "\n",
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100474 mmu_psize_defs[mmu_linear_psize].shift,
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000475 mmu_psize_defs[mmu_virtual_psize].shift,
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000476 mmu_psize_defs[mmu_io_psize].shift
477#ifdef CONFIG_SPARSEMEM_VMEMMAP
478 ,mmu_psize_defs[mmu_vmemmap_psize].shift
479#endif
480 );
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100481
482#ifdef CONFIG_HUGETLB_PAGE
Jon Tollefson658013e2008-07-23 21:27:54 -0700483 /* Reserve 16G huge page memory sections for huge pages */
484 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100485#endif /* CONFIG_HUGETLB_PAGE */
486}
487
488static int __init htab_dt_scan_pftsize(unsigned long node,
489 const char *uname, int depth,
490 void *data)
491{
492 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
493 u32 *prop;
494
495 /* We are scanning "cpu" nodes only */
496 if (type == NULL || strcmp(type, "cpu") != 0)
497 return 0;
498
499 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
500 if (prop != NULL) {
501 /* pft_size[0] is the NUMA CEC cookie */
502 ppc64_pft_size = prop[1];
503 return 1;
504 }
505 return 0;
506}
507
508static unsigned long __init htab_get_table_size(void)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000509{
Anton Blanchard13870b62009-02-13 11:57:30 +0000510 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000511
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100512 /* If hash size isn't already provided by the platform, we try to
Adrian Bunk943ffb52006-01-10 00:10:13 +0100513 * retrieve it from the device-tree. If it's not there neither, we
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100514 * calculate it now based on the total RAM size
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000515 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100516 if (ppc64_pft_size == 0)
517 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000518 if (ppc64_pft_size)
519 return 1UL << ppc64_pft_size;
520
521 /* round mem_size up to next power of 2 */
Yinghai Lu95f72d12010-07-12 14:36:09 +1000522 mem_size = memblock_phys_mem_size();
Paul Mackerras799d6042005-11-10 13:37:51 +1100523 rnd_mem_size = 1UL << __ilog2(mem_size);
524 if (rnd_mem_size < mem_size)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000525 rnd_mem_size <<= 1;
526
527 /* # pages / 2 */
Anton Blanchard13870b62009-02-13 11:57:30 +0000528 psize = mmu_psize_defs[mmu_virtual_psize].shift;
529 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000530
531 return pteg_count << 7;
532}
533
Mike Kravetz54b79242005-11-07 16:25:48 -0800534#ifdef CONFIG_MEMORY_HOTPLUG
Anton Blancharda1194092011-08-10 20:44:24 +0000535int create_section_mapping(unsigned long start, unsigned long end)
Mike Kravetz54b79242005-11-07 16:25:48 -0800536{
Anton Blancharda1194092011-08-10 20:44:24 +0000537 return htab_bolt_mapping(start, end, __pa(start),
David Gibsonf5ea64d2008-10-12 17:54:24 +0000538 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
Anton Blancharda1194092011-08-10 20:44:24 +0000539 mmu_kernel_ssize);
Mike Kravetz54b79242005-11-07 16:25:48 -0800540}
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100541
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100542int remove_section_mapping(unsigned long start, unsigned long end)
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100543{
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100544 return htab_remove_mapping(start, end, mmu_linear_psize,
545 mmu_kernel_ssize);
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100546}
Mike Kravetz54b79242005-11-07 16:25:48 -0800547#endif /* CONFIG_MEMORY_HOTPLUG */
548
Anton Blanchardb68a70c2011-04-04 23:56:18 +0000549#define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000550
551static void __init htab_finish_init(void)
552{
553 extern unsigned int *htab_call_hpte_insert1;
554 extern unsigned int *htab_call_hpte_insert2;
555 extern unsigned int *htab_call_hpte_remove;
556 extern unsigned int *htab_call_hpte_updatepp;
557
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000558#ifdef CONFIG_PPC_HAS_HASH_64K
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000559 extern unsigned int *ht64_call_hpte_insert1;
560 extern unsigned int *ht64_call_hpte_insert2;
561 extern unsigned int *ht64_call_hpte_remove;
562 extern unsigned int *ht64_call_hpte_updatepp;
563
Anton Blanchardb68a70c2011-04-04 23:56:18 +0000564 patch_branch(ht64_call_hpte_insert1,
565 FUNCTION_TEXT(ppc_md.hpte_insert),
566 BRANCH_SET_LINK);
567 patch_branch(ht64_call_hpte_insert2,
568 FUNCTION_TEXT(ppc_md.hpte_insert),
569 BRANCH_SET_LINK);
570 patch_branch(ht64_call_hpte_remove,
571 FUNCTION_TEXT(ppc_md.hpte_remove),
572 BRANCH_SET_LINK);
573 patch_branch(ht64_call_hpte_updatepp,
574 FUNCTION_TEXT(ppc_md.hpte_updatepp),
575 BRANCH_SET_LINK);
576
Jon Tollefson5b825832007-05-17 04:43:02 +1000577#endif /* CONFIG_PPC_HAS_HASH_64K */
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000578
Anton Blanchardb68a70c2011-04-04 23:56:18 +0000579 patch_branch(htab_call_hpte_insert1,
580 FUNCTION_TEXT(ppc_md.hpte_insert),
581 BRANCH_SET_LINK);
582 patch_branch(htab_call_hpte_insert2,
583 FUNCTION_TEXT(ppc_md.hpte_insert),
584 BRANCH_SET_LINK);
585 patch_branch(htab_call_hpte_remove,
586 FUNCTION_TEXT(ppc_md.hpte_remove),
587 BRANCH_SET_LINK);
588 patch_branch(htab_call_hpte_updatepp,
589 FUNCTION_TEXT(ppc_md.hpte_updatepp),
590 BRANCH_SET_LINK);
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000591}
592
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000593static void __init htab_initialize(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594{
Michael Ellerman337a7122006-02-21 17:22:55 +1100595 unsigned long table;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 unsigned long pteg_count;
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000597 unsigned long prot;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100598 unsigned long base = 0, size = 0, limit;
Benjamin Herrenschmidt28be7072010-08-04 13:43:53 +1000599 struct memblock_region *reg;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100600
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 DBG(" -> htab_initialize()\n");
602
Paul Mackerras1189be62007-10-11 20:37:10 +1000603 /* Initialize segment sizes */
604 htab_init_seg_sizes();
605
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100606 /* Initialize page sizes */
607 htab_init_page_sizes();
608
Matt Evans44ae3ab2011-04-06 19:48:50 +0000609 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
Paul Mackerras1189be62007-10-11 20:37:10 +1000610 mmu_kernel_ssize = MMU_SEGSIZE_1T;
611 mmu_highuser_ssize = MMU_SEGSIZE_1T;
612 printk(KERN_INFO "Using 1TB segments\n");
613 }
614
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 /*
616 * Calculate the required size of the htab. We want the number of
617 * PTEGs to equal one half the number of real pages.
618 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100619 htab_size_bytes = htab_get_table_size();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 pteg_count = htab_size_bytes >> 7;
621
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622 htab_hash_mask = pteg_count - 1;
623
Michael Ellerman57cfb812006-03-21 20:45:59 +1100624 if (firmware_has_feature(FW_FEATURE_LPAR)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 /* Using a hypervisor which owns the htab */
626 htab_address = NULL;
627 _SDR1 = 0;
Mahesh Salgaonkar3ccc00a2012-02-20 02:15:03 +0000628#ifdef CONFIG_FA_DUMP
629 /*
630 * If firmware assisted dump is active firmware preserves
631 * the contents of htab along with entire partition memory.
632 * Clear the htab if firmware assisted dump is active so
633 * that we dont end up using old mappings.
634 */
635 if (is_fadump_active() && ppc_md.hpte_clear_all)
636 ppc_md.hpte_clear_all();
637#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 } else {
639 /* Find storage for the HPT. Must be contiguous in
Michael Ellerman41d824b2008-01-30 01:13:59 +1100640 * the absolute address space. On cell we want it to be
Michael Ellerman31bf1112008-03-12 18:03:24 +1100641 * in the first 2 Gig so we can use it for IOMMU hacks.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 */
Michael Ellerman41d824b2008-01-30 01:13:59 +1100643 if (machine_is(cell))
Michael Ellerman31bf1112008-03-12 18:03:24 +1100644 limit = 0x80000000;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100645 else
Benjamin Herrenschmidt27f574c2010-07-06 15:39:00 -0700646 limit = MEMBLOCK_ALLOC_ANYWHERE;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100647
Yinghai Lu95f72d12010-07-12 14:36:09 +1000648 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649
650 DBG("Hash table allocated at %lx, size: %lx\n", table,
651 htab_size_bytes);
652
Michael Ellerman70267a72012-07-25 21:19:50 +0000653 htab_address = __va(table);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
655 /* htab absolute addr + encoded htabsize */
656 _SDR1 = table + __ilog2(pteg_count) - 11;
657
658 /* Initialize the HPT with no entries */
659 memset((void *)table, 0, htab_size_bytes);
Paul Mackerras799d6042005-11-10 13:37:51 +1100660
661 /* Set SDR1 */
662 mtspr(SPRN_SDR1, _SDR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 }
664
David Gibsonf5ea64d2008-10-12 17:54:24 +0000665 prot = pgprot_val(PAGE_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000667#ifdef CONFIG_DEBUG_PAGEALLOC
Yinghai Lu95f72d12010-07-12 14:36:09 +1000668 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
669 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -0700670 1, ppc64_rma_size));
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000671 memset(linear_map_hash_slots, 0, linear_map_hash_count);
672#endif /* CONFIG_DEBUG_PAGEALLOC */
673
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 /* On U3 based machines, we need to reserve the DART area and
675 * _NOT_ map it to avoid cache paradoxes as it's remapped non
676 * cacheable later on
677 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
679 /* create bolted the linear mapping in the hash table */
Benjamin Herrenschmidt28be7072010-08-04 13:43:53 +1000680 for_each_memblock(memory, reg) {
681 base = (unsigned long)__va(reg->base);
682 size = reg->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683
Sachin P. Sant5c339912009-12-13 21:15:12 +0000684 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000685 base, size, prot);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686
687#ifdef CONFIG_U3_DART
688 /* Do not map the DART space. Fortunately, it will be aligned
Yinghai Lu95f72d12010-07-12 14:36:09 +1000689 * in such a way that it will not cross two memblock regions and
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100690 * will fit within a single 16Mb page.
691 * The DART space is assumed to be a full 16Mb region even if
692 * we only use 2Mb of that space. We will use more of it later
693 * for AGP GART. We have to use a full 16Mb large page.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 */
695 DBG("DART base: %lx\n", dart_tablebase);
696
697 if (dart_tablebase != 0 && dart_tablebase >= base
698 && dart_tablebase < (base + size)) {
Michael Ellermancaf80e52006-03-21 20:45:51 +1100699 unsigned long dart_table_end = dart_tablebase + 16 * MB;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 if (base != dart_tablebase)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100701 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000702 __pa(base), prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000703 mmu_linear_psize,
704 mmu_kernel_ssize));
Michael Ellermancaf80e52006-03-21 20:45:51 +1100705 if ((base + size) > dart_table_end)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100706 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
Michael Ellermancaf80e52006-03-21 20:45:51 +1100707 base + size,
708 __pa(dart_table_end),
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000709 prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000710 mmu_linear_psize,
711 mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 continue;
713 }
714#endif /* CONFIG_U3_DART */
Michael Ellermancaf80e52006-03-21 20:45:51 +1100715 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000716 prot, mmu_linear_psize, mmu_kernel_ssize));
Benjamin Herrenschmidte63075a2010-07-06 15:39:01 -0700717 }
718 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
720 /*
721 * If we have a memory_limit and we've allocated TCEs then we need to
722 * explicitly map the TCE area at the top of RAM. We also cope with the
723 * case that the TCEs start below memory_limit.
724 * tce_alloc_start/end are 16MB aligned so the mapping should work
725 * for either 4K or 16MB pages.
726 */
727 if (tce_alloc_start) {
Michael Ellermanb5666f72005-12-05 10:24:33 -0600728 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
729 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730
731 if (base + size >= tce_alloc_start)
732 tce_alloc_start = base + size + 1;
733
Michael Ellermancaf80e52006-03-21 20:45:51 +1100734 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000735 __pa(tce_alloc_start), prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000736 mmu_linear_psize, mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737 }
738
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000739 htab_finish_init();
740
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 DBG(" <- htab_initialize()\n");
742}
743#undef KB
744#undef MB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000746void __init early_init_mmu(void)
Paul Mackerras799d6042005-11-10 13:37:51 +1100747{
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000748 /* Setup initial STAB address in the PACA */
749 get_paca()->stab_real = __pa((u64)&initial_stab);
750 get_paca()->stab_addr = (u64)&initial_stab;
751
752 /* Initialize the MMU Hash table and create the linear mapping
753 * of memory. Has to be done before stab/slb initialization as
754 * this is currently where the page size encoding is obtained
755 */
756 htab_initialize();
757
Stephen Rothwellf5339272012-03-15 18:18:00 +0000758 /* Initialize stab / SLB management */
Matt Evans44ae3ab2011-04-06 19:48:50 +0000759 if (mmu_has_feature(MMU_FTR_SLB))
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000760 slb_initialize();
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000761}
762
763#ifdef CONFIG_SMP
Michael Ellerman24f1ce82009-04-16 04:47:32 +0000764void __cpuinit early_init_mmu_secondary(void)
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000765{
766 /* Initialize hash table for that CPU */
Michael Ellerman57cfb812006-03-21 20:45:59 +1100767 if (!firmware_has_feature(FW_FEATURE_LPAR))
Paul Mackerras799d6042005-11-10 13:37:51 +1100768 mtspr(SPRN_SDR1, _SDR1);
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000769
770 /* Initialize STAB/SLB. We use a virtual address as it works
Stephen Rothwellf5339272012-03-15 18:18:00 +0000771 * in real mode on pSeries.
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000772 */
Matt Evans44ae3ab2011-04-06 19:48:50 +0000773 if (mmu_has_feature(MMU_FTR_SLB))
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000774 slb_initialize();
775 else
776 stab_initialize(get_paca()->stab_addr);
Paul Mackerras799d6042005-11-10 13:37:51 +1100777}
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000778#endif /* CONFIG_SMP */
Paul Mackerras799d6042005-11-10 13:37:51 +1100779
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780/*
781 * Called by asm hashtable.S for doing lazy icache flush
782 */
783unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
784{
785 struct page *page;
786
Benjamin Herrenschmidt76c8e252005-11-08 11:21:05 +1100787 if (!pfn_valid(pte_pfn(pte)))
788 return pp;
789
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 page = pte_page(pte);
791
792 /* page is dirty */
793 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
794 if (trap == 0x400) {
David Gibson0895ecd2009-10-26 19:24:31 +0000795 flush_dcache_icache_page(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 set_bit(PG_arch_1, &page->flags);
797 } else
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100798 pp |= HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 }
800 return pp;
801}
802
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000803#ifdef CONFIG_PPC_MM_SLICES
804unsigned int get_paca_psize(unsigned long addr)
805{
806 unsigned long index, slices;
807
808 if (addr < SLICE_LOW_TOP) {
809 slices = get_paca()->context.low_slices_psize;
810 index = GET_LOW_SLICE_INDEX(addr);
811 } else {
812 slices = get_paca()->context.high_slices_psize;
813 index = GET_HIGH_SLICE_INDEX(addr);
814 }
815 return (slices >> (index * 4)) & 0xF;
816}
817
818#else
819unsigned int get_paca_psize(unsigned long addr)
820{
821 return get_paca()->context.user_psize;
822}
823#endif
824
Paul Mackerras721151d2007-04-03 21:24:02 +1000825/*
826 * Demote a segment to using 4k pages.
827 * For now this makes the whole process use 4k pages.
828 */
Paul Mackerras721151d2007-04-03 21:24:02 +1000829#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerrasfa282372008-01-24 08:35:13 +1100830void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000831{
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000832 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
Paul Mackerras721151d2007-04-03 21:24:02 +1000833 return;
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000834 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +1000835#ifdef CONFIG_SPU_BASE
Paul Mackerras721151d2007-04-03 21:24:02 +1000836 spu_flush_all_slbs(mm);
837#endif
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000838 if (get_paca_psize(addr) != MMU_PAGE_4K) {
Paul Mackerrasfa282372008-01-24 08:35:13 +1100839 get_paca()->context = mm->context;
840 slb_flush_and_rebolt();
841 }
Paul Mackerras721151d2007-04-03 21:24:02 +1000842}
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000843#endif /* CONFIG_PPC_64K_PAGES */
Paul Mackerras721151d2007-04-03 21:24:02 +1000844
Paul Mackerrasfa282372008-01-24 08:35:13 +1100845#ifdef CONFIG_PPC_SUBPAGE_PROT
846/*
847 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
848 * Userspace sets the subpage permissions using the subpage_prot system call.
849 *
850 * Result is 0: full permissions, _PAGE_RW: read-only,
851 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
852 */
David Gibsond28513b2009-11-26 18:56:04 +0000853static int subpage_protection(struct mm_struct *mm, unsigned long ea)
Paul Mackerrasfa282372008-01-24 08:35:13 +1100854{
David Gibsond28513b2009-11-26 18:56:04 +0000855 struct subpage_prot_table *spt = &mm->context.spt;
Paul Mackerrasfa282372008-01-24 08:35:13 +1100856 u32 spp = 0;
857 u32 **sbpm, *sbpp;
858
859 if (ea >= spt->maxaddr)
860 return 0;
861 if (ea < 0x100000000) {
862 /* addresses below 4GB use spt->low_prot */
863 sbpm = spt->low_prot;
864 } else {
865 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
866 if (!sbpm)
867 return 0;
868 }
869 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
870 if (!sbpp)
871 return 0;
872 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
873
874 /* extract 2-bit bitfield for this 4k subpage */
875 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
876
877 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
878 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
879 return spp;
880}
881
882#else /* CONFIG_PPC_SUBPAGE_PROT */
David Gibsond28513b2009-11-26 18:56:04 +0000883static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
Paul Mackerrasfa282372008-01-24 08:35:13 +1100884{
885 return 0;
886}
887#endif
888
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +1000889void hash_failure_debug(unsigned long ea, unsigned long access,
890 unsigned long vsid, unsigned long trap,
891 int ssize, int psize, unsigned long pte)
892{
893 if (!printk_ratelimit())
894 return;
895 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
896 ea, access, current->comm);
897 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
898 trap, vsid, ssize, psize, pte);
899}
900
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901/* Result code is:
902 * 0 - handled
903 * 1 - normal page fault
904 * -1 - critical hash insertion error
Paul Mackerrasfa282372008-01-24 08:35:13 +1100905 * -2 - access not permitted by subpage protection mechanism
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 */
907int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
908{
David Gibsona1128f82009-12-16 14:29:56 +0000909 pgd_t *pgdir;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 unsigned long vsid;
911 struct mm_struct *mm;
912 pte_t *ptep;
David Gibsona4fe3ce2009-10-26 19:24:31 +0000913 unsigned hugeshift;
Rusty Russell56aa4122009-03-15 18:16:43 +0000914 const struct cpumask *tmp;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100915 int rc, user_region = 0, local = 0;
Paul Mackerras1189be62007-10-11 20:37:10 +1000916 int psize, ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100918 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
919 ea, access, trap);
David Gibson1f8d4192005-05-05 16:15:13 -0700920
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100921 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
922 DBG_LOW(" out of pgtable range !\n");
923 return 1;
924 }
925
926 /* Get region & vsid */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 switch (REGION_ID(ea)) {
928 case USER_REGION_ID:
929 user_region = 1;
930 mm = current->mm;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100931 if (! mm) {
932 DBG_LOW(" user region with no mm !\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 return 1;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100934 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000935 psize = get_slice_psize(mm, ea);
Paul Mackerras1189be62007-10-11 20:37:10 +1000936 ssize = user_segment_size(ea);
937 vsid = get_vsid(mm->context.id, ea, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 case VMALLOC_REGION_ID:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 mm = &init_mm;
Paul Mackerras1189be62007-10-11 20:37:10 +1000941 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000942 if (ea < VMALLOC_END)
943 psize = mmu_vmalloc_psize;
944 else
945 psize = mmu_io_psize;
Paul Mackerras1189be62007-10-11 20:37:10 +1000946 ssize = mmu_kernel_ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 default:
949 /* Not a valid range
950 * Send the problem up to do_page_fault
951 */
952 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100954 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100956 /* Get pgdir */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957 pgdir = mm->pgd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 if (pgdir == NULL)
959 return 1;
960
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100961 /* Check CPU locality */
Rusty Russell56aa4122009-03-15 18:16:43 +0000962 tmp = cpumask_of(smp_processor_id());
963 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964 local = 1;
965
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000966#ifndef CONFIG_PPC_64K_PAGES
David Gibsona4fe3ce2009-10-26 19:24:31 +0000967 /* If we use 4K pages and our psize is not 4K, then we might
968 * be hitting a special driver mapping, and need to align the
969 * address before we fetch the PTE.
970 *
971 * It could also be a hugepage mapping, in which case this is
972 * not necessary, but it's not harmful, either.
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000973 */
974 if (psize != MMU_PAGE_4K)
975 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
976#endif /* CONFIG_PPC_64K_PAGES */
977
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100978 /* Get PTE and page size from page tables */
David Gibsona4fe3ce2009-10-26 19:24:31 +0000979 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100980 if (ptep == NULL || !pte_present(*ptep)) {
981 DBG_LOW(" no PTE !\n");
982 return 1;
983 }
984
Benjamin Herrenschmidtca91e6c2010-07-23 08:53:23 +1000985 /* Add _PAGE_PRESENT to the required access perm */
986 access |= _PAGE_PRESENT;
987
988 /* Pre-check access permissions (will be re-checked atomically
989 * in __hash_page_XX but this pre-check is a fast path
990 */
991 if (access & ~pte_val(*ptep)) {
992 DBG_LOW(" no access !\n");
993 return 1;
994 }
995
David Gibsona4fe3ce2009-10-26 19:24:31 +0000996#ifdef CONFIG_HUGETLB_PAGE
997 if (hugeshift)
998 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
999 ssize, hugeshift, psize);
1000#endif /* CONFIG_HUGETLB_PAGE */
1001
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001002#ifndef CONFIG_PPC_64K_PAGES
1003 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1004#else
1005 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1006 pte_val(*(ptep + PTRS_PER_PTE)));
1007#endif
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001008 /* Do actual hashing */
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001009#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerras721151d2007-04-03 21:24:02 +10001010 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
Paul Mackerras3a8247c2008-06-18 15:29:12 +10001011 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
Paul Mackerras721151d2007-04-03 21:24:02 +10001012 demote_segment_4k(mm, ea);
1013 psize = MMU_PAGE_4K;
1014 }
1015
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001016 /* If this PTE is non-cacheable and we have restrictions on
1017 * using non cacheable large pages, then we switch to 4k
1018 */
1019 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1020 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1021 if (user_region) {
1022 demote_segment_4k(mm, ea);
1023 psize = MMU_PAGE_4K;
1024 } else if (ea < VMALLOC_END) {
1025 /*
1026 * some driver did a non-cacheable mapping
1027 * in vmalloc space, so switch vmalloc
1028 * to 4k pages
1029 */
1030 printk(KERN_ALERT "Reducing vmalloc segment "
1031 "to 4kB pages because of "
1032 "non-cacheable mapping\n");
1033 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +10001034#ifdef CONFIG_SPU_BASE
Benjamin Herrenschmidt94b2a432007-03-10 00:05:37 +01001035 spu_flush_all_slbs(mm);
1036#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001037 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001038 }
1039 if (user_region) {
Paul Mackerras3a8247c2008-06-18 15:29:12 +10001040 if (psize != get_paca_psize(ea)) {
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +11001041 get_paca()->context = mm->context;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001042 slb_flush_and_rebolt();
1043 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001044 } else if (get_paca()->vmalloc_sllp !=
1045 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1046 get_paca()->vmalloc_sllp =
1047 mmu_psize_defs[mmu_vmalloc_psize].sllp;
Michael Neuling67439b72007-08-03 11:55:39 +10001048 slb_vmalloc_update();
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001049 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001050#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001051
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001052#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001053 if (psize == MMU_PAGE_64K)
Paul Mackerras1189be62007-10-11 20:37:10 +10001054 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001055 else
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001056#endif /* CONFIG_PPC_HAS_HASH_64K */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001057 {
David Gibsona1128f82009-12-16 14:29:56 +00001058 int spp = subpage_protection(mm, ea);
Paul Mackerrasfa282372008-01-24 08:35:13 +11001059 if (access & spp)
1060 rc = -2;
1061 else
1062 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1063 local, ssize, spp);
1064 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001065
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +10001066 /* Dump some info in case of hash insertion failure, they should
1067 * never happen so it is really useful to know if/when they do
1068 */
1069 if (rc == -1)
1070 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1071 pte_val(*ptep));
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001072#ifndef CONFIG_PPC_64K_PAGES
1073 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1074#else
1075 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1076 pte_val(*(ptep + PTRS_PER_PTE)));
1077#endif
1078 DBG_LOW(" -> rc=%d\n", rc);
1079 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080}
Arnd Bergmann67207b92005-11-15 15:53:48 -05001081EXPORT_SYMBOL_GPL(hash_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001083void hash_preload(struct mm_struct *mm, unsigned long ea,
1084 unsigned long access, unsigned long trap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001086 unsigned long vsid;
Michael Neuling0b97fee2010-11-17 18:52:45 +00001087 pgd_t *pgdir;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001088 pte_t *ptep;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001089 unsigned long flags;
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +10001090 int rc, ssize, local = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001092 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1093
1094#ifdef CONFIG_PPC_MM_SLICES
1095 /* We only prefault standard pages for now */
Ilpo Järvinen2b02d132007-08-16 08:03:35 +10001096 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001097 return;
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001098#endif
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001099
1100 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1101 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1102
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001103 /* Get Linux PTE if available */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001104 pgdir = mm->pgd;
1105 if (pgdir == NULL)
1106 return;
1107 ptep = find_linux_pte(pgdir, ea);
1108 if (!ptep)
1109 return;
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001110
1111#ifdef CONFIG_PPC_64K_PAGES
1112 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1113 * a 64K kernel), then we don't preload, hash_page() will take
1114 * care of it once we actually try to access the page.
1115 * That way we don't have to duplicate all of the logic for segment
1116 * page size demotion here
1117 */
1118 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1119 return;
1120#endif /* CONFIG_PPC_64K_PAGES */
1121
1122 /* Get VSID */
Paul Mackerras1189be62007-10-11 20:37:10 +10001123 ssize = user_segment_size(ea);
1124 vsid = get_vsid(mm->context.id, ea, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001125
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001126 /* Hash doesn't like irqs */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001127 local_irq_save(flags);
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001128
1129 /* Is that local to this CPU ? */
Rusty Russell56aa4122009-03-15 18:16:43 +00001130 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001131 local = 1;
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001132
1133 /* Hash it in */
1134#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001135 if (mm->context.user_psize == MMU_PAGE_64K)
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +10001136 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137 else
Jon Tollefson5b825832007-05-17 04:43:02 +10001138#endif /* CONFIG_PPC_HAS_HASH_64K */
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +10001139 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
Michael Neuling1c2c25c2010-11-17 16:32:59 +00001140 subpage_protection(mm, ea));
Benjamin Herrenschmidt4b8692c2010-07-23 10:31:13 +10001141
1142 /* Dump some info in case of hash insertion failure, they should
1143 * never happen so it is really useful to know if/when they do
1144 */
1145 if (rc == -1)
1146 hash_failure_debug(ea, access, vsid, trap, ssize,
1147 mm->context.user_psize, pte_val(*ptep));
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001148
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001149 local_irq_restore(flags);
1150}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +11001152/* WARNING: This is called from hash_low_64.S, if you change this prototype,
1153 * do not forget to update the assembly call site !
1154 */
Paul Mackerras1189be62007-10-11 20:37:10 +10001155void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1156 int local)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001157{
1158 unsigned long hash, index, shift, hidx, slot;
1159
Sachin P. Sant5c339912009-12-13 21:15:12 +00001160 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001161 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
Paul Mackerras1189be62007-10-11 20:37:10 +10001162 hash = hpt_hash(va, shift, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001163 hidx = __rpte_to_hidx(pte, index);
1164 if (hidx & _PTEIDX_SECONDARY)
1165 hash = ~hash;
1166 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1167 slot += hidx & _PTEIDX_GROUP_IX;
Sachin P. Sant5c339912009-12-13 21:15:12 +00001168 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
Paul Mackerras1189be62007-10-11 20:37:10 +10001169 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001170 } pte_iterate_hashed_end();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171}
1172
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001173void flush_hash_range(unsigned long number, int local)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001175 if (ppc_md.flush_hash_range)
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001176 ppc_md.flush_hash_range(number, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001177 else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178 int i;
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001179 struct ppc64_tlb_batch *batch =
1180 &__get_cpu_var(ppc64_tlb_batch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181
1182 for (i = 0; i < number; i++)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001183 flush_hash_page(batch->vaddr[i], batch->pte[i],
Paul Mackerras1189be62007-10-11 20:37:10 +10001184 batch->psize, batch->ssize, local);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185 }
1186}
1187
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188/*
1189 * low_hash_fault is called when we the low level hash code failed
1190 * to instert a PTE due to an hypervisor error
1191 */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001192void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193{
1194 if (user_mode(regs)) {
Paul Mackerrasfa282372008-01-24 08:35:13 +11001195#ifdef CONFIG_PPC_SUBPAGE_PROT
1196 if (rc == -2)
1197 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1198 else
1199#endif
1200 _exception(SIGBUS, regs, BUS_ADRERR, address);
1201 } else
1202 bad_page_fault(regs, address, SIGBUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203}
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001204
1205#ifdef CONFIG_DEBUG_PAGEALLOC
1206static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1207{
Paul Mackerras1189be62007-10-11 20:37:10 +10001208 unsigned long hash, hpteg;
1209 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1210 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +10001211 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001212 int ret;
1213
Paul Mackerras1189be62007-10-11 20:37:10 +10001214 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001215 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1216
1217 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
Paul Mackerras1189be62007-10-11 20:37:10 +10001218 mode, HPTE_V_BOLTED,
1219 mmu_linear_psize, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001220 BUG_ON (ret < 0);
1221 spin_lock(&linear_map_hash_lock);
1222 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1223 linear_map_hash_slots[lmi] = ret | 0x80;
1224 spin_unlock(&linear_map_hash_lock);
1225}
1226
1227static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1228{
Paul Mackerras1189be62007-10-11 20:37:10 +10001229 unsigned long hash, hidx, slot;
1230 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1231 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001232
Paul Mackerras1189be62007-10-11 20:37:10 +10001233 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001234 spin_lock(&linear_map_hash_lock);
1235 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1236 hidx = linear_map_hash_slots[lmi] & 0x7f;
1237 linear_map_hash_slots[lmi] = 0;
1238 spin_unlock(&linear_map_hash_lock);
1239 if (hidx & _PTEIDX_SECONDARY)
1240 hash = ~hash;
1241 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1242 slot += hidx & _PTEIDX_GROUP_IX;
Paul Mackerras1189be62007-10-11 20:37:10 +10001243 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001244}
1245
1246void kernel_map_pages(struct page *page, int numpages, int enable)
1247{
1248 unsigned long flags, vaddr, lmi;
1249 int i;
1250
1251 local_irq_save(flags);
1252 for (i = 0; i < numpages; i++, page++) {
1253 vaddr = (unsigned long)page_address(page);
1254 lmi = __pa(vaddr) >> PAGE_SHIFT;
1255 if (lmi >= linear_map_hash_count)
1256 continue;
1257 if (enable)
1258 kernel_map_linear_page(vaddr, lmi);
1259 else
1260 kernel_unmap_linear_page(vaddr, lmi);
1261 }
1262 local_irq_restore(flags);
1263}
1264#endif /* CONFIG_DEBUG_PAGEALLOC */
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -07001265
1266void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1267 phys_addr_t first_memblock_size)
1268{
1269 /* We don't currently support the first MEMBLOCK not mapping 0
1270 * physical on those processors
1271 */
1272 BUG_ON(first_memblock_base != 0);
1273
1274 /* On LPAR systems, the first entry is our RMA region,
1275 * non-LPAR 64-bit hash MMU systems don't have a limitation
1276 * on real mode access, but using the first entry works well
1277 * enough. We also clamp it to 1G to avoid some funky things
1278 * such as RTAS bugs etc...
1279 */
1280 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1281
1282 /* Finally limit subsequent allocations */
1283 memblock_set_current_limit(ppc64_rma_size);
1284}