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Roger Tsenge1237932013-02-04 15:45:59 +08001/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 *
22 * Roger Tseng <rogerable@realtek.com>
23 * No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
24 */
25
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/mfd/rtsx_pci.h>
29
30#include "rtsx_pcr.h"
31
Wei WANG773ccdf2013-08-20 14:18:51 +080032static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
33{
34 u8 driving_3v3[4][3] = {
35 {0x13, 0x13, 0x13},
36 {0x96, 0x96, 0x96},
37 {0x7F, 0x7F, 0x7F},
38 {0x96, 0x96, 0x96},
39 };
40 u8 driving_1v8[4][3] = {
41 {0x99, 0x99, 0x99},
42 {0xAA, 0xAA, 0xAA},
43 {0xFE, 0xFE, 0xFE},
44 {0xB3, 0xB3, 0xB3},
45 };
46 u8 (*driving)[3], drive_sel;
47
48 if (voltage == OUTPUT_3V3) {
49 driving = driving_3v3;
50 drive_sel = pcr->sd30_drive_sel_3v3;
51 } else {
52 driving = driving_1v8;
53 drive_sel = pcr->sd30_drive_sel_1v8;
54 }
55
56 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
57 0xFF, driving[drive_sel][0]);
58 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
59 0xFF, driving[drive_sel][1]);
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
61 0xFF, driving[drive_sel][2]);
62}
63
64static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
65{
66 u32 reg;
67
68 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
69 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
70
71 if (!rtsx_vendor_setting_valid(reg))
72 return;
73
74 pcr->aspm_en = rtsx_reg_to_aspm(reg);
75 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
76 pcr->card_drive_sel &= 0x3F;
77 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
78
79 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
80 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
82 if (rtsx_reg_check_reverse_socket(reg))
83 pcr->flags |= PCR_REVERSE_SOCKET;
84}
85
Wei WANG5947c162013-08-20 14:18:52 +080086static void rts5227_force_power_down(struct rtsx_pcr *pcr)
87{
88 /* Set relink_time to 0 */
89 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
90 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
91 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
92
93 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
94}
95
Roger Tsenge1237932013-02-04 15:45:59 +080096static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
97{
98 u16 cap;
99
100 rtsx_pci_init_cmd(pcr);
101
102 /* Configure GPIO as output */
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
Wei WANG71408122013-08-20 14:18:53 +0800104 /* Reset ASPM state to default value */
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
Roger Tsenge1237932013-02-04 15:45:59 +0800106 /* Switch LDO3318 source from DV33 to card_3v3 */
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
109 /* LED shine disabled, set initial shine cycle period */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
111 /* Configure LTR */
112 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
113 if (cap & PCI_EXP_LTR_EN)
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
115 /* Configure OBFF */
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
Wei WANG773ccdf2013-08-20 14:18:51 +0800117 /* Configure driving */
118 rts5227_fill_driving(pcr, OUTPUT_3V3);
119 /* Configure force_clock_req */
120 if (pcr->flags & PCR_REVERSE_SOCKET)
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
122 AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
123 else
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
125 AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
Roger Tsenge1237932013-02-04 15:45:59 +0800126
127 return rtsx_pci_send_cmd(pcr, 100);
128}
129
130static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
131{
132 /* Optimize RX sensitivity */
133 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
134}
135
136static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
137{
138 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
139}
140
141static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
142{
143 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
144}
145
146static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
147{
148 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
149}
150
151static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
152{
153 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
154}
155
156static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
157{
158 int err;
159
160 rtsx_pci_init_cmd(pcr);
161 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
162 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
163 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
164 LDO3318_PWR_MASK, 0x02);
165 err = rtsx_pci_send_cmd(pcr, 100);
166 if (err < 0)
167 return err;
168
169 /* To avoid too large in-rush current */
170 udelay(150);
171
172 rtsx_pci_init_cmd(pcr);
173 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
174 SD_POWER_MASK, SD_POWER_ON);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
176 LDO3318_PWR_MASK, 0x06);
177 err = rtsx_pci_send_cmd(pcr, 100);
178 if (err < 0)
179 return err;
180
181 return 0;
182}
183
184static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
185{
186 rtsx_pci_init_cmd(pcr);
187 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
188 SD_POWER_MASK | PMOS_STRG_MASK,
189 SD_POWER_OFF | PMOS_STRG_400mA);
190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
191 LDO3318_PWR_MASK, 0X00);
192 return rtsx_pci_send_cmd(pcr, 100);
193}
194
195static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
196{
197 int err;
Roger Tsenge1237932013-02-04 15:45:59 +0800198
199 if (voltage == OUTPUT_3V3) {
200 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
201 if (err < 0)
202 return err;
Roger Tsenge1237932013-02-04 15:45:59 +0800203 } else if (voltage == OUTPUT_1V8) {
204 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
205 if (err < 0)
206 return err;
207 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
208 if (err < 0)
209 return err;
Roger Tsenge1237932013-02-04 15:45:59 +0800210 } else {
211 return -EINVAL;
212 }
213
214 /* set pad drive */
215 rtsx_pci_init_cmd(pcr);
Wei WANG773ccdf2013-08-20 14:18:51 +0800216 rts5227_fill_driving(pcr, voltage);
Roger Tsenge1237932013-02-04 15:45:59 +0800217 return rtsx_pci_send_cmd(pcr, 100);
218}
219
220static const struct pcr_ops rts5227_pcr_ops = {
Wei WANG773ccdf2013-08-20 14:18:51 +0800221 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
Roger Tsenge1237932013-02-04 15:45:59 +0800222 .extra_init_hw = rts5227_extra_init_hw,
223 .optimize_phy = rts5227_optimize_phy,
224 .turn_on_led = rts5227_turn_on_led,
225 .turn_off_led = rts5227_turn_off_led,
226 .enable_auto_blink = rts5227_enable_auto_blink,
227 .disable_auto_blink = rts5227_disable_auto_blink,
228 .card_power_on = rts5227_card_power_on,
229 .card_power_off = rts5227_card_power_off,
230 .switch_output_voltage = rts5227_switch_output_voltage,
231 .cd_deglitch = NULL,
232 .conv_clk_and_div_n = NULL,
Wei WANG5947c162013-08-20 14:18:52 +0800233 .force_power_down = rts5227_force_power_down,
Roger Tsenge1237932013-02-04 15:45:59 +0800234};
235
236/* SD Pull Control Enable:
237 * SD_DAT[3:0] ==> pull up
238 * SD_CD ==> pull up
239 * SD_WP ==> pull up
240 * SD_CMD ==> pull up
241 * SD_CLK ==> pull down
242 */
243static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
244 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
245 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
246 0,
247};
248
249/* SD Pull Control Disable:
250 * SD_DAT[3:0] ==> pull down
251 * SD_CD ==> pull up
252 * SD_WP ==> pull down
253 * SD_CMD ==> pull down
254 * SD_CLK ==> pull down
255 */
256static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
257 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
258 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
259 0,
260};
261
262/* MS Pull Control Enable:
263 * MS CD ==> pull up
264 * others ==> pull down
265 */
266static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
267 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
268 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
269 0,
270};
271
272/* MS Pull Control Disable:
273 * MS CD ==> pull up
274 * others ==> pull down
275 */
276static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
277 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
278 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
279 0,
280};
281
282void rts5227_init_params(struct rtsx_pcr *pcr)
283{
284 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
285 pcr->num_slots = 2;
286 pcr->ops = &rts5227_pcr_ops;
287
Wei WANG773ccdf2013-08-20 14:18:51 +0800288 pcr->flags = 0;
289 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
290 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
291 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
292 pcr->aspm_en = ASPM_L1_EN;
293
Roger Tsenge1237932013-02-04 15:45:59 +0800294 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
295 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
296 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
297 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
298}