blob: e3e869470cd3e4f6dc5f56daf2645f85bf6f14bc [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +080017 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo73d2b4c2011-10-17 08:42:16 +080022 };
23
24 tzic: tz-interrupt-controller@0fffc000 {
25 compatible = "fsl,imx53-tzic", "fsl,tzic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
28 reg = <0x0fffc000 0x4000>;
29 };
30
31 clocks {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 ckil {
36 compatible = "fsl,imx-ckil", "fixed-clock";
37 clock-frequency = <32768>;
38 };
39
40 ckih1 {
41 compatible = "fsl,imx-ckih1", "fixed-clock";
42 clock-frequency = <22579200>;
43 };
44
45 ckih2 {
46 compatible = "fsl,imx-ckih2", "fixed-clock";
47 clock-frequency = <0>;
48 };
49
50 osc {
51 compatible = "fsl,imx-osc", "fixed-clock";
52 clock-frequency = <24000000>;
53 };
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 interrupt-parent = <&tzic>;
61 ranges;
62
63 aips@50000000 { /* AIPS1 */
64 compatible = "fsl,aips-bus", "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 reg = <0x50000000 0x10000000>;
68 ranges;
69
70 spba@50000000 {
71 compatible = "fsl,spba-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 reg = <0x50000000 0x40000>;
75 ranges;
76
77 esdhc@50004000 { /* ESDHC1 */
78 compatible = "fsl,imx53-esdhc";
79 reg = <0x50004000 0x4000>;
80 interrupts = <1>;
81 status = "disabled";
82 };
83
84 esdhc@50008000 { /* ESDHC2 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50008000 0x4000>;
87 interrupts = <2>;
88 status = "disabled";
89 };
90
Shawn Guo0c456cf2012-04-02 14:39:26 +080091 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +080092 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>;
95 status = "disabled";
96 };
97
98 ecspi@50010000 { /* ECSPI1 */
99 #address-cells = <1>;
100 #size-cells = <0>;
101 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
102 reg = <0x50010000 0x4000>;
103 interrupts = <36>;
104 status = "disabled";
105 };
106
Shawn Guoffc505c2012-05-11 13:12:01 +0800107 ssi2: ssi@50014000 {
108 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
109 reg = <0x50014000 0x4000>;
110 interrupts = <30>;
111 fsl,fifo-depth = <15>;
112 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
113 status = "disabled";
114 };
115
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800116 esdhc@50020000 { /* ESDHC3 */
117 compatible = "fsl,imx53-esdhc";
118 reg = <0x50020000 0x4000>;
119 interrupts = <3>;
120 status = "disabled";
121 };
122
123 esdhc@50024000 { /* ESDHC4 */
124 compatible = "fsl,imx53-esdhc";
125 reg = <0x50024000 0x4000>;
126 interrupts = <4>;
127 status = "disabled";
128 };
129 };
130
Richard Zhao4d191862011-12-14 09:26:44 +0800131 gpio1: gpio@53f84000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800132 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
133 reg = <0x53f84000 0x4000>;
134 interrupts = <50 51>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 };
140
Richard Zhao4d191862011-12-14 09:26:44 +0800141 gpio2: gpio@53f88000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800142 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
143 reg = <0x53f88000 0x4000>;
144 interrupts = <52 53>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 interrupt-controller;
148 #interrupt-cells = <1>;
149 };
150
Richard Zhao4d191862011-12-14 09:26:44 +0800151 gpio3: gpio@53f8c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800152 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
153 reg = <0x53f8c000 0x4000>;
154 interrupts = <54 55>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <1>;
159 };
160
Richard Zhao4d191862011-12-14 09:26:44 +0800161 gpio4: gpio@53f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800162 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
163 reg = <0x53f90000 0x4000>;
164 interrupts = <56 57>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 interrupt-controller;
168 #interrupt-cells = <1>;
169 };
170
171 wdog@53f98000 { /* WDOG1 */
172 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
173 reg = <0x53f98000 0x4000>;
174 interrupts = <58>;
175 status = "disabled";
176 };
177
178 wdog@53f9c000 { /* WDOG2 */
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f9c000 0x4000>;
181 interrupts = <59>;
182 status = "disabled";
183 };
184
Shawn Guo0c456cf2012-04-02 14:39:26 +0800185 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800186 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
187 reg = <0x53fbc000 0x4000>;
188 interrupts = <31>;
189 status = "disabled";
190 };
191
Shawn Guo0c456cf2012-04-02 14:39:26 +0800192 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800193 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fc0000 0x4000>;
195 interrupts = <32>;
196 status = "disabled";
197 };
198
Richard Zhao4d191862011-12-14 09:26:44 +0800199 gpio5: gpio@53fdc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800200 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
201 reg = <0x53fdc000 0x4000>;
202 interrupts = <103 104>;
203 gpio-controller;
204 #gpio-cells = <2>;
205 interrupt-controller;
206 #interrupt-cells = <1>;
207 };
208
Richard Zhao4d191862011-12-14 09:26:44 +0800209 gpio6: gpio@53fe0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800210 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
211 reg = <0x53fe0000 0x4000>;
212 interrupts = <105 106>;
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 };
218
Richard Zhao4d191862011-12-14 09:26:44 +0800219 gpio7: gpio@53fe4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800220 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
221 reg = <0x53fe4000 0x4000>;
222 interrupts = <107 108>;
223 gpio-controller;
224 #gpio-cells = <2>;
225 interrupt-controller;
226 #interrupt-cells = <1>;
227 };
228
229 i2c@53fec000 { /* I2C3 */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
233 reg = <0x53fec000 0x4000>;
234 interrupts = <64>;
235 status = "disabled";
236 };
237
Shawn Guo0c456cf2012-04-02 14:39:26 +0800238 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800239 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
240 reg = <0x53ff0000 0x4000>;
241 interrupts = <13>;
242 status = "disabled";
243 };
244 };
245
246 aips@60000000 { /* AIPS2 */
247 compatible = "fsl,aips-bus", "simple-bus";
248 #address-cells = <1>;
249 #size-cells = <1>;
250 reg = <0x60000000 0x10000000>;
251 ranges;
252
Shawn Guo0c456cf2012-04-02 14:39:26 +0800253 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800254 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
255 reg = <0x63f90000 0x4000>;
256 interrupts = <86>;
257 status = "disabled";
258 };
259
260 ecspi@63fac000 { /* ECSPI2 */
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
264 reg = <0x63fac000 0x4000>;
265 interrupts = <37>;
266 status = "disabled";
267 };
268
269 sdma@63fb0000 {
270 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
271 reg = <0x63fb0000 0x4000>;
272 interrupts = <6>;
273 };
274
275 cspi@63fc0000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
279 reg = <0x63fc0000 0x4000>;
280 interrupts = <38>;
281 status = "disabled";
282 };
283
284 i2c@63fc4000 { /* I2C2 */
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
288 reg = <0x63fc4000 0x4000>;
289 interrupts = <63>;
290 status = "disabled";
291 };
292
293 i2c@63fc8000 { /* I2C1 */
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
297 reg = <0x63fc8000 0x4000>;
298 interrupts = <62>;
299 status = "disabled";
300 };
301
Shawn Guoffc505c2012-05-11 13:12:01 +0800302 ssi1: ssi@63fcc000 {
303 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
304 reg = <0x63fcc000 0x4000>;
305 interrupts = <29>;
306 fsl,fifo-depth = <15>;
307 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
308 status = "disabled";
309 };
310
311 audmux@63fd0000 {
312 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
313 reg = <0x63fd0000 0x4000>;
314 status = "disabled";
315 };
316
317 ssi3: ssi@63fe8000 {
318 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
319 reg = <0x63fe8000 0x4000>;
320 interrupts = <96>;
321 fsl,fifo-depth = <15>;
322 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
323 status = "disabled";
324 };
325
Shawn Guo0c456cf2012-04-02 14:39:26 +0800326 ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800327 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
328 reg = <0x63fec000 0x4000>;
329 interrupts = <87>;
330 status = "disabled";
331 };
332 };
333 };
334};