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gerrit-public.fairphone.software / kernel / msm-4.19 / 72aafdf01d826ad9e6fbd52bf689be937679f5d6 / . / arch / x86 / include / asm / tsc.h
blob: 174c4212780afde12200fd23a1dbc17a08f40309 [file] [log] [blame]
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]1/*
Thomas Gleixner2f0798a2007-10-12 23:04:23 +0200[diff] [blame]2 * x86 TSC related functions
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]3 */
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]4#ifndef _ASM_X86_TSC_H
5#define _ASM_X86_TSC_H
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]6
7#include <asm/processor.h>
8
Thomas Gleixner2f0798a2007-10-12 23:04:23 +0200[diff] [blame]9#define NS_SCALE 10 /* 2^10, carefully chosen */
10#define US_SCALE 32 /* 2^32, arbitralrily chosen */
11
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]12/*
13 * Standard way to access the cycle counter.
14 */
15typedef unsigned long long cycles_t;
16
17extern unsigned int cpu_khz;
18extern unsigned int tsc_khz;
Glauber de Oliveira Costa73018a62008-01-30 13:31:26 +0100[diff] [blame]19
20extern void disable_TSC(void);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]21
22static inline cycles_t get_cycles(void)
23{
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]24#ifndef CONFIG_X86_TSC
25 if (!cpu_has_tsc)
26 return 0;
27#endif
Ingo Molnar75f2ce02008-01-30 13:33:24 +0100[diff] [blame]28
Andy Lutomirski4ea16362015-06-25 18:44:07 +0200[diff] [blame]29 return rdtsc();
Andi Kleen6d63de82008-01-30 13:32:39 +0100[diff] [blame]30}
Glauber de Oliveira Costa4e871732008-01-30 13:31:03 +0100[diff] [blame]31
Christopher S. Hallf9677e02016-02-29 06:33:47 -0800[diff] [blame]32extern struct system_counterval_t convert_art_to_tsc(cycle_t art);
33
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]34extern void tsc_init(void);
john stultz5a90cf22007-05-02 19:27:08 +0200[diff] [blame]35extern void mark_tsc_unstable(char *reason);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]36extern int unsynchronized_tsc(void);
Thomas Gleixner2d826402009-08-20 17:06:25 +0200[diff] [blame]37extern int check_tsc_unstable(void);
Adrian Hunterc73deb62013-06-28 16:22:18 +0300[diff] [blame]38extern int check_tsc_disabled(void);
Thomas Gleixner2d826402009-08-20 17:06:25 +0200[diff] [blame]39extern unsigned long native_calibrate_tsc(void);
Andi Kleena94cab22015-05-10 12:22:39 -0700[diff] [blame]40extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]41
Suresh Siddha28a00182011-11-04 15:42:17 -0700[diff] [blame]42extern int tsc_clocksource_reliable;
43
Andres Salomon2272b0e2007-03-06 01:42:05 -0800[diff] [blame]44/*
45 * Boot-time check whether the TSCs are synchronized across
46 * all CPUs/cores:
47 */
48extern void check_tsc_sync_source(int cpu);
49extern void check_tsc_sync_target(void);
50
Thomas Gleixner80ca9c92008-01-30 13:30:18 +0100[diff] [blame]51extern int notsc_setup(char *);
Marcelo Tosattib74f05d2012-02-13 11:07:27 -0200[diff] [blame]52extern void tsc_save_sched_clock_state(void);
53extern void tsc_restore_sched_clock_state(void);
Thomas Gleixnerd3716982007-10-12 23:04:06 +0200[diff] [blame]54
Bin Gao7da7c152013-10-21 09:16:33 -0700[diff] [blame]55/* MSR based TSC calibration for Intel Atom SoC platforms */
Thomas Gleixner5f0e0302014-02-19 13:52:29 +0200[diff] [blame]56unsigned long try_msr_calibrate_tsc(void);
Bin Gao7da7c152013-10-21 09:16:33 -0700[diff] [blame]57
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]58#endif /* _ASM_X86_TSC_H */