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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* vi: ts=8 sw=8
2 *
3 * TI 3410/5052 USB Serial Driver Header
4 *
5 * Copyright (C) 2004 Texas Instruments
6 *
7 * This driver is based on the Linux io_ti driver, which is
8 * Copyright (C) 2000-2002 Inside Out Networks
9 * Copyright (C) 2001-2002 Greg Kroah-Hartman
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * For questions or problems with this driver, contact Texas Instruments
17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or
18 * Peter Berger <pberger@brimson.com>.
19 */
20
21#ifndef _TI_3410_5052_H_
22#define _TI_3410_5052_H_
23
24/* Configuration ids */
25#define TI_BOOT_CONFIG 1
26#define TI_ACTIVE_CONFIG 2
27
28/* Vendor and product ids */
29#define TI_VENDOR_ID 0x0451
Oliver Neukum1a1fab512009-01-12 13:31:16 +010030#define IBM_VENDOR_ID 0x04b3
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#define TI_3410_PRODUCT_ID 0x3410
Oliver Neukum1a1fab512009-01-12 13:31:16 +010032#define IBM_4543_PRODUCT_ID 0x4543
Oliver Neukum97dcf042009-02-04 16:38:33 +010033#define IBM_454B_PRODUCT_ID 0x454b
34#define IBM_454C_PRODUCT_ID 0x454c
Oleg Verych1f54a6a2006-11-17 08:21:27 +000035#define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */
37#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */
38#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */
39#define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */
40
Chris Adamscb7a7c62009-01-11 19:49:00 +000041/* Multi-Tech vendor and product ids */
42#define MTS_VENDOR_ID 0x06E0
43#define MTS_GSM_NO_FW_PRODUCT_ID 0xF108
44#define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109
45#define MTS_CDMA_PRODUCT_ID 0xF110
46#define MTS_GSM_PRODUCT_ID 0xF111
47#define MTS_EDGE_PRODUCT_ID 0xF112
Alex Manoussakiscdc04832010-04-22 15:18:20 -070048#define MTS_MT9234MU_PRODUCT_ID 0xF114
49#define MTS_MT9234ZBA_PRODUCT_ID 0xF115
50#define MTS_MT9234ZBAOLD_PRODUCT_ID 0x0319
Chris Adamscb7a7c62009-01-11 19:49:00 +000051
Andrew Lunn7fd25702012-02-20 09:31:57 +010052/* Abbott Diabetics vendor and product ids */
53#define ABBOTT_VENDOR_ID 0x1a61
54#define ABBOTT_PRODUCT_ID 0x3410
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056/* Commands */
57#define TI_GET_VERSION 0x01
58#define TI_GET_PORT_STATUS 0x02
59#define TI_GET_PORT_DEV_INFO 0x03
60#define TI_GET_CONFIG 0x04
61#define TI_SET_CONFIG 0x05
62#define TI_OPEN_PORT 0x06
63#define TI_CLOSE_PORT 0x07
64#define TI_START_PORT 0x08
65#define TI_STOP_PORT 0x09
66#define TI_TEST_PORT 0x0A
67#define TI_PURGE_PORT 0x0B
68#define TI_RESET_EXT_DEVICE 0x0C
69#define TI_WRITE_DATA 0x80
70#define TI_READ_DATA 0x81
71#define TI_REQ_TYPE_CLASS 0x82
72
73/* Module identifiers */
74#define TI_I2C_PORT 0x01
75#define TI_IEEE1284_PORT 0x02
76#define TI_UART1_PORT 0x03
77#define TI_UART2_PORT 0x04
78#define TI_RAM_PORT 0x05
79
80/* Modem status */
81#define TI_MSR_DELTA_CTS 0x01
82#define TI_MSR_DELTA_DSR 0x02
83#define TI_MSR_DELTA_RI 0x04
84#define TI_MSR_DELTA_CD 0x08
85#define TI_MSR_CTS 0x10
86#define TI_MSR_DSR 0x20
87#define TI_MSR_RI 0x40
88#define TI_MSR_CD 0x80
89#define TI_MSR_DELTA_MASK 0x0F
90#define TI_MSR_MASK 0xF0
91
92/* Line status */
93#define TI_LSR_OVERRUN_ERROR 0x01
94#define TI_LSR_PARITY_ERROR 0x02
95#define TI_LSR_FRAMING_ERROR 0x04
96#define TI_LSR_BREAK 0x08
97#define TI_LSR_ERROR 0x0F
98#define TI_LSR_RX_FULL 0x10
99#define TI_LSR_TX_EMPTY 0x20
100
101/* Line control */
102#define TI_LCR_BREAK 0x40
103
104/* Modem control */
105#define TI_MCR_LOOP 0x04
106#define TI_MCR_DTR 0x10
107#define TI_MCR_RTS 0x20
108
109/* Mask settings */
110#define TI_UART_ENABLE_RTS_IN 0x0001
111#define TI_UART_DISABLE_RTS 0x0002
112#define TI_UART_ENABLE_PARITY_CHECKING 0x0008
113#define TI_UART_ENABLE_DSR_OUT 0x0010
114#define TI_UART_ENABLE_CTS_OUT 0x0020
115#define TI_UART_ENABLE_X_OUT 0x0040
116#define TI_UART_ENABLE_XA_OUT 0x0080
117#define TI_UART_ENABLE_X_IN 0x0100
118#define TI_UART_ENABLE_DTR_IN 0x0800
119#define TI_UART_DISABLE_DTR 0x1000
120#define TI_UART_ENABLE_MS_INTS 0x2000
121#define TI_UART_ENABLE_AUTO_START_DMA 0x4000
122
123/* Parity */
124#define TI_UART_NO_PARITY 0x00
125#define TI_UART_ODD_PARITY 0x01
126#define TI_UART_EVEN_PARITY 0x02
127#define TI_UART_MARK_PARITY 0x03
128#define TI_UART_SPACE_PARITY 0x04
129
130/* Stop bits */
131#define TI_UART_1_STOP_BITS 0x00
132#define TI_UART_1_5_STOP_BITS 0x01
133#define TI_UART_2_STOP_BITS 0x02
134
135/* Bits per character */
136#define TI_UART_5_DATA_BITS 0x00
137#define TI_UART_6_DATA_BITS 0x01
138#define TI_UART_7_DATA_BITS 0x02
139#define TI_UART_8_DATA_BITS 0x03
140
141/* 232/485 modes */
142#define TI_UART_232 0x00
143#define TI_UART_485_RECEIVER_DISABLED 0x01
144#define TI_UART_485_RECEIVER_ENABLED 0x02
145
146/* Pipe transfer mode and timeout */
147#define TI_PIPE_MODE_CONTINOUS 0x01
148#define TI_PIPE_MODE_MASK 0x03
149#define TI_PIPE_TIMEOUT_MASK 0x7C
150#define TI_PIPE_TIMEOUT_ENABLE 0x80
151
152/* Config struct */
153struct ti_uart_config {
154 __u16 wBaudRate;
155 __u16 wFlags;
156 __u8 bDataBits;
157 __u8 bParity;
158 __u8 bStopBits;
159 char cXon;
160 char cXoff;
161 __u8 bUartMode;
162} __attribute__((packed));
163
164/* Get port status */
165struct ti_port_status {
166 __u8 bCmdCode;
167 __u8 bModuleId;
168 __u8 bErrorCode;
169 __u8 bMSR;
170 __u8 bLSR;
171} __attribute__((packed));
172
173/* Purge modes */
174#define TI_PURGE_OUTPUT 0x00
175#define TI_PURGE_INPUT 0x80
176
177/* Read/Write data */
178#define TI_RW_DATA_ADDR_SFR 0x10
179#define TI_RW_DATA_ADDR_IDATA 0x20
180#define TI_RW_DATA_ADDR_XDATA 0x30
181#define TI_RW_DATA_ADDR_CODE 0x40
182#define TI_RW_DATA_ADDR_GPIO 0x50
183#define TI_RW_DATA_ADDR_I2C 0x60
184#define TI_RW_DATA_ADDR_FLASH 0x70
185#define TI_RW_DATA_ADDR_DSP 0x80
186
187#define TI_RW_DATA_UNSPECIFIED 0x00
188#define TI_RW_DATA_BYTE 0x01
189#define TI_RW_DATA_WORD 0x02
190#define TI_RW_DATA_DOUBLE_WORD 0x04
191
192struct ti_write_data_bytes {
193 __u8 bAddrType;
194 __u8 bDataType;
195 __u8 bDataCounter;
196 __be16 wBaseAddrHi;
197 __be16 wBaseAddrLo;
198 __u8 bData[0];
199} __attribute__((packed));
200
201struct ti_read_data_request {
202 __u8 bAddrType;
203 __u8 bDataType;
204 __u8 bDataCounter;
205 __be16 wBaseAddrHi;
206 __be16 wBaseAddrLo;
207} __attribute__((packed));
208
209struct ti_read_data_bytes {
210 __u8 bCmdCode;
211 __u8 bModuleId;
212 __u8 bErrorCode;
213 __u8 bData[0];
214} __attribute__((packed));
215
216/* Interrupt struct */
217struct ti_interrupt {
218 __u8 bICode;
219 __u8 bIInfo;
220} __attribute__((packed));
221
222/* Interrupt codes */
223#define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
224#define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
225#define TI_CODE_HARDWARE_ERROR 0xFF
226#define TI_CODE_DATA_ERROR 0x03
227#define TI_CODE_MODEM_STATUS 0x04
228
229/* Download firmware max packet size */
230#define TI_DOWNLOAD_MAX_PACKET_SIZE 64
231
232/* Firmware image header */
233struct ti_firmware_header {
234 __le16 wLength;
235 __u8 bCheckSum;
236} __attribute__((packed));
237
238/* UART addresses */
239#define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */
240#define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */
241#define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */
242#define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */
243
244#endif /* _TI_3410_5052_H_ */