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Graf Yangc51b4482009-01-07 23:14:39 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2007-2009 Analog Devices Inc.
3 * Philippe Gerum <rpm@xenomai.org>
Graf Yangc51b4482009-01-07 23:14:39 +08004 *
Robin Getz96f10502009-09-24 14:11:24 +00005 * Licensed under the GPL-2 or later.
Graf Yangc51b4482009-01-07 23:14:39 +08006 */
7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/delay.h>
12#include <asm/smp.h>
13#include <asm/dma.h>
Yi Li0d152c22009-12-28 10:21:49 +000014#include <asm/time.h>
Graf Yangc51b4482009-01-07 23:14:39 +080015
Graf Yangc51b4482009-01-07 23:14:39 +080016static DEFINE_SPINLOCK(boot_lock);
17
Graf Yangc51b4482009-01-07 23:14:39 +080018/*
19 * platform_init_cpus() - Tell the world about how many cores we
20 * have. This is called while setting up the architecture support
21 * (setup_arch()), so don't be too demanding here with respect to
22 * available kernel services.
23 */
24
25void __init platform_init_cpus(void)
26{
27 cpu_set(0, cpu_possible_map); /* CoreA */
28 cpu_set(1, cpu_possible_map); /* CoreB */
29}
30
31void __init platform_prepare_cpus(unsigned int max_cpus)
32{
33 int len;
34
35 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
Graf Yangdbc895f2009-01-07 23:14:39 +080036 BUG_ON(len > L1_CODE_LENGTH);
Graf Yangc51b4482009-01-07 23:14:39 +080037
Graf Yangdbc895f2009-01-07 23:14:39 +080038 dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
Graf Yangc51b4482009-01-07 23:14:39 +080039
40 /* Both cores ought to be present on a bf561! */
41 cpu_set(0, cpu_present_map); /* CoreA */
42 cpu_set(1, cpu_present_map); /* CoreB */
43
Graf Yangdbc895f2009-01-07 23:14:39 +080044 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
Graf Yangc51b4482009-01-07 23:14:39 +080045}
46
47int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
48{
49 return -EINVAL;
50}
51
52void __cpuinit platform_secondary_init(unsigned int cpu)
53{
Graf Yangc51b4482009-01-07 23:14:39 +080054 /* Clone setup for peripheral interrupt sources from CoreA. */
Mike Frysinger39c99962010-10-19 18:44:23 +000055 bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
56 bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
Graf Yangc51b4482009-01-07 23:14:39 +080057 SSYNC();
58
59 /* Clone setup for IARs from CoreA. */
Mike Frysinger39c99962010-10-19 18:44:23 +000060 bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
61 bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
62 bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
63 bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
64 bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
65 bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
66 bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
67 bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
Graf Yang0b39db22009-12-28 11:13:51 +000068 bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
Graf Yangc51b4482009-01-07 23:14:39 +080070 SSYNC();
71
Graf Yangc51b4482009-01-07 23:14:39 +080072 /* Store CPU-private information to the cpu_data array. */
73 bfin_setup_cpudata(cpu);
74
75 /* We are done with local CPU inits, unblock the boot CPU. */
Graf Yang682f5dc2009-12-28 09:27:27 +000076 set_cpu_online(cpu, true);
Graf Yangc51b4482009-01-07 23:14:39 +080077 spin_lock(&boot_lock);
78 spin_unlock(&boot_lock);
79}
80
81int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
82{
83 unsigned long timeout;
84
Graf Yangc51b4482009-01-07 23:14:39 +080085 printk(KERN_INFO "Booting Core B.\n");
86
87 spin_lock(&boot_lock);
88
Mike Frysinger94a038c2010-10-27 10:06:32 -040089 if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
Graf Yang0b39db22009-12-28 11:13:51 +000090 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
Mike Frysinger94a038c2010-10-27 10:06:32 -040094 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
Graf Yang0b39db22009-12-28 11:13:51 +000095 SSYNC();
96 }
Graf Yangc51b4482009-01-07 23:14:39 +080097
98 timeout = jiffies + 1 * HZ;
99 while (time_before(jiffies, timeout)) {
Graf Yang682f5dc2009-12-28 09:27:27 +0000100 if (cpu_online(cpu))
Graf Yangc51b4482009-01-07 23:14:39 +0800101 break;
102 udelay(100);
103 barrier();
104 }
105
Graf Yang682f5dc2009-12-28 09:27:27 +0000106 if (cpu_online(cpu)) {
Yi Li578d36f2009-12-02 07:58:12 +0000107 /* release the lock and let coreb run */
108 spin_unlock(&boot_lock);
109 return 0;
110 } else
111 panic("CPU%u: processor failed to boot\n", cpu);
Graf Yangc51b4482009-01-07 23:14:39 +0800112}
113
Yi Li73a40062009-12-17 08:20:32 +0000114static const char supple0[] = "IRQ_SUPPLE_0";
115static const char supple1[] = "IRQ_SUPPLE_1";
116void __init platform_request_ipi(int irq, void *handler)
Graf Yangc51b4482009-01-07 23:14:39 +0800117{
118 int ret;
Yi Li73a40062009-12-17 08:20:32 +0000119 const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
Graf Yangc51b4482009-01-07 23:14:39 +0800120
Yi Li73a40062009-12-17 08:20:32 +0000121 ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
Graf Yangc51b4482009-01-07 23:14:39 +0800122 if (ret)
Yi Li73a40062009-12-17 08:20:32 +0000123 panic("Cannot request %s for IPI service", name);
Graf Yangc51b4482009-01-07 23:14:39 +0800124}
125
Yi Li73a40062009-12-17 08:20:32 +0000126void platform_send_ipi(cpumask_t callmap, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800127{
128 unsigned int cpu;
Yi Li73a40062009-12-17 08:20:32 +0000129 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
Graf Yangc51b4482009-01-07 23:14:39 +0800130
131 for_each_cpu_mask(cpu, callmap) {
132 BUG_ON(cpu >= 2);
133 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000134 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800135 SSYNC();
136 }
137}
138
Yi Li73a40062009-12-17 08:20:32 +0000139void platform_send_ipi_cpu(unsigned int cpu, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800140{
Yi Li73a40062009-12-17 08:20:32 +0000141 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
Graf Yangc51b4482009-01-07 23:14:39 +0800142 BUG_ON(cpu >= 2);
143 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000144 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800145 SSYNC();
146}
147
Yi Li73a40062009-12-17 08:20:32 +0000148void platform_clear_ipi(unsigned int cpu, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800149{
Yi Li73a40062009-12-17 08:20:32 +0000150 int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
Graf Yangc51b4482009-01-07 23:14:39 +0800151 BUG_ON(cpu >= 2);
152 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000153 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800154 SSYNC();
155}
Yi Li0d152c22009-12-28 10:21:49 +0000156
157/*
158 * Setup core B's local core timer.
159 * In SMP, core timer is used for clock event device.
160 */
161void __cpuinit bfin_local_timer_setup(void)
162{
163#if defined(CONFIG_TICKSOURCE_CORETMR)
164 bfin_coretmr_init();
165 bfin_coretmr_clockevent_init();
166 get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR);
167#else
168 /* Power down the core timer, just to play safe. */
169 bfin_write_TCNTL(0);
170#endif
171
172}