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gerrit-public.fairphone.software / kernel / msm-4.19 / 741edc494978bc2770e891b8cfadbca3246a3d1a / . / arch / powerpc / boot / dts / mpc8572ds.dts
blob: 174d51aff9240908e47471cca704e1c455a47add [file] [log] [blame]
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]1/*
2 * MPC8572 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 };
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]46
47 PowerPC,8572@1 {
48 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]49 reg = <0x1>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]54 timebase-frequency = <0>;
55 bus-frequency = <0>;
56 clock-frequency = <0>;
57 };
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]58 };
59
60 memory {
61 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]62 reg = <0x0 0x0>; // Filled by U-Boot
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]63 };
64
65 soc8572@ffe00000 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 device_type = "soc";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]69 ranges = <0x0 0xffe00000 0x100000>;
70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]71 bus-frequency = <0>; // Filled out by uboot.
72
73 memory-controller@2000 {
74 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]75 reg = <0x2000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]76 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]77 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]78 };
79
80 memory-controller@6000 {
81 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]82 reg = <0x6000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]83 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]84 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]85 };
86
87 l2-cache-controller@20000 {
88 compatible = "fsl,mpc8572-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]89 reg = <0x20000 0x1000>;
90 cache-line-size = <32>; // 32 bytes
91 cache-size = <0x80000>; // L2, 512K
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]92 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]93 interrupts = <16 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]94 };
95
96 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]97 #address-cells = <1>;
98 #size-cells = <0>;
99 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]100 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]101 reg = <0x3000 0x100>;
102 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]103 interrupt-parent = <&mpic>;
104 dfsrr;
105 };
106
107 i2c@3100 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]108 #address-cells = <1>;
109 #size-cells = <0>;
110 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]111 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]112 reg = <0x3100 0x100>;
113 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]114 interrupt-parent = <&mpic>;
115 dfsrr;
116 };
117
118 mdio@24520 {
119 #address-cells = <1>;
120 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]121 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]122 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]123
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]124 phy0: ethernet-phy@0 {
125 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]126 interrupts = <10 1>;
127 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]128 };
129 phy1: ethernet-phy@1 {
130 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]131 interrupts = <10 1>;
132 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]133 };
134 phy2: ethernet-phy@2 {
135 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]136 interrupts = <10 1>;
137 reg = <0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]138 };
139 phy3: ethernet-phy@3 {
140 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]141 interrupts = <10 1>;
142 reg = <0x3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]143 };
144 };
145
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]146 enet0: ethernet@24000 {
147 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]148 device_type = "network";
149 model = "eTSEC";
150 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]151 reg = <0x24000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]152 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]153 interrupts = <29 2 30 2 34 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy0>;
156 phy-connection-type = "rgmii-id";
157 };
158
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]159 enet1: ethernet@25000 {
160 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]161 device_type = "network";
162 model = "eTSEC";
163 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]164 reg = <0x25000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]165 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]166 interrupts = <35 2 36 2 40 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy1>;
169 phy-connection-type = "rgmii-id";
170 };
171
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]172 enet2: ethernet@26000 {
173 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]174 device_type = "network";
175 model = "eTSEC";
176 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]177 reg = <0x26000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]178 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]179 interrupts = <31 2 32 2 33 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]180 interrupt-parent = <&mpic>;
181 phy-handle = <&phy2>;
182 phy-connection-type = "rgmii-id";
183 };
184
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]185 enet3: ethernet@27000 {
186 cell-index = <3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]187 device_type = "network";
188 model = "eTSEC";
189 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]190 reg = <0x27000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]191 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]192 interrupts = <37 2 38 2 39 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]193 interrupt-parent = <&mpic>;
194 phy-handle = <&phy3>;
195 phy-connection-type = "rgmii-id";
196 };
197
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]198 serial0: serial@4500 {
199 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]200 device_type = "serial";
201 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]202 reg = <0x4500 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]203 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]204 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]205 interrupt-parent = <&mpic>;
206 };
207
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]208 serial1: serial@4600 {
209 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]210 device_type = "serial";
211 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]212 reg = <0x4600 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]213 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]214 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]215 interrupt-parent = <&mpic>;
216 };
217
218 global-utilities@e0000 { //global utilities block
219 compatible = "fsl,mpc8572-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]220 reg = <0xe0000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]221 fsl,has-rstcr;
222 };
223
Jason Jin741edc42008-05-23 16:32:48 +0800[diff] [blame^]224 msi@41600 {
225 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
226 reg = <0x41600 0x80>;
227 msi-available-ranges = <0 0x100>;
228 interrupts = <
229 0xe0 0
230 0xe1 0
231 0xe2 0
232 0xe3 0
233 0xe4 0
234 0xe5 0
235 0xe6 0
236 0xe7 0>;
237 interrupt-parent = <&mpic>;
238 };
239
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]240 mpic: pic@40000 {
241 clock-frequency = <0>;
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]245 reg = <0x40000 0x40000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]246 compatible = "chrp,open-pic";
247 device_type = "open-pic";
248 big-endian;
249 };
250 };
251
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]252 pci0: pcie@ffe08000 {
253 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]254 compatible = "fsl,mpc8548-pcie";
255 device_type = "pci";
256 #interrupt-cells = <1>;
257 #size-cells = <2>;
258 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]259 reg = <0xffe08000 0x1000>;
260 bus-range = <0 255>;
261 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
262 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
263 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]264 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]265 interrupts = <24 2>;
266 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]267 interrupt-map = <
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]268 /* IDSEL 0x11 func 0 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]269 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
270 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
271 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
272 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]273
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]274 /* IDSEL 0x11 func 1 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]275 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
276 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
277 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
278 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]279
280 /* IDSEL 0x11 func 2 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]281 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
282 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
283 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
284 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]285
286 /* IDSEL 0x11 func 3 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]287 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
288 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
289 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
290 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]291
292 /* IDSEL 0x11 func 4 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]293 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
294 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
295 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
296 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]297
298 /* IDSEL 0x11 func 5 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]299 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
300 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
301 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
302 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]303
304 /* IDSEL 0x11 func 6 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]305 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
306 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
307 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
308 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]309
310 /* IDSEL 0x11 func 7 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]311 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
312 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
313 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
314 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]315
316 /* IDSEL 0x12 func 0 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]317 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
318 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
319 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
320 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]321
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]322 /* IDSEL 0x12 func 1 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]323 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
324 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
325 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
326 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]327
328 /* IDSEL 0x12 func 2 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]329 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
330 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
331 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
332 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]333
334 /* IDSEL 0x12 func 3 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]335 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
336 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
337 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
338 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]339
340 /* IDSEL 0x12 func 4 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]341 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
342 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
343 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
344 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]345
346 /* IDSEL 0x12 func 5 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]347 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
348 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
349 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
350 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]351
352 /* IDSEL 0x12 func 6 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]353 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
354 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
355 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
356 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]357
358 /* IDSEL 0x12 func 7 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]359 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
360 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
361 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
362 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]363
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]364 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]365 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
366 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
367 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
368 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]369
370 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]371 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]372
373 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]374 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
375 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]376
377 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]378 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
379 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]380
381 >;
382
383 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]384 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]385 #size-cells = <2>;
386 #address-cells = <3>;
387 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]388 ranges = <0x2000000 0x0 0x80000000
389 0x2000000 0x0 0x80000000
390 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]391
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]392 0x1000000 0x0 0x0
393 0x1000000 0x0 0x0
394 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]395 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]396 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]397 #size-cells = <2>;
398 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]399 ranges = <0x2000000 0x0 0x80000000
400 0x2000000 0x0 0x80000000
401 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]402
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]403 0x1000000 0x0 0x0
404 0x1000000 0x0 0x0
405 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]406 isa@1e {
407 device_type = "isa";
408 #interrupt-cells = <2>;
409 #size-cells = <1>;
410 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]411 reg = <0xf000 0x0 0x0 0x0 0x0>;
412 ranges = <0x1 0x0 0x1000000 0x0 0x0
413 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]414 interrupt-parent = <&i8259>;
415
416 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]417 reg = <0x1 0x20 0x2
418 0x1 0xa0 0x2
419 0x1 0x4d0 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]420 interrupt-controller;
421 device_type = "interrupt-controller";
422 #address-cells = <0>;
423 #interrupt-cells = <2>;
424 compatible = "chrp,iic";
425 interrupts = <9 2>;
426 interrupt-parent = <&mpic>;
427 };
428
429 i8042@60 {
430 #size-cells = <0>;
431 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]432 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
433 interrupts = <1 3 12 3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]434 interrupt-parent =
435 <&i8259>;
436
437 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]438 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]439 compatible = "pnpPNP,303";
440 };
441
442 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]443 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]444 compatible = "pnpPNP,f03";
445 };
446 };
447
448 rtc@70 {
449 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]450 reg = <0x1 0x70 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]451 };
452
453 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]454 reg = <0x1 0x400 0x80>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]455 };
456 };
457 };
458 };
459
460 };
461
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]462 pci1: pcie@ffe09000 {
463 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]464 compatible = "fsl,mpc8548-pcie";
465 device_type = "pci";
466 #interrupt-cells = <1>;
467 #size-cells = <2>;
468 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]469 reg = <0xffe09000 0x1000>;
470 bus-range = <0 255>;
471 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
472 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
473 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]474 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]475 interrupts = <26 2>;
476 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]477 interrupt-map = <
478 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]479 0000 0x0 0x0 0x1 &mpic 0x4 0x1
480 0000 0x0 0x0 0x2 &mpic 0x5 0x1
481 0000 0x0 0x0 0x3 &mpic 0x6 0x1
482 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]483 >;
484 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]485 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]486 #size-cells = <2>;
487 #address-cells = <3>;
488 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]489 ranges = <0x2000000 0x0 0xa0000000
490 0x2000000 0x0 0xa0000000
491 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]492
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]493 0x1000000 0x0 0x0
494 0x1000000 0x0 0x0
495 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]496 };
497 };
498
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]499 pci2: pcie@ffe0a000 {
500 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]501 compatible = "fsl,mpc8548-pcie";
502 device_type = "pci";
503 #interrupt-cells = <1>;
504 #size-cells = <2>;
505 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]506 reg = <0xffe0a000 0x1000>;
507 bus-range = <0 255>;
508 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
509 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
510 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]511 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]512 interrupts = <27 2>;
513 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]514 interrupt-map = <
515 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]516 0000 0x0 0x0 0x1 &mpic 0x0 0x1
517 0000 0x0 0x0 0x2 &mpic 0x1 0x1
518 0000 0x0 0x0 0x3 &mpic 0x2 0x1
519 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]520 >;
521 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]522 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]523 #size-cells = <2>;
524 #address-cells = <3>;
525 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]526 ranges = <0x2000000 0x0 0xc0000000
527 0x2000000 0x0 0xc0000000
528 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]529
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]530 0x1000000 0x0 0x0
531 0x1000000 0x0 0x0
532 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]533 };
534 };
535};