Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 28 | #include <linux/async.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 30 | #include <linux/hdmi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/i915_drm.h> |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_crtc_helper.h> |
| 35 | #include <drm/drm_fb_helper.h> |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 36 | #include <drm/drm_dp_mst_helper.h> |
Gustavo Padovan | eeca778 | 2014-09-05 17:04:46 -0300 | [diff] [blame] | 37 | #include <drm/drm_rect.h> |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 38 | |
U. Artie Eoff | 2e54162 | 2014-09-29 15:49:33 -0700 | [diff] [blame] | 39 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
| 40 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
| 41 | |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 42 | /** |
| 43 | * _wait_for - magic (register) wait macro |
| 44 | * |
| 45 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| 46 | * contexts. Note that it's important that we check the condition again after |
| 47 | * having timed out, since the timeout could be due to preemption or similar and |
| 48 | * we've never had a chance to check the condition before the timeout. |
| 49 | */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 50 | #define _wait_for(COND, MS, W) ({ \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 51 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 52 | int ret__ = 0; \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 53 | while (!(COND)) { \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 54 | if (time_after(jiffies, timeout__)) { \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 55 | if (!(COND)) \ |
| 56 | ret__ = -ETIMEDOUT; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 57 | break; \ |
| 58 | } \ |
Ben Widawsky | 0cc2764 | 2012-09-01 22:59:48 -0700 | [diff] [blame] | 59 | if (W && drm_can_sleep()) { \ |
| 60 | msleep(W); \ |
| 61 | } else { \ |
| 62 | cpu_relax(); \ |
| 63 | } \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 64 | } \ |
| 65 | ret__; \ |
| 66 | }) |
| 67 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
Daniel Vetter | 6effa33 | 2013-03-28 11:31:04 +0100 | [diff] [blame] | 70 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
| 71 | DIV_ROUND_UP((US), 1000), 0) |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 72 | |
Jani Nikula | 49938ac | 2014-01-10 17:10:20 +0200 | [diff] [blame] | 73 | #define KHz(x) (1000 * (x)) |
| 74 | #define MHz(x) KHz(1000 * (x)) |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 75 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | /* |
| 77 | * Display related stuff |
| 78 | */ |
| 79 | |
| 80 | /* store information about an Ixxx DVO */ |
| 81 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 82 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 83 | #define MAX_OUTPUTS 6 |
| 84 | /* maximum connectors per crtcs in the mode set */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 85 | |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 86 | /* Maximum cursor sizes */ |
| 87 | #define GEN2_CURSOR_WIDTH 64 |
| 88 | #define GEN2_CURSOR_HEIGHT 64 |
Damien Lespiau | 068be56 | 2014-03-28 14:17:49 +0000 | [diff] [blame] | 89 | #define MAX_CURSOR_WIDTH 256 |
| 90 | #define MAX_CURSOR_HEIGHT 256 |
Sagar Kamble | 4726e0b | 2014-03-10 17:06:23 +0530 | [diff] [blame] | 91 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 92 | #define INTEL_I2C_BUS_DVO 1 |
| 93 | #define INTEL_I2C_BUS_SDVO 2 |
| 94 | |
| 95 | /* these are outputs from the chip - integrated only |
| 96 | external chips are via DVO or SDVO output */ |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 97 | enum intel_output_type { |
| 98 | INTEL_OUTPUT_UNUSED = 0, |
| 99 | INTEL_OUTPUT_ANALOG = 1, |
| 100 | INTEL_OUTPUT_DVO = 2, |
| 101 | INTEL_OUTPUT_SDVO = 3, |
| 102 | INTEL_OUTPUT_LVDS = 4, |
| 103 | INTEL_OUTPUT_TVOUT = 5, |
| 104 | INTEL_OUTPUT_HDMI = 6, |
| 105 | INTEL_OUTPUT_DISPLAYPORT = 7, |
| 106 | INTEL_OUTPUT_EDP = 8, |
| 107 | INTEL_OUTPUT_DSI = 9, |
| 108 | INTEL_OUTPUT_UNKNOWN = 10, |
| 109 | INTEL_OUTPUT_DP_MST = 11, |
| 110 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 111 | |
| 112 | #define INTEL_DVO_CHIP_NONE 0 |
| 113 | #define INTEL_DVO_CHIP_LVDS 1 |
| 114 | #define INTEL_DVO_CHIP_TMDS 2 |
| 115 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 116 | |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 117 | #define INTEL_DSI_VIDEO_MODE 0 |
| 118 | #define INTEL_DSI_COMMAND_MODE 1 |
Jani Nikula | 72ffa33 | 2013-08-27 15:12:17 +0300 | [diff] [blame] | 119 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 120 | struct intel_framebuffer { |
| 121 | struct drm_framebuffer base; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 122 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 123 | }; |
| 124 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 125 | struct intel_fbdev { |
| 126 | struct drm_fb_helper helper; |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 127 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 128 | struct list_head fbdev_list; |
| 129 | struct drm_display_mode *our_mode; |
Jesse Barnes | d978ef1 | 2014-03-07 08:57:51 -0800 | [diff] [blame] | 130 | int preferred_bpp; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 131 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 132 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 133 | struct intel_encoder { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 134 | struct drm_encoder base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 135 | /* |
| 136 | * The new crtc this encoder will be driven from. Only differs from |
| 137 | * base->crtc while a modeset is in progress. |
| 138 | */ |
| 139 | struct intel_crtc *new_crtc; |
| 140 | |
Paulo Zanoni | 6847d71b | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 141 | enum intel_output_type type; |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 142 | unsigned int cloneable; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 143 | bool connectors_active; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 144 | void (*hot_plug)(struct intel_encoder *); |
Daniel Vetter | 7ae8923 | 2013-03-27 00:44:52 +0100 | [diff] [blame] | 145 | bool (*compute_config)(struct intel_encoder *, |
| 146 | struct intel_crtc_config *); |
Daniel Vetter | dafd226 | 2012-11-26 17:22:07 +0100 | [diff] [blame] | 147 | void (*pre_pll_enable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8c | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 148 | void (*pre_enable)(struct intel_encoder *); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 149 | void (*enable)(struct intel_encoder *); |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 150 | void (*mode_set)(struct intel_encoder *intel_encoder); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 151 | void (*disable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8c | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 152 | void (*post_disable)(struct intel_encoder *); |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 153 | /* Read out the current hw state of this connector, returning true if |
| 154 | * the encoder is active. If the encoder is enabled it also set the pipe |
| 155 | * it is connected to in the pipe parameter. */ |
| 156 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 157 | /* Reconstructs the equivalent mode flags for the current hardware |
Daniel Vetter | fdafa9e | 2013-06-12 11:47:24 +0200 | [diff] [blame] | 158 | * state. This must be called _after_ display->get_pipe_config has |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 159 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
| 160 | * be set correctly before calling this function. */ |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 161 | void (*get_config)(struct intel_encoder *, |
| 162 | struct intel_crtc_config *pipe_config); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 163 | /* |
| 164 | * Called during system suspend after all pending requests for the |
| 165 | * encoder are flushed (for example for DP AUX transactions) and |
| 166 | * device interrupts are disabled. |
| 167 | */ |
| 168 | void (*suspend)(struct intel_encoder *); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 169 | int crtc_mask; |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 170 | enum hpd_pin hpd_pin; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 171 | }; |
| 172 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 173 | struct intel_panel { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 174 | struct drm_display_mode *fixed_mode; |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 175 | struct drm_display_mode *downclock_mode; |
Jani Nikula | 4d89152 | 2012-10-26 12:03:59 +0300 | [diff] [blame] | 176 | int fitting_mode; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 177 | |
| 178 | /* backlight */ |
| 179 | struct { |
Jani Nikula | c91c9f3 | 2013-11-08 16:48:55 +0200 | [diff] [blame] | 180 | bool present; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 181 | u32 level; |
Jani Nikula | 6dda730 | 2014-06-24 18:27:40 +0300 | [diff] [blame] | 182 | u32 min; |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 183 | u32 max; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 184 | bool enabled; |
Jani Nikula | 636baeb | 2013-11-08 16:49:02 +0200 | [diff] [blame] | 185 | bool combination_mode; /* gen 2/4 only */ |
| 186 | bool active_low_pwm; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 187 | struct backlight_device *device; |
| 188 | } backlight; |
Jani Nikula | ab656bb | 2014-08-13 12:10:12 +0300 | [diff] [blame] | 189 | |
| 190 | void (*backlight_power)(struct intel_connector *, bool enable); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 191 | }; |
| 192 | |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 193 | struct intel_connector { |
| 194 | struct drm_connector base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 195 | /* |
| 196 | * The fixed encoder this connector is connected to. |
| 197 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 198 | struct intel_encoder *encoder; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 199 | |
| 200 | /* |
| 201 | * The new encoder this connector will be driven. Only differs from |
| 202 | * encoder while a modeset is in progress. |
| 203 | */ |
| 204 | struct intel_encoder *new_encoder; |
| 205 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 206 | /* Reads out the current hw, returning true if the connector is enabled |
| 207 | * and active (i.e. dpms ON state). */ |
| 208 | bool (*get_hw_state)(struct intel_connector *); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 209 | |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 210 | /* |
| 211 | * Removes all interfaces through which the connector is accessible |
| 212 | * - like sysfs, debugfs entries -, so that no new operations can be |
| 213 | * started on the connector. Also makes sure all currently pending |
| 214 | * operations finish before returing. |
| 215 | */ |
| 216 | void (*unregister)(struct intel_connector *); |
| 217 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 218 | /* Panel info for eDP and LVDS */ |
| 219 | struct intel_panel panel; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 220 | |
| 221 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| 222 | struct edid *edid; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 223 | struct edid *detect_edid; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 224 | |
| 225 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| 226 | state of connector->polled in case hotplug storm detection changes it */ |
| 227 | u8 polled; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 228 | |
| 229 | void *port; /* store this opaque as its illegal to dereference it */ |
| 230 | |
| 231 | struct intel_dp *mst_port; |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 232 | }; |
| 233 | |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 234 | typedef struct dpll { |
| 235 | /* given values */ |
| 236 | int n; |
| 237 | int m1, m2; |
| 238 | int p1, p2; |
| 239 | /* derived values */ |
| 240 | int dot; |
| 241 | int vco; |
| 242 | int m; |
| 243 | int p; |
| 244 | } intel_clock_t; |
| 245 | |
Gustavo Padovan | eeca778 | 2014-09-05 17:04:46 -0300 | [diff] [blame] | 246 | struct intel_plane_state { |
| 247 | struct drm_crtc *crtc; |
| 248 | struct drm_framebuffer *fb; |
| 249 | struct drm_rect src; |
| 250 | struct drm_rect dst; |
| 251 | struct drm_rect clip; |
| 252 | struct drm_rect orig_src; |
| 253 | struct drm_rect orig_dst; |
| 254 | bool visible; |
| 255 | }; |
| 256 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 257 | struct intel_plane_config { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 258 | bool tiled; |
| 259 | int size; |
| 260 | u32 base; |
| 261 | }; |
| 262 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 263 | struct intel_crtc_config { |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 264 | /** |
| 265 | * quirks - bitfield with hw state readout quirks |
| 266 | * |
| 267 | * For various reasons the hw state readout code might not be able to |
| 268 | * completely faithfully read out the current state. These cases are |
| 269 | * tracked with quirk flags so that fastboot and state checker can act |
| 270 | * accordingly. |
| 271 | */ |
Daniel Vetter | 9953599 | 2014-04-13 12:00:33 +0200 | [diff] [blame] | 272 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| 273 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 274 | unsigned long quirks; |
| 275 | |
Ville Syrjälä | 5113bc9 | 2013-09-04 18:25:29 +0300 | [diff] [blame] | 276 | /* User requested mode, only valid as a starting point to |
| 277 | * compute adjusted_mode, except in the case of (S)DVO where |
| 278 | * it's also for the output timings of the (S)DVO chip. |
| 279 | * adjusted_mode will then correspond to the S(DVO) chip's |
| 280 | * preferred input timings. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 281 | struct drm_display_mode requested_mode; |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 282 | /* Actual pipe timings ie. what we program into the pipe timing |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 283 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 284 | struct drm_display_mode adjusted_mode; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 285 | |
| 286 | /* Pipe source size (ie. panel fitter input size) |
| 287 | * All planes will be positioned inside this space, |
| 288 | * and get clipped at the edges. */ |
| 289 | int pipe_src_w, pipe_src_h; |
| 290 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 291 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| 292 | * between pch encoders and cpu encoders. */ |
| 293 | bool has_pch_encoder; |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 294 | |
Jesse Barnes | e43823e | 2014-11-05 14:26:08 -0800 | [diff] [blame] | 295 | /* Are we sending infoframes on the attached port */ |
| 296 | bool has_infoframe; |
| 297 | |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 298 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| 299 | * pipe on Haswell (where we have a special eDP transcoder). */ |
| 300 | enum transcoder cpu_transcoder; |
| 301 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 302 | /* |
| 303 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| 304 | * range fed into the crtcs. |
| 305 | */ |
| 306 | bool limited_color_range; |
| 307 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 308 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| 309 | * accordingly. */ |
| 310 | bool has_dp_encoder; |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 311 | |
Daniel Vetter | 6897b4b | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 312 | /* Whether we should send NULL infoframes. Required for audio. */ |
| 313 | bool has_hdmi_sink; |
| 314 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 315 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
| 316 | * has_dp_encoder is set. */ |
| 317 | bool has_audio; |
| 318 | |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 319 | /* |
| 320 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| 321 | * plane bpp. |
| 322 | */ |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 323 | bool dither; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 324 | |
| 325 | /* Controls for the clock computation, to override various stages. */ |
| 326 | bool clock_set; |
| 327 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 328 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
| 329 | * work correctly, we need to track this at runtime.*/ |
| 330 | bool sdvo_tv_clock; |
| 331 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 332 | /* |
| 333 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| 334 | * required. This is set in the 2nd loop of calling encoder's |
| 335 | * ->compute_config if the first pick doesn't work out. |
| 336 | */ |
| 337 | bool bw_constrained; |
| 338 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 339 | /* Settings for the intel dpll used on pretty much everything but |
| 340 | * haswell. */ |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 341 | struct dpll dpll; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 342 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 343 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
| 344 | enum intel_dpll_id shared_dpll; |
| 345 | |
Satheeshakrishna M | 96b7dfb | 2014-11-13 14:55:17 +0000 | [diff] [blame] | 346 | /* |
| 347 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. |
| 348 | * - enum skl_dpll on SKL |
| 349 | */ |
Daniel Vetter | de7cfc6 | 2014-06-25 22:01:54 +0300 | [diff] [blame] | 350 | uint32_t ddi_pll_sel; |
| 351 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 352 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| 353 | struct intel_dpll_hw_state dpll_hw_state; |
| 354 | |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 355 | int pipe_bpp; |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 356 | struct intel_link_m_n dp_m_n; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 357 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 358 | /* m2_n2 for eDP downclock */ |
| 359 | struct intel_link_m_n dp_m2_n2; |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 360 | bool has_drrs; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 361 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 362 | /* |
| 363 | * Frequence the dpll for the port should run at. Differs from the |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 364 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 365 | * already multiplied by pixel_multiplier. |
Daniel Vetter | df92b1e | 2013-03-28 10:41:58 +0100 | [diff] [blame] | 366 | */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 367 | int port_clock; |
| 368 | |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 369 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| 370 | unsigned pixel_multiplier; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 371 | |
| 372 | /* Panel fitter controls for gen2-gen4 + VLV */ |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 373 | struct { |
| 374 | u32 control; |
| 375 | u32 pgm_ratios; |
Daniel Vetter | 68fc874 | 2013-04-25 22:52:16 +0200 | [diff] [blame] | 376 | u32 lvds_border_bits; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 377 | } gmch_pfit; |
| 378 | |
| 379 | /* Panel fitter placement and size for Ironlake+ */ |
| 380 | struct { |
| 381 | u32 pos; |
| 382 | u32 size; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 383 | bool enabled; |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 384 | bool force_thru; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 385 | } pch_pfit; |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 386 | |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 387 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 388 | int fdi_lanes; |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 389 | struct intel_link_m_n fdi_m_n; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 390 | |
| 391 | bool ips_enabled; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 392 | |
| 393 | bool double_wide; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 394 | |
| 395 | bool dp_encoder_is_mst; |
| 396 | int pbn; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 397 | }; |
| 398 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 399 | struct intel_pipe_wm { |
| 400 | struct intel_wm_level wm[5]; |
| 401 | uint32_t linetime; |
| 402 | bool fbc_wm_enabled; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 403 | bool pipe_enabled; |
| 404 | bool sprites_enabled; |
| 405 | bool sprites_scaled; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 406 | }; |
| 407 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 408 | struct intel_mmio_flip { |
| 409 | u32 seqno; |
Ander Conselvan de Oliveira | 536f5b5 | 2014-11-06 11:03:40 +0200 | [diff] [blame] | 410 | struct intel_engine_cs *ring; |
Ander Conselvan de Oliveira | 9362c7c | 2014-10-28 15:10:14 +0200 | [diff] [blame] | 411 | struct work_struct work; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 412 | }; |
| 413 | |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 414 | struct skl_pipe_wm { |
| 415 | struct skl_wm_level wm[8]; |
| 416 | struct skl_wm_level trans_wm; |
| 417 | uint32_t linetime; |
| 418 | }; |
| 419 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 420 | struct intel_crtc { |
| 421 | struct drm_crtc base; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 422 | enum pipe pipe; |
| 423 | enum plane plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 424 | u8 lut_r[256], lut_g[256], lut_b[256]; |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 425 | /* |
| 426 | * Whether the crtc and the connected output pipeline is active. Implies |
| 427 | * that crtc->enabled is set, i.e. the current mode configuration has |
| 428 | * some outputs connected to this crtc. |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 429 | */ |
| 430 | bool active; |
Imre Deak | 6efdf35 | 2013-10-16 17:25:52 +0300 | [diff] [blame] | 431 | unsigned long enabled_power_domains; |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 432 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 433 | bool lowfreq_avail; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 434 | struct intel_overlay *overlay; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 435 | struct intel_unpin_work *unpin_work; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 436 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 437 | atomic_t unpin_work_count; |
| 438 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 439 | /* Display surface base address adjustement for pageflips. Note that on |
| 440 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 441 | * handled in the hw itself (with the TILEOFF register). */ |
| 442 | unsigned long dspaddr_offset; |
| 443 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 444 | struct drm_i915_gem_object *cursor_bo; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 445 | uint32_t cursor_addr; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 446 | int16_t cursor_width, cursor_height; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 447 | uint32_t cursor_cntl; |
Ville Syrjälä | dc41c15 | 2014-08-13 11:57:05 +0300 | [diff] [blame] | 448 | uint32_t cursor_size; |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 449 | uint32_t cursor_base; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 450 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 451 | struct intel_plane_config plane_config; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 452 | struct intel_crtc_config config; |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 453 | struct intel_crtc_config *new_config; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 454 | bool new_enabled; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 455 | |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 456 | /* reset counter value when the last flip was submitted */ |
| 457 | unsigned int reset_counter; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 458 | |
| 459 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| 460 | bool cpu_fifo_underrun_disabled; |
| 461 | bool pch_fifo_underrun_disabled; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 462 | |
| 463 | /* per-pipe watermark state */ |
| 464 | struct { |
| 465 | /* watermarks currently being used */ |
| 466 | struct intel_pipe_wm active; |
Pradeep Bhat | 2ac96d2 | 2014-11-04 17:06:40 +0000 | [diff] [blame] | 467 | /* SKL wm values currently in use */ |
| 468 | struct skl_pipe_wm skl_active; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 469 | } wm; |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 470 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 471 | int scanline_offset; |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 472 | struct intel_mmio_flip mmio_flip; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 473 | }; |
| 474 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 475 | struct intel_plane_wm_parameters { |
| 476 | uint32_t horiz_pixels; |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 477 | uint32_t vert_pixels; |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 478 | uint8_t bytes_per_pixel; |
| 479 | bool enabled; |
| 480 | bool scaled; |
| 481 | }; |
| 482 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 483 | struct intel_plane { |
| 484 | struct drm_plane base; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 485 | int plane; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 486 | enum pipe pipe; |
| 487 | struct drm_i915_gem_object *obj; |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 488 | bool can_scale; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 489 | int max_downscale; |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 490 | int crtc_x, crtc_y; |
| 491 | unsigned int crtc_w, crtc_h; |
| 492 | uint32_t src_x, src_y; |
| 493 | uint32_t src_w, src_h; |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 494 | unsigned int rotation; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 495 | |
| 496 | /* Since we need to change the watermarks before/after |
| 497 | * enabling/disabling the planes, we need to store the parameters here |
| 498 | * as the other pieces of the struct may not reflect the values we want |
| 499 | * for the watermark calculations. Currently only Haswell uses this. |
| 500 | */ |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 501 | struct intel_plane_wm_parameters wm; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 502 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 503 | void (*update_plane)(struct drm_plane *plane, |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 504 | struct drm_crtc *crtc, |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 505 | struct drm_framebuffer *fb, |
| 506 | struct drm_i915_gem_object *obj, |
| 507 | int crtc_x, int crtc_y, |
| 508 | unsigned int crtc_w, unsigned int crtc_h, |
| 509 | uint32_t x, uint32_t y, |
| 510 | uint32_t src_w, uint32_t src_h); |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 511 | void (*disable_plane)(struct drm_plane *plane, |
| 512 | struct drm_crtc *crtc); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 513 | int (*update_colorkey)(struct drm_plane *plane, |
| 514 | struct drm_intel_sprite_colorkey *key); |
| 515 | void (*get_colorkey)(struct drm_plane *plane, |
| 516 | struct drm_intel_sprite_colorkey *key); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 517 | }; |
| 518 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 519 | struct intel_watermark_params { |
| 520 | unsigned long fifo_size; |
| 521 | unsigned long max_wm; |
| 522 | unsigned long default_wm; |
| 523 | unsigned long guard_size; |
| 524 | unsigned long cacheline_size; |
| 525 | }; |
| 526 | |
| 527 | struct cxsr_latency { |
| 528 | int is_desktop; |
| 529 | int is_ddr3; |
| 530 | unsigned long fsb_freq; |
| 531 | unsigned long mem_freq; |
| 532 | unsigned long display_sr; |
| 533 | unsigned long display_hpll_disable; |
| 534 | unsigned long cursor_sr; |
| 535 | unsigned long cursor_hpll_disable; |
| 536 | }; |
| 537 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 538 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 539 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 540 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 541 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 542 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
Matt Roper | 155e636 | 2014-07-07 18:21:47 -0700 | [diff] [blame] | 543 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 544 | |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 545 | struct intel_hdmi { |
Paulo Zanoni | b242b7f | 2013-02-18 19:00:26 -0300 | [diff] [blame] | 546 | u32 hdmi_reg; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 547 | int ddc_bus; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 548 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 549 | bool color_range_auto; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 550 | bool has_hdmi_sink; |
| 551 | bool has_audio; |
| 552 | enum hdmi_force_audio force_audio; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 553 | bool rgb_quant_range_selectable; |
Vandana Kannan | 94a11dd | 2014-06-11 11:06:01 +0530 | [diff] [blame] | 554 | enum hdmi_picture_aspect aspect_ratio; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 555 | void (*write_infoframe)(struct drm_encoder *encoder, |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 556 | enum hdmi_infoframe_type type, |
Ville Syrjälä | fff6386 | 2013-12-10 15:19:08 +0200 | [diff] [blame] | 557 | const void *frame, ssize_t len); |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 558 | void (*set_infoframes)(struct drm_encoder *encoder, |
Daniel Vetter | 6897b4b | 2014-04-24 23:54:47 +0200 | [diff] [blame] | 559 | bool enable, |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 560 | struct drm_display_mode *adjusted_mode); |
Jesse Barnes | e43823e | 2014-11-05 14:26:08 -0800 | [diff] [blame] | 561 | bool (*infoframe_enabled)(struct drm_encoder *encoder); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 562 | }; |
| 563 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 564 | struct intel_dp_mst_encoder; |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 565 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 566 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 567 | /** |
| 568 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
| 569 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
| 570 | * parsing for same resolution. |
| 571 | */ |
| 572 | enum edp_drrs_refresh_rate_type { |
| 573 | DRRS_HIGH_RR, |
| 574 | DRRS_LOW_RR, |
| 575 | DRRS_MAX_RR, /* RR count */ |
| 576 | }; |
| 577 | |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 578 | struct intel_dp { |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 579 | uint32_t output_reg; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 580 | uint32_t aux_ch_ctl_reg; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 581 | uint32_t DP; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 582 | bool has_audio; |
| 583 | enum hdmi_force_audio force_audio; |
| 584 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 585 | bool color_range_auto; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 586 | uint8_t link_bw; |
| 587 | uint8_t lane_count; |
| 588 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 589 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 590 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 591 | struct drm_dp_aux aux; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 592 | uint8_t train_set[4]; |
| 593 | int panel_power_up_delay; |
| 594 | int panel_power_down_delay; |
| 595 | int panel_power_cycle_delay; |
| 596 | int backlight_on_delay; |
| 597 | int backlight_off_delay; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 598 | struct delayed_work panel_vdd_work; |
| 599 | bool want_panel_vdd; |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 600 | unsigned long last_power_cycle; |
| 601 | unsigned long last_power_on; |
| 602 | unsigned long last_backlight_off; |
Dave Airlie | 5d42f82 | 2014-08-05 09:04:59 +1000 | [diff] [blame] | 603 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 604 | struct notifier_block edp_notifier; |
| 605 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 606 | /* |
| 607 | * Pipe whose power sequencer is currently locked into |
| 608 | * this port. Only relevant on VLV/CHV. |
| 609 | */ |
| 610 | enum pipe pps_pipe; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 611 | struct edp_power_seq pps_delays; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 612 | |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 613 | bool use_tps3; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 614 | bool can_mst; /* this port supports mst */ |
| 615 | bool is_mst; |
| 616 | int active_mst_links; |
| 617 | /* connector directly attached - won't be use for modeset in mst world */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 618 | struct intel_connector *attached_connector; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 619 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 620 | /* mst connector list */ |
| 621 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
| 622 | struct drm_dp_mst_topology_mgr mst_mgr; |
| 623 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 624 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 625 | /* |
| 626 | * This function returns the value we have to program the AUX_CTL |
| 627 | * register with to kick off an AUX transaction. |
| 628 | */ |
| 629 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
| 630 | bool has_aux_irq, |
| 631 | int send_bytes, |
| 632 | uint32_t aux_clock_divider); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 633 | struct { |
| 634 | enum drrs_support_type type; |
| 635 | enum edp_drrs_refresh_rate_type refresh_rate_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 636 | struct mutex mutex; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 637 | } drrs_state; |
| 638 | |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 639 | }; |
| 640 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 641 | struct intel_digital_port { |
| 642 | struct intel_encoder base; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 643 | enum port port; |
Stéphane Marchesin | bcf53de | 2013-07-12 13:54:41 -0700 | [diff] [blame] | 644 | u32 saved_port_bits; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 645 | struct intel_dp dp; |
| 646 | struct intel_hdmi hdmi; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 647 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 648 | }; |
| 649 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 650 | struct intel_dp_mst_encoder { |
| 651 | struct intel_encoder base; |
| 652 | enum pipe pipe; |
| 653 | struct intel_digital_port *primary; |
| 654 | void *port; /* store this opaque as its illegal to dereference it */ |
| 655 | }; |
| 656 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 657 | static inline int |
| 658 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| 659 | { |
| 660 | switch (dport->port) { |
| 661 | case PORT_B: |
Chon Ming Lee | 00fc31b | 2014-04-09 13:28:15 +0300 | [diff] [blame] | 662 | case PORT_D: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 663 | return DPIO_CH0; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 664 | case PORT_C: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 665 | return DPIO_CH1; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 666 | default: |
| 667 | BUG(); |
| 668 | } |
| 669 | } |
| 670 | |
Chon Ming Lee | eb69b0e | 2014-04-09 13:28:16 +0300 | [diff] [blame] | 671 | static inline int |
| 672 | vlv_pipe_to_channel(enum pipe pipe) |
| 673 | { |
| 674 | switch (pipe) { |
| 675 | case PIPE_A: |
| 676 | case PIPE_C: |
| 677 | return DPIO_CH0; |
| 678 | case PIPE_B: |
| 679 | return DPIO_CH1; |
| 680 | default: |
| 681 | BUG(); |
| 682 | } |
| 683 | } |
| 684 | |
Chris Wilson | f875c15 | 2010-09-09 15:44:14 +0100 | [diff] [blame] | 685 | static inline struct drm_crtc * |
| 686 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 687 | { |
| 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 689 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 690 | } |
| 691 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 692 | static inline struct drm_crtc * |
| 693 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 694 | { |
| 695 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 696 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 697 | } |
| 698 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 699 | struct intel_unpin_work { |
| 700 | struct work_struct work; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 701 | struct drm_crtc *crtc; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 702 | struct drm_i915_gem_object *old_fb_obj; |
| 703 | struct drm_i915_gem_object *pending_flip_obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 704 | struct drm_pending_vblank_event *event; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 705 | atomic_t pending; |
| 706 | #define INTEL_FLIP_INACTIVE 0 |
| 707 | #define INTEL_FLIP_PENDING 1 |
| 708 | #define INTEL_FLIP_COMPLETE 2 |
Ville Syrjälä | 75f7f3e | 2014-04-15 21:41:34 +0300 | [diff] [blame] | 709 | u32 flip_count; |
| 710 | u32 gtt_offset; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 711 | struct intel_engine_cs *flip_queued_ring; |
| 712 | u32 flip_queued_seqno; |
| 713 | int flip_queued_vblank; |
| 714 | int flip_ready_vblank; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 715 | bool enable_stall_check; |
| 716 | }; |
| 717 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 718 | struct intel_set_config { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 719 | struct drm_encoder **save_connector_encoders; |
| 720 | struct drm_crtc **save_encoder_crtcs; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 721 | bool *save_crtc_enabled; |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 722 | |
| 723 | bool fb_changed; |
| 724 | bool mode_changed; |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 725 | }; |
| 726 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 727 | struct intel_load_detect_pipe { |
| 728 | struct drm_framebuffer *release_fb; |
| 729 | bool load_detect_temp; |
| 730 | int dpms_mode; |
| 731 | }; |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 732 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 733 | static inline struct intel_encoder * |
| 734 | intel_attached_encoder(struct drm_connector *connector) |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 735 | { |
| 736 | return to_intel_connector(connector)->encoder; |
| 737 | } |
| 738 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 739 | static inline struct intel_digital_port * |
| 740 | enc_to_dig_port(struct drm_encoder *encoder) |
| 741 | { |
| 742 | return container_of(encoder, struct intel_digital_port, base.base); |
| 743 | } |
| 744 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 745 | static inline struct intel_dp_mst_encoder * |
| 746 | enc_to_mst(struct drm_encoder *encoder) |
| 747 | { |
| 748 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
| 749 | } |
| 750 | |
Imre Deak | 9ff8c9b | 2013-05-08 13:14:02 +0300 | [diff] [blame] | 751 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 752 | { |
| 753 | return &enc_to_dig_port(encoder)->dp; |
| 754 | } |
| 755 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 756 | static inline struct intel_digital_port * |
| 757 | dp_to_dig_port(struct intel_dp *intel_dp) |
| 758 | { |
| 759 | return container_of(intel_dp, struct intel_digital_port, dp); |
| 760 | } |
| 761 | |
| 762 | static inline struct intel_digital_port * |
| 763 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| 764 | { |
| 765 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 766 | } |
| 767 | |
Damien Lespiau | 6af31a6 | 2014-03-28 00:18:33 +0530 | [diff] [blame] | 768 | /* |
| 769 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
| 770 | * (primary plane). This doesn't count the cursor plane then. |
| 771 | */ |
| 772 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
| 773 | { |
| 774 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
| 775 | } |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 776 | |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 777 | /* intel_fifo_underrun.c */ |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 778 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 779 | enum pipe pipe, bool enable); |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 780 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 781 | enum transcoder pch_transcoder, |
| 782 | bool enable); |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 783 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 784 | enum pipe pipe); |
| 785 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 786 | enum transcoder pch_transcoder); |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 787 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 788 | |
| 789 | /* i915_irq.c */ |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 790 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 791 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 792 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 793 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 794 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 795 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
| 796 | void gen6_disable_rps_interrupts(struct drm_device *dev); |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 797 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
| 798 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 799 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
| 800 | { |
| 801 | /* |
| 802 | * We only use drm_irq_uninstall() at unload and VT switch, so |
| 803 | * this is the only thing we need to check. |
| 804 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 805 | return dev_priv->pm.irqs_enabled; |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 806 | } |
| 807 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 808 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 809 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 810 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 811 | /* intel_crt.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 812 | void intel_crt_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 813 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 814 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 815 | /* intel_ddi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 816 | void intel_prepare_ddi(struct drm_device *dev); |
| 817 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
| 818 | void intel_ddi_init(struct drm_device *dev, enum port port); |
| 819 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
| 820 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
| 821 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| 822 | void intel_ddi_pll_init(struct drm_device *dev); |
| 823 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| 824 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 825 | enum transcoder cpu_transcoder); |
| 826 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 827 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 828 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 829 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| 830 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| 831 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 832 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| 833 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 834 | struct intel_crtc_config *pipe_config); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 835 | |
Dave Airlie | 44905a27 | 2014-05-02 13:36:43 +1000 | [diff] [blame] | 836 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 837 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
| 838 | struct intel_crtc_config *pipe_config); |
| 839 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 840 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 841 | /* intel_frontbuffer.c */ |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 842 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| 843 | struct intel_engine_cs *ring); |
| 844 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| 845 | unsigned frontbuffer_bits); |
| 846 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| 847 | unsigned frontbuffer_bits); |
| 848 | void intel_frontbuffer_flush(struct drm_device *dev, |
| 849 | unsigned frontbuffer_bits); |
| 850 | /** |
Daniel Vetter | 5c323b2 | 2014-09-30 22:10:53 +0200 | [diff] [blame] | 851 | * intel_frontbuffer_flip - synchronous frontbuffer flip |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 852 | * @dev: DRM device |
| 853 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 854 | * |
| 855 | * This function gets called after scheduling a flip on @obj. This is for |
| 856 | * synchronous plane updates which will happen on the next vblank and which will |
| 857 | * not get delayed by pending gpu rendering. |
| 858 | * |
| 859 | * Can be called without any locks held. |
| 860 | */ |
| 861 | static inline |
| 862 | void intel_frontbuffer_flip(struct drm_device *dev, |
| 863 | unsigned frontbuffer_bits) |
| 864 | { |
| 865 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
| 866 | } |
| 867 | |
| 868 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 869 | |
| 870 | |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 871 | /* intel_audio.c */ |
| 872 | void intel_init_audio(struct drm_device *dev); |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 873 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
| 874 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 875 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 876 | /* intel_display.c */ |
| 877 | const char *intel_output_name(int output); |
| 878 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
| 879 | int intel_pch_rawclk(struct drm_device *dev); |
| 880 | void intel_mark_busy(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 881 | void intel_mark_idle(struct drm_device *dev); |
| 882 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 883 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 884 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| 885 | void intel_encoder_destroy(struct drm_encoder *encoder); |
| 886 | void intel_connector_dpms(struct drm_connector *, int mode); |
| 887 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
| 888 | void intel_modeset_check_state(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 889 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 890 | struct intel_digital_port *port); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 891 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 892 | struct intel_encoder *encoder); |
| 893 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| 894 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 895 | struct drm_crtc *crtc); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 896 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 897 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 898 | struct drm_file *file_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 899 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 900 | enum pipe pipe); |
Damien Lespiau | 4093561 | 2014-10-29 11:16:59 +0000 | [diff] [blame] | 901 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
Daniel Vetter | 4f905cf9 | 2014-09-15 14:12:21 +0200 | [diff] [blame] | 902 | static inline void |
| 903 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
| 904 | { |
| 905 | drm_wait_one_vblank(dev, pipe); |
| 906 | } |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 907 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 908 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 909 | struct intel_digital_port *dport); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 910 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 911 | struct drm_display_mode *mode, |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 912 | struct intel_load_detect_pipe *old, |
| 913 | struct drm_modeset_acquire_ctx *ctx); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 914 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 915 | struct intel_load_detect_pipe *old); |
Tvrtko Ursulin | 850c4cd | 2014-10-30 16:39:38 +0000 | [diff] [blame] | 916 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
| 917 | struct drm_framebuffer *fb, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 918 | struct intel_engine_cs *pipelined); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 919 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 920 | struct drm_framebuffer * |
| 921 | __intel_framebuffer_create(struct drm_device *dev, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 922 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 923 | struct drm_i915_gem_object *obj); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 924 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| 925 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| 926 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 927 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 928 | |
| 929 | /* shared dpll functions */ |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 930 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
| 931 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 932 | struct intel_shared_dpll *pll, |
| 933 | bool state); |
| 934 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 935 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 936 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
| 937 | void intel_put_shared_dpll(struct intel_crtc *crtc); |
| 938 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 939 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 940 | const struct dpll *dpll); |
| 941 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
| 942 | |
Daniel Vetter | 716c2e5 | 2014-06-25 22:02:02 +0300 | [diff] [blame] | 943 | /* modesetting asserts */ |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 944 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 945 | enum pipe pipe); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 946 | void assert_pll(struct drm_i915_private *dev_priv, |
| 947 | enum pipe pipe, bool state); |
| 948 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 949 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 950 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 951 | enum pipe pipe, bool state); |
| 952 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
| 953 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 954 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 955 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 956 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 957 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 958 | unsigned int tiling_mode, |
| 959 | unsigned int bpp, |
| 960 | unsigned int pitch); |
Ville Syrjälä | 7514747 | 2014-11-24 18:28:11 +0200 | [diff] [blame^] | 961 | void intel_prepare_reset(struct drm_device *dev); |
| 962 | void intel_finish_reset(struct drm_device *dev); |
Paulo Zanoni | a14cb6f | 2014-03-07 20:08:17 -0300 | [diff] [blame] | 963 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
| 964 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 965 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 966 | struct intel_crtc_config *pipe_config); |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 967 | void intel_dp_set_m_n(struct intel_crtc *crtc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 968 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 969 | void |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 970 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
| 971 | int dotclock); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 972 | bool intel_crtc_active(struct drm_crtc *crtc); |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 973 | void hsw_enable_ips(struct intel_crtc *crtc); |
| 974 | void hsw_disable_ips(struct intel_crtc *crtc); |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 975 | enum intel_display_power_domain |
| 976 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 977 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 978 | struct intel_crtc_config *pipe_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 979 | int intel_format_to_fourcc(int format); |
Ville Syrjälä | 46a55d3 | 2014-05-21 14:04:46 +0300 | [diff] [blame] | 980 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 981 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 982 | |
| 983 | /* intel_dp.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 984 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
| 985 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 986 | struct intel_connector *intel_connector); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 987 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 988 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| 989 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| 990 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 991 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 992 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 993 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 994 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
| 995 | struct intel_crtc_config *pipe_config); |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 996 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 997 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| 998 | bool long_hpd); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 999 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| 1000 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 1001 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1002 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
| 1003 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1004 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1005 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
| 1006 | void intel_dp_mst_suspend(struct drm_device *dev); |
| 1007 | void intel_dp_mst_resume(struct drm_device *dev); |
| 1008 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); |
| 1009 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1010 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 1011 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
| 1012 | void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes); |
| 1013 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1014 | /* intel_dp_mst.c */ |
| 1015 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
| 1016 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1017 | /* intel_dsi.c */ |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1018 | void intel_dsi_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1019 | |
| 1020 | |
| 1021 | /* intel_dvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1022 | void intel_dvo_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1023 | |
| 1024 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1025 | /* legacy fbdev emulation in intel_fbdev.c */ |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1026 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1027 | extern int intel_fbdev_init(struct drm_device *dev); |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 1028 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1029 | extern void intel_fbdev_fini(struct drm_device *dev); |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 1030 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1031 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
| 1032 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1033 | #else |
| 1034 | static inline int intel_fbdev_init(struct drm_device *dev) |
| 1035 | { |
| 1036 | return 0; |
| 1037 | } |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1038 | |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 1039 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1040 | { |
| 1041 | } |
| 1042 | |
| 1043 | static inline void intel_fbdev_fini(struct drm_device *dev) |
| 1044 | { |
| 1045 | } |
| 1046 | |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 1047 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1048 | { |
| 1049 | } |
| 1050 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1051 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1052 | { |
| 1053 | } |
| 1054 | #endif |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1055 | |
| 1056 | /* intel_hdmi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1057 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
| 1058 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 1059 | struct intel_connector *intel_connector); |
| 1060 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 1061 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1062 | struct intel_crtc_config *pipe_config); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1063 | |
| 1064 | |
| 1065 | /* intel_lvds.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1066 | void intel_lvds_init(struct drm_device *dev); |
| 1067 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1068 | |
| 1069 | |
| 1070 | /* intel_modes.c */ |
| 1071 | int intel_connector_update_modes(struct drm_connector *connector, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1072 | struct edid *edid); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1073 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1074 | void intel_attach_force_audio_property(struct drm_connector *connector); |
| 1075 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1076 | |
| 1077 | |
| 1078 | /* intel_overlay.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1079 | void intel_setup_overlay(struct drm_device *dev); |
| 1080 | void intel_cleanup_overlay(struct drm_device *dev); |
| 1081 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
| 1082 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
| 1083 | struct drm_file *file_priv); |
| 1084 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
| 1085 | struct drm_file *file_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1086 | |
| 1087 | |
| 1088 | /* intel_panel.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1089 | int intel_panel_init(struct intel_panel *panel, |
Vandana Kannan | 4b6ed68 | 2014-02-11 14:26:36 +0530 | [diff] [blame] | 1090 | struct drm_display_mode *fixed_mode, |
| 1091 | struct drm_display_mode *downclock_mode); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1092 | void intel_panel_fini(struct intel_panel *panel); |
| 1093 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| 1094 | struct drm_display_mode *adjusted_mode); |
| 1095 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| 1096 | struct intel_crtc_config *pipe_config, |
| 1097 | int fitting_mode); |
| 1098 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| 1099 | struct intel_crtc_config *pipe_config, |
| 1100 | int fitting_mode); |
Jani Nikula | 6dda730 | 2014-06-24 18:27:40 +0300 | [diff] [blame] | 1101 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
| 1102 | u32 level, u32 max); |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 1103 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1104 | void intel_panel_enable_backlight(struct intel_connector *connector); |
| 1105 | void intel_panel_disable_backlight(struct intel_connector *connector); |
Jani Nikula | db31af1 | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 1106 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 1107 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1108 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 1109 | extern struct drm_display_mode *intel_find_panel_downclock( |
| 1110 | struct drm_device *dev, |
| 1111 | struct drm_display_mode *fixed_mode, |
| 1112 | struct drm_connector *connector); |
Ville Syrjälä | 0962c3c | 2014-11-07 15:19:46 +0200 | [diff] [blame] | 1113 | void intel_backlight_register(struct drm_device *dev); |
| 1114 | void intel_backlight_unregister(struct drm_device *dev); |
| 1115 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1116 | |
Rodrigo Vivi | 0bc12bc | 2014-11-14 08:52:28 -0800 | [diff] [blame] | 1117 | /* intel_psr.c */ |
| 1118 | bool intel_psr_is_enabled(struct drm_device *dev); |
| 1119 | void intel_psr_enable(struct intel_dp *intel_dp); |
| 1120 | void intel_psr_disable(struct intel_dp *intel_dp); |
| 1121 | void intel_psr_invalidate(struct drm_device *dev, |
| 1122 | unsigned frontbuffer_bits); |
| 1123 | void intel_psr_flush(struct drm_device *dev, |
| 1124 | unsigned frontbuffer_bits); |
| 1125 | void intel_psr_init(struct drm_device *dev); |
| 1126 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1127 | /* intel_runtime_pm.c */ |
| 1128 | int intel_power_domains_init(struct drm_i915_private *); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1129 | void intel_power_domains_fini(struct drm_i915_private *); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1130 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1131 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1132 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1133 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1134 | enum intel_display_power_domain domain); |
| 1135 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1136 | enum intel_display_power_domain domain); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1137 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 1138 | enum intel_display_power_domain domain); |
| 1139 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 1140 | enum intel_display_power_domain domain); |
| 1141 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
| 1142 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
| 1143 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
| 1144 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
| 1145 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| 1146 | |
Daniel Vetter | d9bc89d9 | 2014-09-30 10:56:40 +0200 | [diff] [blame] | 1147 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
| 1148 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1149 | /* intel_pm.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1150 | void intel_init_clock_gating(struct drm_device *dev); |
| 1151 | void intel_suspend_hw(struct drm_device *dev); |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 1152 | int ilk_wm_max_level(const struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1153 | void intel_update_watermarks(struct drm_crtc *crtc); |
| 1154 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 1155 | struct drm_crtc *crtc, |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 1156 | uint32_t sprite_width, |
| 1157 | uint32_t sprite_height, |
| 1158 | int pixel_size, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1159 | bool enabled, bool scaled); |
| 1160 | void intel_init_pm(struct drm_device *dev); |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 1161 | void intel_pm_setup(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1162 | bool intel_fbc_enabled(struct drm_device *dev); |
| 1163 | void intel_update_fbc(struct drm_device *dev); |
| 1164 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 1165 | void intel_gpu_ips_teardown(void); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 1166 | void intel_init_gt_powersave(struct drm_device *dev); |
| 1167 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1168 | void intel_enable_gt_powersave(struct drm_device *dev); |
| 1169 | void intel_disable_gt_powersave(struct drm_device *dev); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 1170 | void intel_suspend_gt_powersave(struct drm_device *dev); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 1171 | void intel_reset_gt_powersave(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1172 | void ironlake_teardown_rc6(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1173 | void gen6_update_ring_freq(struct drm_device *dev); |
Daniel Vetter | 076e29f | 2013-10-08 19:39:29 +0200 | [diff] [blame] | 1174 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 1175 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 1176 | void ilk_wm_get_hw_state(struct drm_device *dev); |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 1177 | void skl_wm_get_hw_state(struct drm_device *dev); |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 1178 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
| 1179 | struct skl_ddb_allocation *ddb /* out */); |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 1180 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1181 | |
| 1182 | /* intel_sdvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1183 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1184 | |
| 1185 | |
| 1186 | /* intel_sprite.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1187 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1188 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1189 | enum plane plane); |
Sonika Jindal | 48404c1 | 2014-08-22 14:06:04 +0530 | [diff] [blame] | 1190 | int intel_plane_set_property(struct drm_plane *plane, |
| 1191 | struct drm_property *prop, |
| 1192 | uint64_t val); |
Ville Syrjälä | e57465f | 2014-08-05 11:26:53 +0530 | [diff] [blame] | 1193 | int intel_plane_restore(struct drm_plane *plane); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1194 | void intel_plane_disable(struct drm_plane *plane); |
| 1195 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 1196 | struct drm_file *file_priv); |
| 1197 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 1198 | struct drm_file *file_priv); |
Ander Conselvan de Oliveira | 9362c7c | 2014-10-28 15:10:14 +0200 | [diff] [blame] | 1199 | bool intel_pipe_update_start(struct intel_crtc *crtc, |
| 1200 | uint32_t *start_vbl_count); |
| 1201 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 1202 | |
| 1203 | /* intel_tv.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 1204 | void intel_tv_init(struct drm_device *dev); |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1205 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1206 | #endif /* __INTEL_DRV_H__ */ |