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Stefan Agnerefb45b32014-11-02 21:36:46 +01001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf610-pinfunc.h"
11#include <dt-bindings/clock/vf610-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
Stefan Agner2b36bda2014-11-04 14:07:08 +010013#include <dt-bindings/gpio/gpio.h>
Stefan Agnerefb45b32014-11-02 21:36:46 +010014
15/ {
16 aliases {
17 can0 = &can0;
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
Stefan Agner76713952015-01-16 18:06:15 +010025 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 gpio3 = &gpio3;
29 gpio4 = &gpio4;
Stefan Agnerefb45b32014-11-02 21:36:46 +010030 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 fxosc: fxosc {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24000000>;
38 };
39
40 sxosc: sxosc {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 };
45
Stefan Agner0d018d72014-12-02 18:11:59 +010046 reboot: syscon-reboot {
47 compatible = "syscon-reboot";
48 regmap = <&src>;
49 offset = <0x0>;
50 mask = <0x1000>;
51 };
52
Stefan Agnerefb45b32014-11-02 21:36:46 +010053 soc {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "simple-bus";
57 ranges;
58
59 aips0: aips-bus@40000000 {
60 compatible = "fsl,aips-bus", "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 edma0: dma-controller@40018000 {
66 #dma-cells = <2>;
67 compatible = "fsl,vf610-edma";
68 reg = <0x40018000 0x2000>,
69 <0x40024000 0x1000>,
70 <0x40025000 0x1000>;
71 dma-channels = <32>;
72 clock-names = "dmamux0", "dmamux1";
73 clocks = <&clks VF610_CLK_DMAMUX0>,
74 <&clks VF610_CLK_DMAMUX1>;
75 status = "disabled";
76 };
77
78 can0: flexcan@40020000 {
79 compatible = "fsl,vf610-flexcan";
80 reg = <0x40020000 0x4000>;
81 clocks = <&clks VF610_CLK_FLEXCAN0>,
82 <&clks VF610_CLK_FLEXCAN0>;
83 clock-names = "ipg", "per";
84 status = "disabled";
85 };
86
87 uart0: serial@40027000 {
88 compatible = "fsl,vf610-lpuart";
89 reg = <0x40027000 0x1000>;
90 clocks = <&clks VF610_CLK_UART0>;
91 clock-names = "ipg";
92 dmas = <&edma0 0 2>,
93 <&edma0 0 3>;
94 dma-names = "rx","tx";
95 status = "disabled";
96 };
97
98 uart1: serial@40028000 {
99 compatible = "fsl,vf610-lpuart";
100 reg = <0x40028000 0x1000>;
101 clocks = <&clks VF610_CLK_UART1>;
102 clock-names = "ipg";
103 dmas = <&edma0 0 4>,
104 <&edma0 0 5>;
105 dma-names = "rx","tx";
106 status = "disabled";
107 };
108
109 uart2: serial@40029000 {
110 compatible = "fsl,vf610-lpuart";
111 reg = <0x40029000 0x1000>;
112 clocks = <&clks VF610_CLK_UART2>;
113 clock-names = "ipg";
114 dmas = <&edma0 0 6>,
115 <&edma0 0 7>;
116 dma-names = "rx","tx";
117 status = "disabled";
118 };
119
120 uart3: serial@4002a000 {
121 compatible = "fsl,vf610-lpuart";
122 reg = <0x4002a000 0x1000>;
123 clocks = <&clks VF610_CLK_UART3>;
124 clock-names = "ipg";
125 dmas = <&edma0 0 8>,
126 <&edma0 0 9>;
127 dma-names = "rx","tx";
128 status = "disabled";
129 };
130
131 dspi0: dspi0@4002c000 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "fsl,vf610-dspi";
135 reg = <0x4002c000 0x1000>;
136 clocks = <&clks VF610_CLK_DSPI0>;
137 clock-names = "dspi";
138 spi-num-chipselects = <5>;
139 status = "disabled";
140 };
141
142 sai2: sai@40031000 {
143 compatible = "fsl,vf610-sai";
144 reg = <0x40031000 0x1000>;
145 clocks = <&clks VF610_CLK_SAI2>;
146 clock-names = "sai";
147 dma-names = "tx", "rx";
148 dmas = <&edma0 0 21>,
149 <&edma0 0 20>;
150 status = "disabled";
151 };
152
153 pit: pit@40037000 {
154 compatible = "fsl,vf610-pit";
155 reg = <0x40037000 0x1000>;
156 clocks = <&clks VF610_CLK_PIT>;
157 clock-names = "pit";
158 };
159
160 pwm0: pwm@40038000 {
161 compatible = "fsl,vf610-ftm-pwm";
162 #pwm-cells = <3>;
163 reg = <0x40038000 0x1000>;
164 clock-names = "ftm_sys", "ftm_ext",
165 "ftm_fix", "ftm_cnt_clk_en";
166 clocks = <&clks VF610_CLK_FTM0>,
167 <&clks VF610_CLK_FTM0_EXT_SEL>,
168 <&clks VF610_CLK_FTM0_FIX_SEL>,
169 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
170 status = "disabled";
171 };
172
173 pwm1: pwm@40039000 {
174 compatible = "fsl,vf610-ftm-pwm";
175 #pwm-cells = <3>;
176 reg = <0x40039000 0x1000>;
177 clock-names = "ftm_sys", "ftm_ext",
178 "ftm_fix", "ftm_cnt_clk_en";
179 clocks = <&clks VF610_CLK_FTM1>,
180 <&clks VF610_CLK_FTM1_EXT_SEL>,
181 <&clks VF610_CLK_FTM1_FIX_SEL>,
182 <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
183 status = "disabled";
184 };
185
186 adc0: adc@4003b000 {
187 compatible = "fsl,vf610-adc";
188 reg = <0x4003b000 0x1000>;
189 clocks = <&clks VF610_CLK_ADC0>;
190 clock-names = "adc";
191 status = "disabled";
192 };
193
Stefan Agnerc134e092014-11-28 00:35:36 +0100194 wdoga5: wdog@4003e000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
196 reg = <0x4003e000 0x1000>;
197 clocks = <&clks VF610_CLK_WDT>;
198 clock-names = "wdog";
199 status = "disabled";
200 };
201
202 qspi0: quadspi@40044000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,vf610-qspi";
206 reg = <0x40044000 0x1000>;
207 clocks = <&clks VF610_CLK_QSPI0_EN>,
208 <&clks VF610_CLK_QSPI0>;
209 clock-names = "qspi_en", "qspi";
210 status = "disabled";
211 };
212
213 iomuxc: iomuxc@40048000 {
214 compatible = "fsl,vf610-iomuxc";
215 reg = <0x40048000 0x1000>;
216 #gpio-range-cells = <3>;
217 };
218
Stefan Agner76713952015-01-16 18:06:15 +0100219 gpio0: gpio@40049000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100220 compatible = "fsl,vf610-gpio";
221 reg = <0x40049000 0x1000 0x400ff000 0x40>;
222 gpio-controller;
223 #gpio-cells = <2>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 gpio-ranges = <&iomuxc 0 0 32>;
227 };
228
Stefan Agner76713952015-01-16 18:06:15 +0100229 gpio1: gpio@4004a000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100230 compatible = "fsl,vf610-gpio";
231 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 gpio-ranges = <&iomuxc 0 32 32>;
237 };
238
Stefan Agner76713952015-01-16 18:06:15 +0100239 gpio2: gpio@4004b000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100240 compatible = "fsl,vf610-gpio";
241 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 gpio-ranges = <&iomuxc 0 64 32>;
247 };
248
Stefan Agner76713952015-01-16 18:06:15 +0100249 gpio3: gpio@4004c000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100250 compatible = "fsl,vf610-gpio";
251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 96 32>;
257 };
258
Stefan Agner76713952015-01-16 18:06:15 +0100259 gpio4: gpio@4004d000 {
Stefan Agnerefb45b32014-11-02 21:36:46 +0100260 compatible = "fsl,vf610-gpio";
261 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 128 7>;
267 };
268
269 anatop: anatop@40050000 {
270 compatible = "fsl,vf610-anatop", "syscon";
271 reg = <0x40050000 0x400>;
272 };
273
274 usbphy0: usbphy@40050800 {
275 compatible = "fsl,vf610-usbphy";
276 reg = <0x40050800 0x400>;
277 clocks = <&clks VF610_CLK_USBPHY0>;
278 fsl,anatop = <&anatop>;
279 status = "disabled";
280 };
281
282 usbphy1: usbphy@40050c00 {
283 compatible = "fsl,vf610-usbphy";
284 reg = <0x40050c00 0x400>;
285 clocks = <&clks VF610_CLK_USBPHY1>;
286 fsl,anatop = <&anatop>;
287 status = "disabled";
288 };
289
290 i2c0: i2c@40066000 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "fsl,vf610-i2c";
294 reg = <0x40066000 0x1000>;
295 clocks = <&clks VF610_CLK_I2C0>;
296 clock-names = "ipg";
297 dmas = <&edma0 0 50>,
298 <&edma0 0 51>;
299 dma-names = "rx","tx";
300 status = "disabled";
301 };
302
303 clks: ccm@4006b000 {
304 compatible = "fsl,vf610-ccm";
305 reg = <0x4006b000 0x1000>;
306 clocks = <&sxosc>, <&fxosc>;
307 clock-names = "sxosc", "fxosc";
308 #clock-cells = <1>;
309 };
310
311 usbdev0: usb@40034000 {
312 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
313 reg = <0x40034000 0x800>;
314 clocks = <&clks VF610_CLK_USBC0>;
315 fsl,usbphy = <&usbphy0>;
316 fsl,usbmisc = <&usbmisc0 0>;
317 dr_mode = "peripheral";
318 status = "disabled";
319 };
320
321 usbmisc0: usb@40034800 {
322 #index-cells = <1>;
323 compatible = "fsl,vf610-usbmisc";
324 reg = <0x40034800 0x200>;
325 clocks = <&clks VF610_CLK_USBC0>;
326 status = "disabled";
327 };
Stefan Agner0d018d72014-12-02 18:11:59 +0100328
329 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>;
332 };
Stefan Agnerefb45b32014-11-02 21:36:46 +0100333 };
334
335 aips1: aips-bus@40080000 {
336 compatible = "fsl,aips-bus", "simple-bus";
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges;
340
341 edma1: dma-controller@40098000 {
342 #dma-cells = <2>;
343 compatible = "fsl,vf610-edma";
344 reg = <0x40098000 0x2000>,
345 <0x400a1000 0x1000>,
346 <0x400a2000 0x1000>;
347 dma-channels = <32>;
348 clock-names = "dmamux0", "dmamux1";
349 clocks = <&clks VF610_CLK_DMAMUX2>,
350 <&clks VF610_CLK_DMAMUX3>;
351 status = "disabled";
352 };
353
Sanchayan Maity8455dd02015-01-07 12:39:30 +0530354 snvs0: snvs@400a7000 {
355 compatible = "fsl,sec-v4.0-mon", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0x400a7000 0x2000>;
359
360 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>;
363 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc";
365 };
366 };
367
Stefan Agnerefb45b32014-11-02 21:36:46 +0100368 uart4: serial@400a9000 {
369 compatible = "fsl,vf610-lpuart";
370 reg = <0x400a9000 0x1000>;
371 clocks = <&clks VF610_CLK_UART4>;
372 clock-names = "ipg";
373 status = "disabled";
374 };
375
376 uart5: serial@400aa000 {
377 compatible = "fsl,vf610-lpuart";
378 reg = <0x400aa000 0x1000>;
379 clocks = <&clks VF610_CLK_UART5>;
380 clock-names = "ipg";
381 status = "disabled";
382 };
383
384 adc1: adc@400bb000 {
385 compatible = "fsl,vf610-adc";
386 reg = <0x400bb000 0x1000>;
387 clocks = <&clks VF610_CLK_ADC1>;
388 clock-names = "adc";
389 status = "disabled";
390 };
391
392 esdhc1: esdhc@400b2000 {
393 compatible = "fsl,imx53-esdhc";
394 reg = <0x400b2000 0x1000>;
395 clocks = <&clks VF610_CLK_IPG_BUS>,
396 <&clks VF610_CLK_PLATFORM_BUS>,
397 <&clks VF610_CLK_ESDHC1>;
398 clock-names = "ipg", "ahb", "per";
399 status = "disabled";
400 };
401
402 usbh1: usb@400b4000 {
403 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
404 reg = <0x400b4000 0x800>;
405 clocks = <&clks VF610_CLK_USBC1>;
406 fsl,usbphy = <&usbphy1>;
407 fsl,usbmisc = <&usbmisc1 0>;
408 dr_mode = "host";
409 status = "disabled";
410 };
411
412 usbmisc1: usb@400b4800 {
413 #index-cells = <1>;
414 compatible = "fsl,vf610-usbmisc";
415 reg = <0x400b4800 0x200>;
416 clocks = <&clks VF610_CLK_USBC1>;
417 status = "disabled";
418 };
419
420 ftm: ftm@400b8000 {
421 compatible = "fsl,ftm-timer";
422 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
423 clock-names = "ftm-evt", "ftm-src",
424 "ftm-evt-counter-en", "ftm-src-counter-en";
425 clocks = <&clks VF610_CLK_FTM2>,
426 <&clks VF610_CLK_FTM3>,
427 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
428 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
429 status = "disabled";
430 };
431
432 fec0: ethernet@400d0000 {
433 compatible = "fsl,mvf600-fec";
434 reg = <0x400d0000 0x1000>;
435 clocks = <&clks VF610_CLK_ENET0>,
436 <&clks VF610_CLK_ENET0>,
437 <&clks VF610_CLK_ENET>;
438 clock-names = "ipg", "ahb", "ptp";
439 status = "disabled";
440 };
441
442 fec1: ethernet@400d1000 {
443 compatible = "fsl,mvf600-fec";
444 reg = <0x400d1000 0x1000>;
445 clocks = <&clks VF610_CLK_ENET1>,
446 <&clks VF610_CLK_ENET1>,
447 <&clks VF610_CLK_ENET>;
448 clock-names = "ipg", "ahb", "ptp";
449 status = "disabled";
450 };
451
452 can1: flexcan@400d4000 {
453 compatible = "fsl,vf610-flexcan";
454 reg = <0x400d4000 0x4000>;
455 clocks = <&clks VF610_CLK_FLEXCAN1>,
456 <&clks VF610_CLK_FLEXCAN1>;
457 clock-names = "ipg", "per";
458 status = "disabled";
459 };
460
461 };
462 };
463};