Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * SMI (Serial Memory Controller) device driver for Serial NOR Flash on |
| 3 | * SPEAr platform |
| 4 | * The serial nor interface is largely based on drivers/mtd/m25p80.c, |
| 5 | * however the SPI interface has been replaced by SMI. |
| 6 | * |
| 7 | * Copyright © 2010 STMicroelectronics. |
| 8 | * Ashish Priyadarshi |
| 9 | * Shiraz Hashim <shiraz.hashim@st.com> |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/ioport.h> |
| 24 | #include <linux/jiffies.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/param.h> |
| 28 | #include <linux/platform_device.h> |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 29 | #include <linux/pm.h> |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 30 | #include <linux/mtd/mtd.h> |
| 31 | #include <linux/mtd/partitions.h> |
| 32 | #include <linux/mtd/spear_smi.h> |
| 33 | #include <linux/mutex.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/slab.h> |
| 36 | #include <linux/wait.h> |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 37 | #include <linux/of.h> |
| 38 | #include <linux/of_address.h> |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 39 | |
| 40 | /* SMI clock rate */ |
| 41 | #define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */ |
| 42 | |
| 43 | /* MAX time out to safely come out of a erase or write busy conditions */ |
| 44 | #define SMI_PROBE_TIMEOUT (HZ / 10) |
| 45 | #define SMI_MAX_TIME_OUT (3 * HZ) |
| 46 | |
| 47 | /* timeout for command completion */ |
| 48 | #define SMI_CMD_TIMEOUT (HZ / 10) |
| 49 | |
| 50 | /* registers of smi */ |
| 51 | #define SMI_CR1 0x0 /* SMI control register 1 */ |
| 52 | #define SMI_CR2 0x4 /* SMI control register 2 */ |
| 53 | #define SMI_SR 0x8 /* SMI status register */ |
| 54 | #define SMI_TR 0xC /* SMI transmit register */ |
| 55 | #define SMI_RR 0x10 /* SMI receive register */ |
| 56 | |
| 57 | /* defines for control_reg 1 */ |
| 58 | #define BANK_EN (0xF << 0) /* enables all banks */ |
| 59 | #define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */ |
| 60 | #define SW_MODE (0x1 << 28) /* enables SW Mode */ |
| 61 | #define WB_MODE (0x1 << 29) /* Write Burst Mode */ |
| 62 | #define FAST_MODE (0x1 << 15) /* Fast Mode */ |
| 63 | #define HOLD1 (0x1 << 16) /* Clock Hold period selection */ |
| 64 | |
| 65 | /* defines for control_reg 2 */ |
| 66 | #define SEND (0x1 << 7) /* Send data */ |
| 67 | #define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */ |
| 68 | #define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */ |
| 69 | #define RD_STATUS_REG (0x1 << 10) /* reads status reg */ |
| 70 | #define WE (0x1 << 11) /* Write Enable */ |
| 71 | |
| 72 | #define TX_LEN_SHIFT 0 |
| 73 | #define RX_LEN_SHIFT 4 |
| 74 | #define BANK_SHIFT 12 |
| 75 | |
| 76 | /* defines for status register */ |
| 77 | #define SR_WIP 0x1 /* Write in progress */ |
| 78 | #define SR_WEL 0x2 /* Write enable latch */ |
| 79 | #define SR_BP0 0x4 /* Block protect 0 */ |
| 80 | #define SR_BP1 0x8 /* Block protect 1 */ |
| 81 | #define SR_BP2 0x10 /* Block protect 2 */ |
| 82 | #define SR_SRWD 0x80 /* SR write protect */ |
| 83 | #define TFF 0x100 /* Transfer Finished Flag */ |
| 84 | #define WCF 0x200 /* Transfer Finished Flag */ |
| 85 | #define ERF1 0x400 /* Forbidden Write Request */ |
| 86 | #define ERF2 0x800 /* Forbidden Access */ |
| 87 | |
| 88 | #define WM_SHIFT 12 |
| 89 | |
| 90 | /* flash opcodes */ |
| 91 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
| 92 | |
| 93 | /* Flash Device Ids maintenance section */ |
| 94 | |
| 95 | /* data structure to maintain flash ids from different vendors */ |
| 96 | struct flash_device { |
| 97 | char *name; |
| 98 | u8 erase_cmd; |
| 99 | u32 device_id; |
| 100 | u32 pagesize; |
| 101 | unsigned long sectorsize; |
| 102 | unsigned long size_in_bytes; |
| 103 | }; |
| 104 | |
| 105 | #define FLASH_ID(n, es, id, psize, ssize, size) \ |
| 106 | { \ |
| 107 | .name = n, \ |
| 108 | .erase_cmd = es, \ |
| 109 | .device_id = id, \ |
| 110 | .pagesize = psize, \ |
| 111 | .sectorsize = ssize, \ |
| 112 | .size_in_bytes = size \ |
| 113 | } |
| 114 | |
| 115 | static struct flash_device flash_devices[] = { |
| 116 | FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), |
| 117 | FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), |
| 118 | FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), |
| 119 | FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), |
| 120 | FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), |
| 121 | FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), |
| 122 | FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), |
| 123 | FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), |
| 124 | FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), |
| 125 | FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), |
| 126 | FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), |
| 127 | FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), |
| 128 | FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), |
| 129 | FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), |
| 130 | FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), |
| 131 | FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), |
| 132 | FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), |
| 133 | FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), |
| 134 | FLASH_ID("atmel 25f512" , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000), |
| 135 | FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000), |
| 136 | FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000), |
| 137 | FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000), |
| 138 | FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000), |
| 139 | FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), |
| 140 | FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), |
| 141 | FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), |
| 142 | FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), |
| 143 | FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), |
| 144 | FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), |
| 145 | FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), |
| 146 | FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), |
| 147 | FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), |
| 148 | FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), |
| 149 | FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), |
| 150 | }; |
| 151 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 152 | /* Define spear specific structures */ |
| 153 | |
| 154 | struct spear_snor_flash; |
| 155 | |
| 156 | /** |
| 157 | * struct spear_smi - Structure for SMI Device |
| 158 | * |
| 159 | * @clk: functional clock |
| 160 | * @status: current status register of SMI. |
| 161 | * @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ) |
| 162 | * @lock: lock to prevent parallel access of SMI. |
| 163 | * @io_base: base address for registers of SMI. |
| 164 | * @pdev: platform device |
| 165 | * @cmd_complete: queue to wait for command completion of NOR-flash. |
| 166 | * @num_flashes: number of flashes actually present on board. |
| 167 | * @flash: separate structure for each Serial NOR-flash attached to SMI. |
| 168 | */ |
| 169 | struct spear_smi { |
| 170 | struct clk *clk; |
| 171 | u32 status; |
| 172 | unsigned long clk_rate; |
| 173 | struct mutex lock; |
| 174 | void __iomem *io_base; |
| 175 | struct platform_device *pdev; |
| 176 | wait_queue_head_t cmd_complete; |
| 177 | u32 num_flashes; |
| 178 | struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP]; |
| 179 | }; |
| 180 | |
| 181 | /** |
| 182 | * struct spear_snor_flash - Structure for Serial NOR Flash |
| 183 | * |
| 184 | * @bank: Bank number(0, 1, 2, 3) for each NOR-flash. |
| 185 | * @dev_id: Device ID of NOR-flash. |
| 186 | * @lock: lock to manage flash read, write and erase operations |
| 187 | * @mtd: MTD info for each NOR-flash. |
| 188 | * @num_parts: Total number of partition in each bank of NOR-flash. |
| 189 | * @parts: Partition info for each bank of NOR-flash. |
| 190 | * @page_size: Page size of NOR-flash. |
| 191 | * @base_addr: Base address of NOR-flash. |
| 192 | * @erase_cmd: erase command may vary on different flash types |
| 193 | * @fast_mode: flash supports read in fast mode |
| 194 | */ |
| 195 | struct spear_snor_flash { |
| 196 | u32 bank; |
| 197 | u32 dev_id; |
| 198 | struct mutex lock; |
| 199 | struct mtd_info mtd; |
| 200 | u32 num_parts; |
| 201 | struct mtd_partition *parts; |
| 202 | u32 page_size; |
| 203 | void __iomem *base_addr; |
| 204 | u8 erase_cmd; |
| 205 | u8 fast_mode; |
| 206 | }; |
| 207 | |
| 208 | static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd) |
| 209 | { |
| 210 | return container_of(mtd, struct spear_snor_flash, mtd); |
| 211 | } |
| 212 | |
| 213 | /** |
| 214 | * spear_smi_read_sr - Read status register of flash through SMI |
| 215 | * @dev: structure of SMI information. |
| 216 | * @bank: bank to which flash is connected |
| 217 | * |
| 218 | * This routine will return the status register of the flash chip present at the |
| 219 | * given bank. |
| 220 | */ |
| 221 | static int spear_smi_read_sr(struct spear_smi *dev, u32 bank) |
| 222 | { |
| 223 | int ret; |
| 224 | u32 ctrlreg1; |
| 225 | |
| 226 | mutex_lock(&dev->lock); |
| 227 | dev->status = 0; /* Will be set in interrupt handler */ |
| 228 | |
| 229 | ctrlreg1 = readl(dev->io_base + SMI_CR1); |
| 230 | /* program smi in hw mode */ |
| 231 | writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); |
| 232 | |
| 233 | /* performing a rsr instruction in hw mode */ |
| 234 | writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE, |
| 235 | dev->io_base + SMI_CR2); |
| 236 | |
| 237 | /* wait for tff */ |
| 238 | ret = wait_event_interruptible_timeout(dev->cmd_complete, |
| 239 | dev->status & TFF, SMI_CMD_TIMEOUT); |
| 240 | |
| 241 | /* copy dev->status (lower 16 bits) in order to release lock */ |
| 242 | if (ret > 0) |
| 243 | ret = dev->status & 0xffff; |
| 244 | else |
| 245 | ret = -EIO; |
| 246 | |
| 247 | /* restore the ctrl regs state */ |
| 248 | writel(ctrlreg1, dev->io_base + SMI_CR1); |
| 249 | writel(0, dev->io_base + SMI_CR2); |
| 250 | mutex_unlock(&dev->lock); |
| 251 | |
| 252 | return ret; |
| 253 | } |
| 254 | |
| 255 | /** |
| 256 | * spear_smi_wait_till_ready - wait till flash is ready |
| 257 | * @dev: structure of SMI information. |
| 258 | * @bank: flash corresponding to this bank |
| 259 | * @timeout: timeout for busy wait condition |
| 260 | * |
| 261 | * This routine checks for WIP (write in progress) bit in Status register |
| 262 | * If successful the routine returns 0 else -EBUSY |
| 263 | */ |
| 264 | static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank, |
| 265 | unsigned long timeout) |
| 266 | { |
| 267 | unsigned long finish; |
| 268 | int status; |
| 269 | |
| 270 | finish = jiffies + timeout; |
| 271 | do { |
| 272 | status = spear_smi_read_sr(dev, bank); |
| 273 | if (status < 0) |
| 274 | continue; /* try till timeout */ |
| 275 | else if (!(status & SR_WIP)) |
| 276 | return 0; |
| 277 | |
| 278 | cond_resched(); |
| 279 | } while (!time_after_eq(jiffies, finish)); |
| 280 | |
| 281 | dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n"); |
| 282 | return status; |
| 283 | } |
| 284 | |
| 285 | /** |
| 286 | * spear_smi_int_handler - SMI Interrupt Handler. |
| 287 | * @irq: irq number |
| 288 | * @dev_id: structure of SMI device, embedded in dev_id. |
| 289 | * |
| 290 | * The handler clears all interrupt conditions and records the status in |
| 291 | * dev->status which is used by the driver later. |
| 292 | */ |
| 293 | static irqreturn_t spear_smi_int_handler(int irq, void *dev_id) |
| 294 | { |
| 295 | u32 status = 0; |
| 296 | struct spear_smi *dev = dev_id; |
| 297 | |
| 298 | status = readl(dev->io_base + SMI_SR); |
| 299 | |
| 300 | if (unlikely(!status)) |
| 301 | return IRQ_NONE; |
| 302 | |
| 303 | /* clear all interrupt conditions */ |
| 304 | writel(0, dev->io_base + SMI_SR); |
| 305 | |
| 306 | /* copy the status register in dev->status */ |
| 307 | dev->status |= status; |
| 308 | |
| 309 | /* send the completion */ |
| 310 | wake_up_interruptible(&dev->cmd_complete); |
| 311 | |
| 312 | return IRQ_HANDLED; |
| 313 | } |
| 314 | |
| 315 | /** |
| 316 | * spear_smi_hw_init - initializes the smi controller. |
| 317 | * @dev: structure of smi device |
| 318 | * |
| 319 | * this routine initializes the smi controller wit the default values |
| 320 | */ |
| 321 | static void spear_smi_hw_init(struct spear_smi *dev) |
| 322 | { |
| 323 | unsigned long rate = 0; |
| 324 | u32 prescale = 0; |
| 325 | u32 val; |
| 326 | |
| 327 | rate = clk_get_rate(dev->clk); |
| 328 | |
| 329 | /* functional clock of smi */ |
| 330 | prescale = DIV_ROUND_UP(rate, dev->clk_rate); |
| 331 | |
| 332 | /* |
| 333 | * setting the standard values, fast mode, prescaler for |
| 334 | * SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable |
| 335 | */ |
| 336 | val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8); |
| 337 | |
| 338 | mutex_lock(&dev->lock); |
| 339 | writel(val, dev->io_base + SMI_CR1); |
| 340 | mutex_unlock(&dev->lock); |
| 341 | } |
| 342 | |
| 343 | /** |
| 344 | * get_flash_index - match chip id from a flash list. |
| 345 | * @flash_id: a valid nor flash chip id obtained from board. |
| 346 | * |
| 347 | * try to validate the chip id by matching from a list, if not found then simply |
| 348 | * returns negative. In case of success returns index in to the flash devices |
| 349 | * array. |
| 350 | */ |
| 351 | static int get_flash_index(u32 flash_id) |
| 352 | { |
| 353 | int index; |
| 354 | |
| 355 | /* Matches chip-id to entire list of 'serial-nor flash' ids */ |
| 356 | for (index = 0; index < ARRAY_SIZE(flash_devices); index++) { |
| 357 | if (flash_devices[index].device_id == flash_id) |
| 358 | return index; |
| 359 | } |
| 360 | |
| 361 | /* Memory chip is not listed and not supported */ |
| 362 | return -ENODEV; |
| 363 | } |
| 364 | |
| 365 | /** |
| 366 | * spear_smi_write_enable - Enable the flash to do write operation |
| 367 | * @dev: structure of SMI device |
| 368 | * @bank: enable write for flash connected to this bank |
| 369 | * |
| 370 | * Set write enable latch with Write Enable command. |
| 371 | * Returns 0 on success. |
| 372 | */ |
| 373 | static int spear_smi_write_enable(struct spear_smi *dev, u32 bank) |
| 374 | { |
| 375 | int ret; |
| 376 | u32 ctrlreg1; |
| 377 | |
| 378 | mutex_lock(&dev->lock); |
| 379 | dev->status = 0; /* Will be set in interrupt handler */ |
| 380 | |
| 381 | ctrlreg1 = readl(dev->io_base + SMI_CR1); |
| 382 | /* program smi in h/w mode */ |
| 383 | writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1); |
| 384 | |
| 385 | /* give the flash, write enable command */ |
| 386 | writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2); |
| 387 | |
| 388 | ret = wait_event_interruptible_timeout(dev->cmd_complete, |
| 389 | dev->status & TFF, SMI_CMD_TIMEOUT); |
| 390 | |
| 391 | /* restore the ctrl regs state */ |
| 392 | writel(ctrlreg1, dev->io_base + SMI_CR1); |
| 393 | writel(0, dev->io_base + SMI_CR2); |
| 394 | |
| 395 | if (ret <= 0) { |
| 396 | ret = -EIO; |
| 397 | dev_err(&dev->pdev->dev, |
| 398 | "smi controller failed on write enable\n"); |
| 399 | } else { |
| 400 | /* check whether write mode status is set for required bank */ |
| 401 | if (dev->status & (1 << (bank + WM_SHIFT))) |
| 402 | ret = 0; |
| 403 | else { |
| 404 | dev_err(&dev->pdev->dev, "couldn't enable write\n"); |
| 405 | ret = -EIO; |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | mutex_unlock(&dev->lock); |
| 410 | return ret; |
| 411 | } |
| 412 | |
| 413 | static inline u32 |
| 414 | get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset) |
| 415 | { |
| 416 | u32 cmd; |
| 417 | u8 *x = (u8 *)&cmd; |
| 418 | |
| 419 | x[0] = flash->erase_cmd; |
| 420 | x[1] = offset >> 16; |
| 421 | x[2] = offset >> 8; |
| 422 | x[3] = offset; |
| 423 | |
| 424 | return cmd; |
| 425 | } |
| 426 | |
| 427 | /** |
| 428 | * spear_smi_erase_sector - erase one sector of flash |
| 429 | * @dev: structure of SMI information |
| 430 | * @command: erase command to be send |
| 431 | * @bank: bank to which this command needs to be send |
| 432 | * @bytes: size of command |
| 433 | * |
| 434 | * Erase one sector of flash memory at offset ``offset'' which is any |
| 435 | * address within the sector which should be erased. |
| 436 | * Returns 0 if successful, non-zero otherwise. |
| 437 | */ |
| 438 | static int spear_smi_erase_sector(struct spear_smi *dev, |
| 439 | u32 bank, u32 command, u32 bytes) |
| 440 | { |
| 441 | u32 ctrlreg1 = 0; |
| 442 | int ret; |
| 443 | |
| 444 | ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); |
| 445 | if (ret) |
| 446 | return ret; |
| 447 | |
| 448 | ret = spear_smi_write_enable(dev, bank); |
| 449 | if (ret) |
| 450 | return ret; |
| 451 | |
| 452 | mutex_lock(&dev->lock); |
| 453 | |
| 454 | ctrlreg1 = readl(dev->io_base + SMI_CR1); |
| 455 | writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1); |
| 456 | |
| 457 | /* send command in sw mode */ |
| 458 | writel(command, dev->io_base + SMI_TR); |
| 459 | |
| 460 | writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT), |
| 461 | dev->io_base + SMI_CR2); |
| 462 | |
| 463 | ret = wait_event_interruptible_timeout(dev->cmd_complete, |
| 464 | dev->status & TFF, SMI_CMD_TIMEOUT); |
| 465 | |
| 466 | if (ret <= 0) { |
| 467 | ret = -EIO; |
| 468 | dev_err(&dev->pdev->dev, "sector erase failed\n"); |
| 469 | } else |
| 470 | ret = 0; /* success */ |
| 471 | |
| 472 | /* restore ctrl regs */ |
| 473 | writel(ctrlreg1, dev->io_base + SMI_CR1); |
| 474 | writel(0, dev->io_base + SMI_CR2); |
| 475 | |
| 476 | mutex_unlock(&dev->lock); |
| 477 | return ret; |
| 478 | } |
| 479 | |
| 480 | /** |
| 481 | * spear_mtd_erase - perform flash erase operation as requested by user |
| 482 | * @mtd: Provides the memory characteristics |
| 483 | * @e_info: Provides the erase information |
| 484 | * |
| 485 | * Erase an address range on the flash chip. The address range may extend |
| 486 | * one or more erase sectors. Return an error is there is a problem erasing. |
| 487 | */ |
| 488 | static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info) |
| 489 | { |
| 490 | struct spear_snor_flash *flash = get_flash_data(mtd); |
| 491 | struct spear_smi *dev = mtd->priv; |
| 492 | u32 addr, command, bank; |
| 493 | int len, ret; |
| 494 | |
| 495 | if (!flash || !dev) |
| 496 | return -ENODEV; |
| 497 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 498 | bank = flash->bank; |
| 499 | if (bank > dev->num_flashes - 1) { |
| 500 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); |
| 501 | return -EINVAL; |
| 502 | } |
| 503 | |
| 504 | addr = e_info->addr; |
| 505 | len = e_info->len; |
| 506 | |
| 507 | mutex_lock(&flash->lock); |
| 508 | |
| 509 | /* now erase sectors in loop */ |
| 510 | while (len) { |
| 511 | command = get_sector_erase_cmd(flash, addr); |
| 512 | /* preparing the command for flash */ |
| 513 | ret = spear_smi_erase_sector(dev, bank, command, 4); |
| 514 | if (ret) { |
| 515 | e_info->state = MTD_ERASE_FAILED; |
| 516 | mutex_unlock(&flash->lock); |
| 517 | return ret; |
| 518 | } |
| 519 | addr += mtd->erasesize; |
| 520 | len -= mtd->erasesize; |
| 521 | } |
| 522 | |
| 523 | mutex_unlock(&flash->lock); |
| 524 | e_info->state = MTD_ERASE_DONE; |
| 525 | mtd_erase_callback(e_info); |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | /** |
| 531 | * spear_mtd_read - performs flash read operation as requested by the user |
| 532 | * @mtd: MTD information of the memory bank |
| 533 | * @from: Address from which to start read |
| 534 | * @len: Number of bytes to be read |
| 535 | * @retlen: Fills the Number of bytes actually read |
| 536 | * @buf: Fills this after reading |
| 537 | * |
| 538 | * Read an address range from the flash chip. The address range |
| 539 | * may be any size provided it is within the physical boundaries. |
| 540 | * Returns 0 on success, non zero otherwise |
| 541 | */ |
| 542 | static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, |
| 543 | size_t *retlen, u8 *buf) |
| 544 | { |
| 545 | struct spear_snor_flash *flash = get_flash_data(mtd); |
| 546 | struct spear_smi *dev = mtd->priv; |
| 547 | void *src; |
| 548 | u32 ctrlreg1, val; |
| 549 | int ret; |
| 550 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 551 | if (!flash || !dev) |
| 552 | return -ENODEV; |
| 553 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 554 | if (flash->bank > dev->num_flashes - 1) { |
| 555 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); |
| 556 | return -EINVAL; |
| 557 | } |
| 558 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 559 | /* select address as per bank number */ |
| 560 | src = flash->base_addr + from; |
| 561 | |
| 562 | mutex_lock(&flash->lock); |
| 563 | |
| 564 | /* wait till previous write/erase is done. */ |
| 565 | ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT); |
| 566 | if (ret) { |
| 567 | mutex_unlock(&flash->lock); |
| 568 | return ret; |
| 569 | } |
| 570 | |
| 571 | mutex_lock(&dev->lock); |
| 572 | /* put smi in hw mode not wbt mode */ |
| 573 | ctrlreg1 = val = readl(dev->io_base + SMI_CR1); |
| 574 | val &= ~(SW_MODE | WB_MODE); |
| 575 | if (flash->fast_mode) |
| 576 | val |= FAST_MODE; |
| 577 | |
| 578 | writel(val, dev->io_base + SMI_CR1); |
| 579 | |
| 580 | memcpy_fromio(buf, (u8 *)src, len); |
| 581 | |
| 582 | /* restore ctrl reg1 */ |
| 583 | writel(ctrlreg1, dev->io_base + SMI_CR1); |
| 584 | mutex_unlock(&dev->lock); |
| 585 | |
| 586 | *retlen = len; |
| 587 | mutex_unlock(&flash->lock); |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank, |
| 593 | void *dest, const void *src, size_t len) |
| 594 | { |
| 595 | int ret; |
| 596 | u32 ctrlreg1; |
| 597 | |
| 598 | /* wait until finished previous write command. */ |
| 599 | ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); |
| 600 | if (ret) |
| 601 | return ret; |
| 602 | |
| 603 | /* put smi in write enable */ |
| 604 | ret = spear_smi_write_enable(dev, bank); |
| 605 | if (ret) |
| 606 | return ret; |
| 607 | |
| 608 | /* put smi in hw, write burst mode */ |
| 609 | mutex_lock(&dev->lock); |
| 610 | |
| 611 | ctrlreg1 = readl(dev->io_base + SMI_CR1); |
| 612 | writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1); |
| 613 | |
| 614 | memcpy_toio(dest, src, len); |
| 615 | |
| 616 | writel(ctrlreg1, dev->io_base + SMI_CR1); |
| 617 | |
| 618 | mutex_unlock(&dev->lock); |
| 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | /** |
| 623 | * spear_mtd_write - performs write operation as requested by the user. |
| 624 | * @mtd: MTD information of the memory bank. |
| 625 | * @to: Address to write. |
| 626 | * @len: Number of bytes to be written. |
| 627 | * @retlen: Number of bytes actually wrote. |
| 628 | * @buf: Buffer from which the data to be taken. |
| 629 | * |
| 630 | * Write an address range to the flash chip. Data must be written in |
| 631 | * flash_page_size chunks. The address range may be any size provided |
| 632 | * it is within the physical boundaries. |
| 633 | * Returns 0 on success, non zero otherwise |
| 634 | */ |
| 635 | static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, |
| 636 | size_t *retlen, const u8 *buf) |
| 637 | { |
| 638 | struct spear_snor_flash *flash = get_flash_data(mtd); |
| 639 | struct spear_smi *dev = mtd->priv; |
| 640 | void *dest; |
| 641 | u32 page_offset, page_size; |
| 642 | int ret; |
| 643 | |
| 644 | if (!flash || !dev) |
| 645 | return -ENODEV; |
| 646 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 647 | if (flash->bank > dev->num_flashes - 1) { |
| 648 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); |
| 649 | return -EINVAL; |
| 650 | } |
| 651 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 652 | /* select address as per bank number */ |
| 653 | dest = flash->base_addr + to; |
| 654 | mutex_lock(&flash->lock); |
| 655 | |
| 656 | page_offset = (u32)to % flash->page_size; |
| 657 | |
| 658 | /* do if all the bytes fit onto one page */ |
| 659 | if (page_offset + len <= flash->page_size) { |
| 660 | ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len); |
| 661 | if (!ret) |
| 662 | *retlen += len; |
| 663 | } else { |
| 664 | u32 i; |
| 665 | |
| 666 | /* the size of data remaining on the first page */ |
| 667 | page_size = flash->page_size - page_offset; |
| 668 | |
| 669 | ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, |
| 670 | page_size); |
| 671 | if (ret) |
| 672 | goto err_write; |
| 673 | else |
| 674 | *retlen += page_size; |
| 675 | |
| 676 | /* write everything in pagesize chunks */ |
| 677 | for (i = page_size; i < len; i += page_size) { |
| 678 | page_size = len - i; |
| 679 | if (page_size > flash->page_size) |
| 680 | page_size = flash->page_size; |
| 681 | |
| 682 | ret = spear_smi_cpy_toio(dev, flash->bank, dest + i, |
| 683 | buf + i, page_size); |
| 684 | if (ret) |
| 685 | break; |
| 686 | else |
| 687 | *retlen += page_size; |
| 688 | } |
| 689 | } |
| 690 | |
| 691 | err_write: |
| 692 | mutex_unlock(&flash->lock); |
| 693 | |
| 694 | return ret; |
| 695 | } |
| 696 | |
| 697 | /** |
| 698 | * spear_smi_probe_flash - Detects the NOR Flash chip. |
| 699 | * @dev: structure of SMI information. |
| 700 | * @bank: bank on which flash must be probed |
| 701 | * |
| 702 | * This routine will check whether there exists a flash chip on a given memory |
| 703 | * bank ID. |
| 704 | * Return index of the probed flash in flash devices structure |
| 705 | */ |
| 706 | static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank) |
| 707 | { |
| 708 | int ret; |
| 709 | u32 val = 0; |
| 710 | |
| 711 | ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT); |
| 712 | if (ret) |
| 713 | return ret; |
| 714 | |
| 715 | mutex_lock(&dev->lock); |
| 716 | |
| 717 | dev->status = 0; /* Will be set in interrupt handler */ |
| 718 | /* put smi in sw mode */ |
| 719 | val = readl(dev->io_base + SMI_CR1); |
| 720 | writel(val | SW_MODE, dev->io_base + SMI_CR1); |
| 721 | |
| 722 | /* send readid command in sw mode */ |
| 723 | writel(OPCODE_RDID, dev->io_base + SMI_TR); |
| 724 | |
| 725 | val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) | |
| 726 | (3 << RX_LEN_SHIFT) | TFIE; |
| 727 | writel(val, dev->io_base + SMI_CR2); |
| 728 | |
| 729 | /* wait for TFF */ |
| 730 | ret = wait_event_interruptible_timeout(dev->cmd_complete, |
| 731 | dev->status & TFF, SMI_CMD_TIMEOUT); |
| 732 | if (ret <= 0) { |
| 733 | ret = -ENODEV; |
| 734 | goto err_probe; |
| 735 | } |
| 736 | |
| 737 | /* get memory chip id */ |
| 738 | val = readl(dev->io_base + SMI_RR); |
| 739 | val &= 0x00ffffff; |
| 740 | ret = get_flash_index(val); |
| 741 | |
| 742 | err_probe: |
| 743 | /* clear sw mode */ |
| 744 | val = readl(dev->io_base + SMI_CR1); |
| 745 | writel(val & ~SW_MODE, dev->io_base + SMI_CR1); |
| 746 | |
| 747 | mutex_unlock(&dev->lock); |
| 748 | return ret; |
| 749 | } |
| 750 | |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 751 | |
| 752 | #ifdef CONFIG_OF |
| 753 | static int __devinit spear_smi_probe_config_dt(struct platform_device *pdev, |
| 754 | struct device_node *np) |
| 755 | { |
| 756 | struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev); |
| 757 | struct device_node *pp = NULL; |
| 758 | const __be32 *addr; |
| 759 | u32 val; |
| 760 | int len; |
| 761 | int i = 0; |
| 762 | |
| 763 | if (!np) |
| 764 | return -ENODEV; |
| 765 | |
| 766 | of_property_read_u32(np, "clock-rate", &val); |
| 767 | pdata->clk_rate = val; |
| 768 | |
| 769 | pdata->board_flash_info = devm_kzalloc(&pdev->dev, |
| 770 | sizeof(*pdata->board_flash_info), |
| 771 | GFP_KERNEL); |
| 772 | |
| 773 | /* Fill structs for each subnode (flash device) */ |
| 774 | while ((pp = of_get_next_child(np, pp))) { |
| 775 | struct spear_smi_flash_info *flash_info; |
| 776 | |
| 777 | flash_info = &pdata->board_flash_info[i]; |
| 778 | pdata->np[i] = pp; |
| 779 | |
| 780 | /* Read base-addr and size from DT */ |
| 781 | addr = of_get_property(pp, "reg", &len); |
| 782 | pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]); |
| 783 | pdata->board_flash_info->size = be32_to_cpup(&addr[1]); |
| 784 | |
| 785 | if (of_get_property(pp, "st,smi-fast-mode", NULL)) |
| 786 | pdata->board_flash_info->fast_mode = 1; |
| 787 | |
| 788 | i++; |
| 789 | } |
| 790 | |
| 791 | pdata->num_flashes = i; |
| 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | #else |
| 796 | static int __devinit spear_smi_probe_config_dt(struct platform_device *pdev, |
| 797 | struct device_node *np) |
| 798 | { |
| 799 | return -ENOSYS; |
| 800 | } |
| 801 | #endif |
| 802 | |
| 803 | static int spear_smi_setup_banks(struct platform_device *pdev, |
| 804 | u32 bank, struct device_node *np) |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 805 | { |
| 806 | struct spear_smi *dev = platform_get_drvdata(pdev); |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 807 | struct mtd_part_parser_data ppdata = {}; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 808 | struct spear_smi_flash_info *flash_info; |
| 809 | struct spear_smi_plat_data *pdata; |
| 810 | struct spear_snor_flash *flash; |
Stefan Roese | f7e3dd8 | 2012-03-16 11:41:40 +0100 | [diff] [blame] | 811 | struct mtd_partition *parts = NULL; |
| 812 | int count = 0; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 813 | int flash_index; |
| 814 | int ret = 0; |
| 815 | |
| 816 | pdata = dev_get_platdata(&pdev->dev); |
| 817 | if (bank > pdata->num_flashes - 1) |
| 818 | return -EINVAL; |
| 819 | |
| 820 | flash_info = &pdata->board_flash_info[bank]; |
| 821 | if (!flash_info) |
| 822 | return -ENODEV; |
| 823 | |
| 824 | flash = kzalloc(sizeof(*flash), GFP_ATOMIC); |
| 825 | if (!flash) |
| 826 | return -ENOMEM; |
| 827 | flash->bank = bank; |
| 828 | flash->fast_mode = flash_info->fast_mode ? 1 : 0; |
| 829 | mutex_init(&flash->lock); |
| 830 | |
| 831 | /* verify whether nor flash is really present on board */ |
| 832 | flash_index = spear_smi_probe_flash(dev, bank); |
| 833 | if (flash_index < 0) { |
| 834 | dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank); |
| 835 | ret = flash_index; |
| 836 | goto err_probe; |
| 837 | } |
| 838 | /* map the memory for nor flash chip */ |
| 839 | flash->base_addr = ioremap(flash_info->mem_base, flash_info->size); |
| 840 | if (!flash->base_addr) { |
| 841 | ret = -EIO; |
| 842 | goto err_probe; |
| 843 | } |
| 844 | |
| 845 | dev->flash[bank] = flash; |
| 846 | flash->mtd.priv = dev; |
| 847 | |
| 848 | if (flash_info->name) |
| 849 | flash->mtd.name = flash_info->name; |
| 850 | else |
| 851 | flash->mtd.name = flash_devices[flash_index].name; |
| 852 | |
| 853 | flash->mtd.type = MTD_NORFLASH; |
| 854 | flash->mtd.writesize = 1; |
| 855 | flash->mtd.flags = MTD_CAP_NORFLASH; |
| 856 | flash->mtd.size = flash_info->size; |
| 857 | flash->mtd.erasesize = flash_devices[flash_index].sectorsize; |
| 858 | flash->page_size = flash_devices[flash_index].pagesize; |
Artem Bityutskiy | 81fefdf | 2012-02-03 10:14:12 +0200 | [diff] [blame] | 859 | flash->mtd.writebufsize = flash->page_size; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 860 | flash->erase_cmd = flash_devices[flash_index].erase_cmd; |
Artem Bityutskiy | 3c3c10b | 2012-01-30 14:58:32 +0200 | [diff] [blame] | 861 | flash->mtd._erase = spear_mtd_erase; |
| 862 | flash->mtd._read = spear_mtd_read; |
| 863 | flash->mtd._write = spear_mtd_write; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 864 | flash->dev_id = flash_devices[flash_index].device_id; |
| 865 | |
| 866 | dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n", |
| 867 | flash->mtd.name, flash->mtd.size, |
| 868 | flash->mtd.size / (1024 * 1024)); |
| 869 | |
| 870 | dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n", |
| 871 | flash->mtd.erasesize, flash->mtd.erasesize / 1024); |
| 872 | |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 873 | #ifndef CONFIG_OF |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 874 | if (flash_info->partitions) { |
| 875 | parts = flash_info->partitions; |
| 876 | count = flash_info->nr_partitions; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 877 | } |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 878 | #endif |
| 879 | ppdata.of_node = np; |
| 880 | |
| 881 | ret = mtd_device_parse_register(&flash->mtd, NULL, &ppdata, parts, |
| 882 | count); |
Stefan Roese | f7e3dd8 | 2012-03-16 11:41:40 +0100 | [diff] [blame] | 883 | if (ret) { |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 884 | dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret); |
Stefan Roese | f7e3dd8 | 2012-03-16 11:41:40 +0100 | [diff] [blame] | 885 | goto err_map; |
| 886 | } |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 887 | |
Stefan Roese | f7e3dd8 | 2012-03-16 11:41:40 +0100 | [diff] [blame] | 888 | return 0; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 889 | |
| 890 | err_map: |
| 891 | iounmap(flash->base_addr); |
| 892 | |
| 893 | err_probe: |
| 894 | kfree(flash); |
| 895 | return ret; |
| 896 | } |
| 897 | |
| 898 | /** |
| 899 | * spear_smi_probe - Entry routine |
| 900 | * @pdev: platform device structure |
| 901 | * |
| 902 | * This is the first routine which gets invoked during booting and does all |
| 903 | * initialization/allocation work. The routine looks for available memory banks, |
| 904 | * and do proper init for any found one. |
| 905 | * Returns 0 on success, non zero otherwise |
| 906 | */ |
| 907 | static int __devinit spear_smi_probe(struct platform_device *pdev) |
| 908 | { |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 909 | struct device_node *np = pdev->dev.of_node; |
| 910 | struct spear_smi_plat_data *pdata = NULL; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 911 | struct spear_smi *dev; |
| 912 | struct resource *smi_base; |
| 913 | int irq, ret = 0; |
| 914 | int i; |
| 915 | |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 916 | if (np) { |
| 917 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 918 | if (!pdata) { |
| 919 | pr_err("%s: ERROR: no memory", __func__); |
| 920 | ret = -ENOMEM; |
| 921 | goto err; |
| 922 | } |
| 923 | pdev->dev.platform_data = pdata; |
| 924 | ret = spear_smi_probe_config_dt(pdev, np); |
| 925 | if (ret) { |
| 926 | ret = -ENODEV; |
| 927 | dev_err(&pdev->dev, "no platform data\n"); |
| 928 | goto err; |
| 929 | } |
| 930 | } else { |
| 931 | pdata = dev_get_platdata(&pdev->dev); |
| 932 | if (pdata < 0) { |
| 933 | ret = -ENODEV; |
| 934 | dev_err(&pdev->dev, "no platform data\n"); |
| 935 | goto err; |
| 936 | } |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 940 | if (!smi_base) { |
| 941 | ret = -ENODEV; |
| 942 | dev_err(&pdev->dev, "invalid smi base address\n"); |
| 943 | goto err; |
| 944 | } |
| 945 | |
| 946 | irq = platform_get_irq(pdev, 0); |
| 947 | if (irq < 0) { |
| 948 | ret = -ENODEV; |
| 949 | dev_err(&pdev->dev, "invalid smi irq\n"); |
| 950 | goto err; |
| 951 | } |
| 952 | |
| 953 | dev = kzalloc(sizeof(*dev), GFP_ATOMIC); |
| 954 | if (!dev) { |
| 955 | ret = -ENOMEM; |
| 956 | dev_err(&pdev->dev, "mem alloc fail\n"); |
| 957 | goto err; |
| 958 | } |
| 959 | |
| 960 | smi_base = request_mem_region(smi_base->start, resource_size(smi_base), |
| 961 | pdev->name); |
| 962 | if (!smi_base) { |
| 963 | ret = -EBUSY; |
| 964 | dev_err(&pdev->dev, "request mem region fail\n"); |
| 965 | goto err_mem; |
| 966 | } |
| 967 | |
| 968 | dev->io_base = ioremap(smi_base->start, resource_size(smi_base)); |
| 969 | if (!dev->io_base) { |
| 970 | ret = -EIO; |
| 971 | dev_err(&pdev->dev, "ioremap fail\n"); |
| 972 | goto err_ioremap; |
| 973 | } |
| 974 | |
| 975 | dev->pdev = pdev; |
| 976 | dev->clk_rate = pdata->clk_rate; |
| 977 | |
| 978 | if (dev->clk_rate < 0 || dev->clk_rate > SMI_MAX_CLOCK_FREQ) |
| 979 | dev->clk_rate = SMI_MAX_CLOCK_FREQ; |
| 980 | |
| 981 | dev->num_flashes = pdata->num_flashes; |
| 982 | |
| 983 | if (dev->num_flashes > MAX_NUM_FLASH_CHIP) { |
| 984 | dev_err(&pdev->dev, "exceeding max number of flashes\n"); |
| 985 | dev->num_flashes = MAX_NUM_FLASH_CHIP; |
| 986 | } |
| 987 | |
| 988 | dev->clk = clk_get(&pdev->dev, NULL); |
| 989 | if (IS_ERR(dev->clk)) { |
| 990 | ret = PTR_ERR(dev->clk); |
| 991 | goto err_clk; |
| 992 | } |
| 993 | |
Viresh Kumar | c0010eb | 2012-04-17 17:07:56 +0530 | [diff] [blame] | 994 | ret = clk_prepare_enable(dev->clk); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 995 | if (ret) |
Viresh Kumar | c0010eb | 2012-04-17 17:07:56 +0530 | [diff] [blame] | 996 | goto err_clk_prepare_enable; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 997 | |
| 998 | ret = request_irq(irq, spear_smi_int_handler, 0, pdev->name, dev); |
| 999 | if (ret) { |
| 1000 | dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n"); |
| 1001 | goto err_irq; |
| 1002 | } |
| 1003 | |
| 1004 | mutex_init(&dev->lock); |
| 1005 | init_waitqueue_head(&dev->cmd_complete); |
| 1006 | spear_smi_hw_init(dev); |
| 1007 | platform_set_drvdata(pdev, dev); |
| 1008 | |
| 1009 | /* loop for each serial nor-flash which is connected to smi */ |
| 1010 | for (i = 0; i < dev->num_flashes; i++) { |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 1011 | ret = spear_smi_setup_banks(pdev, i, pdata->np[i]); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1012 | if (ret) { |
| 1013 | dev_err(&dev->pdev->dev, "bank setup failed\n"); |
| 1014 | goto err_bank_setup; |
| 1015 | } |
| 1016 | } |
| 1017 | |
| 1018 | return 0; |
| 1019 | |
| 1020 | err_bank_setup: |
| 1021 | free_irq(irq, dev); |
| 1022 | platform_set_drvdata(pdev, NULL); |
| 1023 | err_irq: |
Viresh Kumar | c0010eb | 2012-04-17 17:07:56 +0530 | [diff] [blame] | 1024 | clk_disable_unprepare(dev->clk); |
| 1025 | err_clk_prepare_enable: |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1026 | clk_put(dev->clk); |
| 1027 | err_clk: |
| 1028 | iounmap(dev->io_base); |
| 1029 | err_ioremap: |
| 1030 | release_mem_region(smi_base->start, resource_size(smi_base)); |
| 1031 | err_mem: |
| 1032 | kfree(dev); |
| 1033 | err: |
| 1034 | return ret; |
| 1035 | } |
| 1036 | |
| 1037 | /** |
| 1038 | * spear_smi_remove - Exit routine |
| 1039 | * @pdev: platform device structure |
| 1040 | * |
| 1041 | * free all allocations and delete the partitions. |
| 1042 | */ |
| 1043 | static int __devexit spear_smi_remove(struct platform_device *pdev) |
| 1044 | { |
| 1045 | struct spear_smi *dev; |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 1046 | struct spear_smi_plat_data *pdata; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1047 | struct spear_snor_flash *flash; |
Shiraz Hashim | 495c47d | 2012-01-20 11:35:19 +0100 | [diff] [blame] | 1048 | struct resource *smi_base; |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1049 | int ret; |
| 1050 | int i, irq; |
| 1051 | |
| 1052 | dev = platform_get_drvdata(pdev); |
| 1053 | if (!dev) { |
| 1054 | dev_err(&pdev->dev, "dev is null\n"); |
| 1055 | return -ENODEV; |
| 1056 | } |
| 1057 | |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 1058 | pdata = dev_get_platdata(&pdev->dev); |
| 1059 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1060 | /* clean up for all nor flash */ |
| 1061 | for (i = 0; i < dev->num_flashes; i++) { |
| 1062 | flash = dev->flash[i]; |
| 1063 | if (!flash) |
| 1064 | continue; |
| 1065 | |
| 1066 | /* clean up mtd stuff */ |
| 1067 | ret = mtd_device_unregister(&flash->mtd); |
| 1068 | if (ret) |
| 1069 | dev_err(&pdev->dev, "error removing mtd\n"); |
| 1070 | |
| 1071 | iounmap(flash->base_addr); |
| 1072 | kfree(flash); |
| 1073 | } |
| 1074 | |
| 1075 | irq = platform_get_irq(pdev, 0); |
| 1076 | free_irq(irq, dev); |
| 1077 | |
Viresh Kumar | c0010eb | 2012-04-17 17:07:56 +0530 | [diff] [blame] | 1078 | clk_disable_unprepare(dev->clk); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1079 | clk_put(dev->clk); |
| 1080 | iounmap(dev->io_base); |
| 1081 | kfree(dev); |
Shiraz Hashim | 495c47d | 2012-01-20 11:35:19 +0100 | [diff] [blame] | 1082 | |
| 1083 | smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1084 | release_mem_region(smi_base->start, resource_size(smi_base)); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1085 | platform_set_drvdata(pdev, NULL); |
| 1086 | |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1090 | #ifdef CONFIG_PM |
| 1091 | static int spear_smi_suspend(struct device *dev) |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1092 | { |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1093 | struct spear_smi *sdev = dev_get_drvdata(dev); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1094 | |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1095 | if (sdev && sdev->clk) |
| 1096 | clk_disable_unprepare(sdev->clk); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1097 | |
| 1098 | return 0; |
| 1099 | } |
| 1100 | |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1101 | static int spear_smi_resume(struct device *dev) |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1102 | { |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1103 | struct spear_smi *sdev = dev_get_drvdata(dev); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1104 | int ret = -EPERM; |
| 1105 | |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1106 | if (sdev && sdev->clk) |
| 1107 | ret = clk_prepare_enable(sdev->clk); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1108 | |
| 1109 | if (!ret) |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1110 | spear_smi_hw_init(sdev); |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1111 | return ret; |
| 1112 | } |
| 1113 | |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1114 | static SIMPLE_DEV_PM_OPS(spear_smi_pm_ops, spear_smi_suspend, spear_smi_resume); |
| 1115 | #endif |
| 1116 | |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 1117 | #ifdef CONFIG_OF |
| 1118 | static const struct of_device_id spear_smi_id_table[] = { |
| 1119 | { .compatible = "st,spear600-smi" }, |
| 1120 | {} |
| 1121 | }; |
| 1122 | MODULE_DEVICE_TABLE(of, spear_smi_id_table); |
| 1123 | #endif |
| 1124 | |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1125 | static struct platform_driver spear_smi_driver = { |
| 1126 | .driver = { |
| 1127 | .name = "smi", |
| 1128 | .bus = &platform_bus_type, |
| 1129 | .owner = THIS_MODULE, |
Stefan Roese | 6551ab5 | 2012-03-16 11:42:11 +0100 | [diff] [blame] | 1130 | .of_match_table = of_match_ptr(spear_smi_id_table), |
Viresh Kumar | 770daa4 | 2012-07-02 11:28:45 +0530 | [diff] [blame^] | 1131 | #ifdef CONFIG_PM |
| 1132 | .pm = &spear_smi_pm_ops, |
| 1133 | #endif |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1134 | }, |
| 1135 | .probe = spear_smi_probe, |
| 1136 | .remove = __devexit_p(spear_smi_remove), |
Shiraz Hashim | f18dbbb | 2012-01-12 14:38:57 +0100 | [diff] [blame] | 1137 | }; |
| 1138 | |
| 1139 | static int spear_smi_init(void) |
| 1140 | { |
| 1141 | return platform_driver_register(&spear_smi_driver); |
| 1142 | } |
| 1143 | module_init(spear_smi_init); |
| 1144 | |
| 1145 | static void spear_smi_exit(void) |
| 1146 | { |
| 1147 | platform_driver_unregister(&spear_smi_driver); |
| 1148 | } |
| 1149 | module_exit(spear_smi_exit); |
| 1150 | |
| 1151 | MODULE_LICENSE("GPL"); |
| 1152 | MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.hashim@st.com>"); |
| 1153 | MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips"); |