blob: a144b89cf9ba299e5f9fb2bcea5fd179f5ceb413 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/types.h>
Ralf Baechle334955e2011-06-01 19:04:57 +010021#include <linux/i8253.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/init.h>
23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/timex.h>
28#include <linux/mc146818rtc.h>
29
30#include <asm/mipsregs.h>
Ralf Baechle41c594a2006-04-05 09:45:45 +010031#include <asm/mipsmtregs.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000032#include <asm/hardirq.h>
33#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/div64.h>
David Howellsb81947c2012-03-28 18:30:02 +010035#include <asm/setup.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/time.h>
37#include <asm/mc146818-time.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000038#include <asm/msc01_ic.h>
Steven J. Hill778eeb12012-12-07 03:51:04 +000039#include <asm/gic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
41#include <asm/mips-boards/generic.h>
42#include <asm/mips-boards/prom.h>
Maciej W. Rozyckifc095a92006-09-12 19:12:18 +010043
Ralf Baechlee01402b2005-07-14 15:57:16 +000044#include <asm/mips-boards/maltaint.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
46unsigned long cpu_khz;
Steven J. Hill778eeb12012-12-07 03:51:04 +000047int gic_frequency;
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Ralf Baechlee01402b2005-07-14 15:57:16 +000049static int mips_cpu_timer_irq;
Ralf Baechle39b8d522008-04-28 17:14:26 +010050static int mips_cpu_perf_irq;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +010051extern int cp0_perfcount_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Ralf Baechle937a8012006-10-07 19:44:33 +010053static void mips_timer_dispatch(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054{
Ralf Baechle937a8012006-10-07 19:44:33 +010055 do_IRQ(mips_cpu_timer_irq);
Ralf Baechlee01402b2005-07-14 15:57:16 +000056}
57
Chris Dearmanffe9ee42007-05-24 22:24:20 +010058static void mips_perf_dispatch(void)
59{
Ralf Baechle39b8d522008-04-28 17:14:26 +010060 do_IRQ(mips_cpu_perf_irq);
Chris Dearmanffe9ee42007-05-24 22:24:20 +010061}
62
Steven J. Hill778eeb12012-12-07 03:51:04 +000063static unsigned int freqround(unsigned int freq, unsigned int amount)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064{
Steven J. Hill778eeb12012-12-07 03:51:04 +000065 freq += amount;
66 freq -= freq % (amount*2);
67 return freq;
68}
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Steven J. Hill778eeb12012-12-07 03:51:04 +000070/*
71 * Estimate CPU and GIC frequencies.
72 */
73static void __init estimate_frequencies(void)
74{
Ralf Baechlee79f55a2006-10-31 19:53:15 +000075 unsigned long flags;
Steven J. Hill778eeb12012-12-07 03:51:04 +000076 unsigned int count, start;
77 unsigned int giccount = 0, gicstart = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 local_irq_save(flags);
80
Steven J. Hill778eeb12012-12-07 03:51:04 +000081 /* Start counter exactly on falling edge of update flag. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
83 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
84
Steven J. Hill778eeb12012-12-07 03:51:04 +000085 /* Initialize counters. */
Ralf Baechle70e46f42006-10-31 18:33:09 +000086 start = read_c0_count();
Steven J. Hill778eeb12012-12-07 03:51:04 +000087 if (gic_present)
88 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
Linus Torvalds1da177e2005-04-16 15:20:36 -070089
Steven J. Hill778eeb12012-12-07 03:51:04 +000090 /* Read counter exactly on falling edge of update flag. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
92 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
93
Steven J. Hill778eeb12012-12-07 03:51:04 +000094 count = read_c0_count();
95 if (gic_present)
96 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Steven J. Hill778eeb12012-12-07 03:51:04 +0000100 count -= start;
101 if (gic_present)
102 giccount -= gicstart;
103
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 mips_hpt_frequency = count;
Steven J. Hill778eeb12012-12-07 03:51:04 +0000105 if (gic_present)
106 gic_frequency = giccount;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107}
108
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200109void read_persistent_clock(struct timespec *ts)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110{
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200111 ts->tv_sec = mc146818_get_cmos_time();
112 ts->tv_nsec = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113}
114
Dmitri Vorobievb31dc3c2008-04-01 02:03:23 +0400115static void __init plat_perf_setup(void)
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100116{
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100117#ifdef MSC01E_INT_BASE
118 if (cpu_has_veic) {
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100119 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100120 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100121 } else
122#endif
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +0100123 if (cp0_perfcount_irq >= 0) {
124 if (cpu_has_vint)
125 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100126 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100127#ifdef CONFIG_SMP
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200128 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100129#endif
130 }
131}
132
Ralf Baechle234fcd12008-03-08 09:56:28 +0000133unsigned int __cpuinit get_c0_compare_int(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134{
Chris Dearman7b4f4ec2007-05-24 22:46:25 +0100135#ifdef MSC01E_INT_BASE
Ralf Baechlee01402b2005-07-14 15:57:16 +0000136 if (cpu_has_veic) {
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100137 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
Ralf Baechlee01402b2005-07-14 15:57:16 +0000138 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
Ralf Baechle38760d42007-10-29 14:23:43 +0000139 } else
Chris Dearman7b4f4ec2007-05-24 22:46:25 +0100140#endif
141 {
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100142 if (cpu_has_vint)
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +0100143 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
144 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100145 }
Ralf Baechlee01402b2005-07-14 15:57:16 +0000146
Ralf Baechle38760d42007-10-29 14:23:43 +0000147 return mips_cpu_timer_irq;
148}
149
150void __init plat_time_init(void)
151{
Steven J. Hill778eeb12012-12-07 03:51:04 +0000152 unsigned int prid = read_c0_prid() & 0xffff00;
153 unsigned int freq;
Ralf Baechle38760d42007-10-29 14:23:43 +0000154
Steven J. Hill778eeb12012-12-07 03:51:04 +0000155 estimate_frequencies();
Ralf Baechle38760d42007-10-29 14:23:43 +0000156
Steven J. Hill778eeb12012-12-07 03:51:04 +0000157 freq = mips_hpt_frequency;
158 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
159 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
160 freq *= 2;
161 freq = freqround(freq, 5000);
162 pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
163 (freq%1000000)*100/1000000);
164 cpu_khz = freq / 1000;
Ralf Baechle38760d42007-10-29 14:23:43 +0000165
Steven J. Hill778eeb12012-12-07 03:51:04 +0000166 if (gic_present) {
167 freq = freqround(gic_frequency, 5000);
168 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
169 (freq%1000000)*100/1000000);
170 gic_clocksource_init(gic_frequency);
171 } else
172 init_r4k_clocksource();
Ralf Baechle38760d42007-10-29 14:23:43 +0000173
Steven J. Hill778eeb12012-12-07 03:51:04 +0000174#ifdef CONFIG_I8253
175 /* Only Malta has a PIT. */
Ralf Baechle38760d42007-10-29 14:23:43 +0000176 setup_pit_timer();
Ralf Baechle340ee4b2005-08-17 17:44:08 +0000177#endif
Chris Dearmanffe9ee42007-05-24 22:24:20 +0100178
Steven J. Hill778eeb12012-12-07 03:51:04 +0000179 mips_scroll_message();
180
Ralf Baechle91a2fcc2007-10-11 23:46:09 +0100181 plat_perf_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182}