blob: 32c8991669d11bb889d31ea7670e021147ff2972 [file] [log] [blame]
Eugeni Dodonov45244b82012-05-09 15:37:20 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
Jani Nikula10122052014-08-27 16:27:30 +030031struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
David Weinehallf8896f52015-06-25 11:11:03 +030034 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
Jani Nikula10122052014-08-27 16:27:30 +030035};
36
Eugeni Dodonov45244b82012-05-09 15:37:20 -030037/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
Jani Nikula10122052014-08-27 16:27:30 +030041static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030042 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
Eugeni Dodonov45244b82012-05-09 15:37:20 -030051};
52
Jani Nikula10122052014-08-27 16:27:30 +030053static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030054 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
Paulo Zanoni6acab152013-09-12 17:06:24 -030063};
64
Jani Nikula10122052014-08-27 16:27:30 +030065static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
David Weinehallf8896f52015-06-25 11:11:03 +030067 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
Eugeni Dodonov45244b82012-05-09 15:37:20 -030079};
80
Jani Nikula10122052014-08-27 16:27:30 +030081static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030082 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
Paulo Zanoni300644c2013-11-02 21:07:42 -070091};
92
Jani Nikula10122052014-08-27 16:27:30 +030093static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030094 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700103};
104
Jani Nikula10122052014-08-27 16:27:30 +0300105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700115};
116
Jani Nikula10122052014-08-27 16:27:30 +0300117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
David Weinehallf8896f52015-06-25 11:11:03 +0300119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100129};
130
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700131/* Skylake H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800136 { 0x80009010, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800139 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300140 { 0x00002016, 0x000000DF, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800141 { 0x80005012, 0x000000C0, 0x1 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000142};
143
David Weinehallf8896f52015-06-25 11:11:03 +0300144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700146 { 0x0000201B, 0x000000A2, 0x0 },
David Weinehallf8896f52015-06-25 11:11:03 +0300147 { 0x00005012, 0x00000088, 0x0 },
Rodrigo Vivi63ebce12016-01-05 07:58:31 -0800148 { 0x80007011, 0x000000CD, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800149 { 0x80009010, 0x000000C0, 0x1 },
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700150 { 0x0000201B, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300153 { 0x00002016, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800154 { 0x80005012, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300155};
156
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
Rodrigo Vivi63ebce12016-01-05 07:58:31 -0800161 { 0x80007011, 0x000000CD, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800162 { 0x80009010, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300163 { 0x00000018, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300166 { 0x00000018, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800167 { 0x80005012, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300168};
169
170/*
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700171 * Skylake H and S
David Weinehallf8896f52015-06-25 11:11:03 +0300172 * eDP 1.4 low vswing translation parameters
173 */
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530185};
186
David Weinehallf8896f52015-06-25 11:11:03 +0300187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202};
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530203
David Weinehallf8896f52015-06-25 11:11:03 +0300204/*
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700205 * Skylake Y
David Weinehallf8896f52015-06-25 11:11:03 +0300206 * eDP 1.4 low vswing translation parameters
207 */
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
220
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700221/* Skylake U, H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800229 { 0x80006012, 0x000000CD, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300230 { 0x00000018, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300234};
235
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800240 { 0x80007011, 0x000000CB, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800244 { 0x80006013, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300245 { 0x00000018, 0x0000008A, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000249};
250
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
David Weinehallf8896f52015-06-25 11:11:03 +0300270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530271};
272
Sonika Jindald9d70002015-09-24 10:24:56 +0530273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
David Weinehallf8896f52015-06-25 11:11:03 +0300306
Imre Deaka1e6ad62015-04-17 19:31:21 +0300307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
Paulo Zanonifc914632012-10-05 12:05:54 -0300310{
Paulo Zanoni0bdee302012-10-15 15:51:38 -0300311 struct drm_encoder *encoder = &intel_encoder->base;
Paulo Zanonifc914632012-10-05 12:05:54 -0300312
Jani Nikula8cd21b72015-09-29 10:24:26 +0300313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
Imre Deaka1e6ad62015-04-17 19:31:21 +0300315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
Jani Nikula8cd21b72015-09-29 10:24:26 +0300317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
Imre Deaka1e6ad62015-04-17 19:31:21 +0300322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
Jani Nikula8cd21b72015-09-29 10:24:26 +0300324 break;
325 case INTEL_OUTPUT_ANALOG:
Imre Deaka1e6ad62015-04-17 19:31:21 +0300326 *dig_port = NULL;
327 *port = PORT_E;
Jani Nikula8cd21b72015-09-29 10:24:26 +0300328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
Paulo Zanonifc914632012-10-05 12:05:54 -0300332 }
333}
334
Imre Deaka1e6ad62015-04-17 19:31:21 +0300335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
Ville Syrjäläacee2992015-12-08 19:59:39 +0200345static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200346skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300347{
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200350 return skl_y_ddi_translations_dp;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
David Weinehallf8896f52015-06-25 11:11:03 +0300352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200353 return skl_u_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300354 } else {
David Weinehallf8896f52015-06-25 11:11:03 +0300355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200356 return skl_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300357 }
David Weinehallf8896f52015-06-25 11:11:03 +0300358}
359
360static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200361skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300362{
Ville Syrjäläcd1101c2015-12-08 19:59:40 +0200363 if (dev_priv->edp_low_vswing) {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
366 return skl_y_ddi_translations_edp;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
369 return skl_u_ddi_translations_edp;
370 } else {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
372 return skl_ddi_translations_edp;
Ville Syrjäläacee2992015-12-08 19:59:39 +0200373 }
David Weinehallf8896f52015-06-25 11:11:03 +0300374 }
Ville Syrjäläcd1101c2015-12-08 19:59:40 +0200375
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200376 return skl_get_buf_trans_dp(dev_priv, n_entries);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200377}
David Weinehallf8896f52015-06-25 11:11:03 +0300378
Ville Syrjäläacee2992015-12-08 19:59:39 +0200379static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200380skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
Ville Syrjäläacee2992015-12-08 19:59:39 +0200381{
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
384 return skl_y_ddi_translations_hdmi;
385 } else {
386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
387 return skl_ddi_translations_hdmi;
388 }
David Weinehallf8896f52015-06-25 11:11:03 +0300389}
390
Art Runyane58623c2013-11-02 21:07:41 -0700391/*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200398void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300399{
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Antti Koskipaa75067dd2015-07-10 14:10:55 +0300401 u32 iboost_bit = 0;
Damien Lespiau7ff44672015-03-02 16:19:36 +0000402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530403 size;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200404 int hdmi_level;
405 enum port port;
Jani Nikula10122052014-08-27 16:27:30 +0300406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
Art Runyane58623c2013-11-02 21:07:41 -0700411
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200415 if (IS_BROXTON(dev_priv)) {
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200416 if (encoder->type != INTEL_OUTPUT_HDMI)
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530417 return;
418
419 /* Vswing programming for HDMI */
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530421 INTEL_OUTPUT_HDMI);
422 return;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Paulo Zanonic30400f2015-07-03 12:31:30 -0300426 ddi_translations_fdi = NULL;
David Weinehallf8896f52015-06-25 11:11:03 +0300427 ddi_translations_dp =
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
David Weinehallf8896f52015-06-25 11:11:03 +0300429 ddi_translations_edp =
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
David Weinehallf8896f52015-06-25 11:11:03 +0300431 ddi_translations_hdmi =
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
David Weinehallf8896f52015-06-25 11:11:03 +0300433 hdmi_default_entry = 8;
Antti Koskipaa75067dd2015-07-10 14:10:55 +0300434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
Ville Syrjälä10afa0b2015-12-08 19:59:43 +0200438
Ville Syrjäläceccad52016-01-12 17:28:16 +0200439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
Ville Syrjälä10afa0b2015-12-08 19:59:43 +0200442 n_edp_entries = 9;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200443 } else if (IS_BROADWELL(dev_priv)) {
Art Runyane58623c2013-11-02 21:07:41 -0700444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700446 ddi_translations_edp = bdw_ddi_translations_edp;
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
Jani Nikula10122052014-08-27 16:27:30 +0300450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
Damien Lespiau7ff44672015-03-02 16:19:36 +0000451 hdmi_default_entry = 7;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200452 } else if (IS_HASWELL(dev_priv)) {
Art Runyane58623c2013-11-02 21:07:41 -0700453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700455 ddi_translations_edp = hsw_ddi_translations_dp;
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
Jani Nikula10122052014-08-27 16:27:30 +0300458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
Damien Lespiau7ff44672015-03-02 16:19:36 +0000459 hdmi_default_entry = 6;
Art Runyane58623c2013-11-02 21:07:41 -0700460 } else {
461 WARN(1, "ddi translation table missing\n");
Paulo Zanoni300644c2013-11-02 21:07:42 -0700462 ddi_translations_edp = bdw_ddi_translations_dp;
Art Runyane58623c2013-11-02 21:07:41 -0700463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
Jani Nikula10122052014-08-27 16:27:30 +0300468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
Damien Lespiau7ff44672015-03-02 16:19:36 +0000469 hdmi_default_entry = 7;
Art Runyane58623c2013-11-02 21:07:41 -0700470 }
471
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
Paulo Zanoni300644c2013-11-02 21:07:42 -0700474 ddi_translations = ddi_translations_edp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530475 size = n_edp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700476 break;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
Paulo Zanoni300644c2013-11-02 21:07:42 -0700479 ddi_translations = ddi_translations_dp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530480 size = n_dp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700481 break;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530484 size = n_dp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700485 break;
486 default:
487 BUG();
488 }
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300489
Ville Syrjälä9712e682015-09-18 20:03:22 +0300490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300495 }
Damien Lespiauce4dd492014-08-01 11:07:54 +0100496
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200497 if (encoder->type != INTEL_OUTPUT_HDMI)
Damien Lespiauce3b7e92014-08-04 15:04:43 +0100498 return;
499
Damien Lespiauce4dd492014-08-01 11:07:54 +0100500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
Damien Lespiau7ff44672015-03-02 16:19:36 +0000503 hdmi_level = hdmi_default_entry;
Damien Lespiauce4dd492014-08-01 11:07:54 +0100504
Paulo Zanoni6acab152013-09-12 17:06:24 -0300505 /* Entry 9 is for HDMI: */
Ville Syrjälä9712e682015-09-18 20:03:22 +0300506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300510}
511
Paulo Zanoni248138b2012-11-29 11:29:31 -0200512static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
513 enum port port)
514{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200515 i915_reg_t reg = DDI_BUF_CTL(port);
Paulo Zanoni248138b2012-11-29 11:29:31 -0200516 int i;
517
Vandana Kannan3449ca82015-03-27 14:19:09 +0200518 for (i = 0; i < 16; i++) {
Paulo Zanoni248138b2012-11-29 11:29:31 -0200519 udelay(1);
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
521 return;
522 }
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
524}
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300525
526/* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
529 *
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
533 */
534
535void hsw_fdi_link_train(struct drm_crtc *crtc)
536{
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200540 struct intel_encoder *encoder;
Paulo Zanoni04945642012-11-01 21:00:59 -0200541 u32 temp, i, rx_ctl_val;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300542
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
546 }
547
Paulo Zanoni04945642012-11-01 21:00:59 -0200548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
551 * - FDI delay to 90h
Damien Lespiau8693a822013-05-03 18:48:11 +0100552 *
553 * WaFDIAutoLinkSetTimingOverrride:hsw
Paulo Zanoni04945642012-11-01 21:00:59 -0200554 */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
Paulo Zanoni04945642012-11-01 21:00:59 -0200556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
558
559 /* Enable the PCH Receiver FDI PLL */
Damien Lespiau3e683202012-12-11 18:48:29 +0000560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
Daniel Vetter33d29b12013-02-13 18:04:45 +0100561 FDI_RX_PLL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200565 udelay(220);
566
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
Paulo Zanoni04945642012-11-01 21:00:59 -0200570
571 /* Configure Port Clock Select */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
Paulo Zanoni04945642012-11-01 21:00:59 -0200574
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
Jani Nikula10122052014-08-27 16:27:30 +0300577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
583 DP_TP_CTL_ENABLE);
584
Damien Lespiau876a8cd2012-12-11 18:48:30 +0000585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300589 I915_WRITE(DDI_BUF_CTL(PORT_E),
Paulo Zanoni04945642012-11-01 21:00:59 -0200590 DDI_BUF_CTL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530592 DDI_BUF_TRANS_SELECT(i / 2));
Paulo Zanoni04945642012-11-01 21:00:59 -0200593 POSTING_READ(DDI_BUF_CTL(PORT_E));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300594
595 udelay(600);
596
Paulo Zanoni04945642012-11-01 21:00:59 -0200597 /* Program PCH FDI Receiver TU */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
Eugeni Dodonov4acf5182012-07-04 20:15:16 -0300599
Paulo Zanoni04945642012-11-01 21:00:59 -0200600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200604
605 /* Wait for FDI receiver lane calibration */
606 udelay(30);
607
608 /* Unset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200613
614 /* Wait for FDI auto training time */
615 udelay(5);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300616
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
Paulo Zanoni04945642012-11-01 21:00:59 -0200619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200620 break;
621 }
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300622
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200623 /*
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
626 */
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
629 break;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300630 }
Paulo Zanoni04945642012-11-01 21:00:59 -0200631
Paulo Zanoni248138b2012-11-29 11:29:31 -0200632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
636
Paulo Zanoni04945642012-11-01 21:00:59 -0200637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
Paulo Zanoni248138b2012-11-29 11:29:31 -0200638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
643
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
Paulo Zanoni04945642012-11-01 21:00:59 -0200645
646 rx_ctl_val &= ~FDI_RX_ENABLE;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200649
650 /* Reset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300656 }
657
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
663 DP_TP_CTL_ENABLE);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300664}
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -0300665
Dave Airlie44905a272014-05-02 13:36:43 +1000666void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
667{
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
671
672 intel_dp->DP = intel_dig_port->saved_port_bits |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
Ville Syrjälä901c2da2015-08-17 18:05:12 +0300674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
Dave Airlie44905a272014-05-02 13:36:43 +1000675}
676
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300677static struct intel_encoder *
678intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
679{
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
684
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
686 ret = intel_encoder;
687 num_encoders++;
688 }
689
690 if (num_encoders != 1)
Ville Syrjälä84f44ce2013-04-17 17:48:49 +0300691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300693
694 BUG_ON(ret == NULL);
695 return ret;
696}
697
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +0530698struct intel_encoder *
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200699intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200700{
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200706 int num_encoders = 0;
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200707 int i;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200708
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200709 state = crtc_state->base.state;
710
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200713 continue;
714
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300715 ret = to_intel_encoder(connector_state->best_encoder);
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200716 num_encoders++;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200717 }
718
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
721
722 BUG_ON(ret == NULL);
723 return ret;
724}
725
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100726#define LC_FREQ 2700
Damien Lespiau27893392014-09-04 12:27:23 +0100727#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100728
729#define P_MIN 2
730#define P_MAX 64
731#define P_INC 2
732
733/* Constraints for PLL good behavior */
734#define REF_MIN 48
735#define REF_MAX 400
736#define VCO_MIN 2400
737#define VCO_MAX 4800
738
Damien Lespiau27893392014-09-04 12:27:23 +0100739#define abs_diff(a, b) ({ \
740 typeof(a) __a = (a); \
741 typeof(b) __b = (b); \
742 (void) (&__a == &__b); \
743 __a > __b ? (__a - __b) : (__b - __a); })
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100744
Damien Lespiau63582982015-05-07 18:38:46 +0100745struct hsw_wrpll_rnp {
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100746 unsigned p, n2, r2;
747};
748
Damien Lespiau63582982015-05-07 18:38:46 +0100749static unsigned hsw_wrpll_get_budget_for_freq(int clock)
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300750{
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100751 unsigned budget;
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300752
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100753 switch (clock) {
754 case 25175000:
755 case 25200000:
756 case 27000000:
757 case 27027000:
758 case 37762500:
759 case 37800000:
760 case 40500000:
761 case 40541000:
762 case 54000000:
763 case 54054000:
764 case 59341000:
765 case 59400000:
766 case 72000000:
767 case 74176000:
768 case 74250000:
769 case 81000000:
770 case 81081000:
771 case 89012000:
772 case 89100000:
773 case 108000000:
774 case 108108000:
775 case 111264000:
776 case 111375000:
777 case 148352000:
778 case 148500000:
779 case 162000000:
780 case 162162000:
781 case 222525000:
782 case 222750000:
783 case 296703000:
784 case 297000000:
785 budget = 0;
786 break;
787 case 233500000:
788 case 245250000:
789 case 247750000:
790 case 253250000:
791 case 298000000:
792 budget = 1500;
793 break;
794 case 169128000:
795 case 169500000:
796 case 179500000:
797 case 202000000:
798 budget = 2000;
799 break;
800 case 256250000:
801 case 262500000:
802 case 270000000:
803 case 272500000:
804 case 273750000:
805 case 280750000:
806 case 281250000:
807 case 286000000:
808 case 291750000:
809 budget = 4000;
810 break;
811 case 267250000:
812 case 268500000:
813 budget = 5000;
814 break;
815 default:
816 budget = 1000;
817 break;
818 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300819
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100820 return budget;
821}
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300822
Damien Lespiau63582982015-05-07 18:38:46 +0100823static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
824 unsigned r2, unsigned n2, unsigned p,
825 struct hsw_wrpll_rnp *best)
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100826{
827 uint64_t a, b, c, d, diff, diff_best;
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300828
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100829 /* No best (r,n,p) yet */
830 if (best->p == 0) {
831 best->p = p;
832 best->n2 = n2;
833 best->r2 = r2;
834 return;
835 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300836
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100837 /*
838 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
839 * freq2k.
840 *
841 * delta = 1e6 *
842 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
843 * freq2k;
844 *
845 * and we would like delta <= budget.
846 *
847 * If the discrepancy is above the PPM-based budget, always prefer to
848 * improve upon the previous solution. However, if you're within the
849 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
850 */
851 a = freq2k * budget * p * r2;
852 b = freq2k * budget * best->p * best->r2;
Damien Lespiau27893392014-09-04 12:27:23 +0100853 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
854 diff_best = abs_diff(freq2k * best->p * best->r2,
855 LC_FREQ_2K * best->n2);
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100856 c = 1000000 * diff;
857 d = 1000000 * diff_best;
858
859 if (a < c && b < d) {
860 /* If both are above the budget, pick the closer */
861 if (best->p * best->r2 * diff < p * r2 * diff_best) {
862 best->p = p;
863 best->n2 = n2;
864 best->r2 = r2;
865 }
866 } else if (a >= c && b < d) {
867 /* If A is below the threshold but B is above it? Update. */
868 best->p = p;
869 best->n2 = n2;
870 best->r2 = r2;
871 } else if (a >= c && b >= d) {
872 /* Both are below the limit, so pick the higher n2/(r2*r2) */
873 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
874 best->p = p;
875 best->n2 = n2;
876 best->r2 = r2;
877 }
878 }
879 /* Otherwise a < c && b >= d, do nothing */
880}
881
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200882static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
883 i915_reg_t reg)
Jesse Barnes11578552014-01-21 12:42:10 -0800884{
885 int refclk = LC_FREQ;
886 int n, p, r;
887 u32 wrpll;
888
889 wrpll = I915_READ(reg);
Daniel Vetter114fe482014-06-25 22:01:48 +0300890 switch (wrpll & WRPLL_PLL_REF_MASK) {
891 case WRPLL_PLL_SSC:
892 case WRPLL_PLL_NON_SSC:
Jesse Barnes11578552014-01-21 12:42:10 -0800893 /*
894 * We could calculate spread here, but our checking
895 * code only cares about 5% accuracy, and spread is a max of
896 * 0.5% downspread.
897 */
898 refclk = 135;
899 break;
Daniel Vetter114fe482014-06-25 22:01:48 +0300900 case WRPLL_PLL_LCPLL:
Jesse Barnes11578552014-01-21 12:42:10 -0800901 refclk = LC_FREQ;
902 break;
903 default:
904 WARN(1, "bad wrpll refclk\n");
905 return 0;
906 }
907
908 r = wrpll & WRPLL_DIVIDER_REF_MASK;
909 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
910 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
911
Jesse Barnes20f0ec12014-01-22 12:58:04 -0800912 /* Convert to KHz, p & r have a fixed point portion */
913 return (refclk * n * 100) / (p * r);
Jesse Barnes11578552014-01-21 12:42:10 -0800914}
915
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000916static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
917 uint32_t dpll)
918{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200919 i915_reg_t cfgcr1_reg, cfgcr2_reg;
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000920 uint32_t cfgcr1_val, cfgcr2_val;
921 uint32_t p0, p1, p2, dco_freq;
922
Ville Syrjälä923c12412015-09-30 17:06:43 +0300923 cfgcr1_reg = DPLL_CFGCR1(dpll);
924 cfgcr2_reg = DPLL_CFGCR2(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000925
926 cfgcr1_val = I915_READ(cfgcr1_reg);
927 cfgcr2_val = I915_READ(cfgcr2_reg);
928
929 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
930 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
931
932 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
933 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
934 else
935 p1 = 1;
936
937
938 switch (p0) {
939 case DPLL_CFGCR2_PDIV_1:
940 p0 = 1;
941 break;
942 case DPLL_CFGCR2_PDIV_2:
943 p0 = 2;
944 break;
945 case DPLL_CFGCR2_PDIV_3:
946 p0 = 3;
947 break;
948 case DPLL_CFGCR2_PDIV_7:
949 p0 = 7;
950 break;
951 }
952
953 switch (p2) {
954 case DPLL_CFGCR2_KDIV_5:
955 p2 = 5;
956 break;
957 case DPLL_CFGCR2_KDIV_2:
958 p2 = 2;
959 break;
960 case DPLL_CFGCR2_KDIV_3:
961 p2 = 3;
962 break;
963 case DPLL_CFGCR2_KDIV_1:
964 p2 = 1;
965 break;
966 }
967
968 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
969
970 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
971 1000) / 0x8000;
972
973 return dco_freq / (p0 * p1 * p2 * 5);
974}
975
Ville Syrjälä398a0172015-06-30 15:33:51 +0300976static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
977{
978 int dotclock;
979
980 if (pipe_config->has_pch_encoder)
981 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
982 &pipe_config->fdi_m_n);
983 else if (pipe_config->has_dp_encoder)
984 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
985 &pipe_config->dp_m_n);
986 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
987 dotclock = pipe_config->port_clock * 2 / 3;
988 else
989 dotclock = pipe_config->port_clock;
990
991 if (pipe_config->pixel_multiplier)
992 dotclock /= pipe_config->pixel_multiplier;
993
994 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
995}
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000996
997static void skl_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200998 struct intel_crtc_state *pipe_config)
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000999{
1000 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001001 int link_clock = 0;
1002 uint32_t dpll_ctl1, dpll;
1003
Damien Lespiau134ffa42014-11-14 17:24:34 +00001004 dpll = pipe_config->ddi_pll_sel;
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001005
1006 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1007
1008 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1009 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1010 } else {
Damien Lespiau71cd8422015-04-30 16:39:17 +01001011 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1012 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001013
1014 switch (link_clock) {
Damien Lespiau71cd8422015-04-30 16:39:17 +01001015 case DPLL_CTRL1_LINK_RATE_810:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001016 link_clock = 81000;
1017 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001018 case DPLL_CTRL1_LINK_RATE_1080:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301019 link_clock = 108000;
1020 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001021 case DPLL_CTRL1_LINK_RATE_1350:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001022 link_clock = 135000;
1023 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001024 case DPLL_CTRL1_LINK_RATE_1620:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301025 link_clock = 162000;
1026 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001027 case DPLL_CTRL1_LINK_RATE_2160:
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301028 link_clock = 216000;
1029 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +01001030 case DPLL_CTRL1_LINK_RATE_2700:
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001031 link_clock = 270000;
1032 break;
1033 default:
1034 WARN(1, "Unsupported link rate\n");
1035 break;
1036 }
1037 link_clock *= 2;
1038 }
1039
1040 pipe_config->port_clock = link_clock;
1041
Ville Syrjälä398a0172015-06-30 15:33:51 +03001042 ddi_dotclock_get(pipe_config);
Satheeshakrishna M540e7322014-11-13 14:55:16 +00001043}
1044
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001045static void hsw_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001046 struct intel_crtc_state *pipe_config)
Jesse Barnes11578552014-01-21 12:42:10 -08001047{
1048 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
Jesse Barnes11578552014-01-21 12:42:10 -08001049 int link_clock = 0;
1050 u32 val, pll;
1051
Daniel Vetter26804af2014-06-25 22:01:55 +03001052 val = pipe_config->ddi_pll_sel;
Jesse Barnes11578552014-01-21 12:42:10 -08001053 switch (val & PORT_CLK_SEL_MASK) {
1054 case PORT_CLK_SEL_LCPLL_810:
1055 link_clock = 81000;
1056 break;
1057 case PORT_CLK_SEL_LCPLL_1350:
1058 link_clock = 135000;
1059 break;
1060 case PORT_CLK_SEL_LCPLL_2700:
1061 link_clock = 270000;
1062 break;
1063 case PORT_CLK_SEL_WRPLL1:
Ville Syrjälä01403de2015-09-18 20:03:33 +03001064 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
Jesse Barnes11578552014-01-21 12:42:10 -08001065 break;
1066 case PORT_CLK_SEL_WRPLL2:
Ville Syrjälä01403de2015-09-18 20:03:33 +03001067 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
Jesse Barnes11578552014-01-21 12:42:10 -08001068 break;
1069 case PORT_CLK_SEL_SPLL:
1070 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1071 if (pll == SPLL_PLL_FREQ_810MHz)
1072 link_clock = 81000;
1073 else if (pll == SPLL_PLL_FREQ_1350MHz)
1074 link_clock = 135000;
1075 else if (pll == SPLL_PLL_FREQ_2700MHz)
1076 link_clock = 270000;
1077 else {
1078 WARN(1, "bad spll freq\n");
1079 return;
1080 }
1081 break;
1082 default:
1083 WARN(1, "bad port clock sel\n");
1084 return;
1085 }
1086
1087 pipe_config->port_clock = link_clock * 2;
1088
Ville Syrjälä398a0172015-06-30 15:33:51 +03001089 ddi_dotclock_get(pipe_config);
Jesse Barnes11578552014-01-21 12:42:10 -08001090}
1091
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301092static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1093 enum intel_dpll_id dpll)
1094{
Imre Deakaa610dc2015-06-22 23:35:52 +03001095 struct intel_shared_dpll *pll;
1096 struct intel_dpll_hw_state *state;
1097 intel_clock_t clock;
1098
1099 /* For DDI ports we always use a shared PLL. */
1100 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1101 return 0;
1102
1103 pll = &dev_priv->shared_dplls[dpll];
1104 state = &pll->config.hw_state;
1105
1106 clock.m1 = 2;
1107 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1108 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1109 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1110 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1111 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1112 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1113
1114 return chv_calc_dpll_params(100000, &clock);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301115}
1116
1117static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1118 struct intel_crtc_state *pipe_config)
1119{
1120 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1121 enum port port = intel_ddi_get_encoder_port(encoder);
1122 uint32_t dpll = port;
1123
Ville Syrjälä398a0172015-06-30 15:33:51 +03001124 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301125
Ville Syrjälä398a0172015-06-30 15:33:51 +03001126 ddi_dotclock_get(pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301127}
1128
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001129void intel_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001130 struct intel_crtc_state *pipe_config)
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001131{
Damien Lespiau22606a12014-12-12 14:26:57 +00001132 struct drm_device *dev = encoder->base.dev;
1133
1134 if (INTEL_INFO(dev)->gen <= 8)
1135 hsw_ddi_clock_get(encoder, pipe_config);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001136 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Damien Lespiau22606a12014-12-12 14:26:57 +00001137 skl_ddi_clock_get(encoder, pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301138 else if (IS_BROXTON(dev))
1139 bxt_ddi_clock_get(encoder, pipe_config);
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001140}
1141
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001142static void
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001143hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1144 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001145{
1146 uint64_t freq2k;
1147 unsigned p, n2, r2;
Damien Lespiau63582982015-05-07 18:38:46 +01001148 struct hsw_wrpll_rnp best = { 0, 0, 0 };
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001149 unsigned budget;
1150
1151 freq2k = clock / 100;
1152
Damien Lespiau63582982015-05-07 18:38:46 +01001153 budget = hsw_wrpll_get_budget_for_freq(clock);
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001154
1155 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1156 * and directly pass the LC PLL to it. */
1157 if (freq2k == 5400000) {
1158 *n2_out = 2;
1159 *p_out = 1;
1160 *r2_out = 2;
1161 return;
1162 }
1163
1164 /*
1165 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1166 * the WR PLL.
1167 *
1168 * We want R so that REF_MIN <= Ref <= REF_MAX.
1169 * Injecting R2 = 2 * R gives:
1170 * REF_MAX * r2 > LC_FREQ * 2 and
1171 * REF_MIN * r2 < LC_FREQ * 2
1172 *
1173 * Which means the desired boundaries for r2 are:
1174 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1175 *
1176 */
1177 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1178 r2 <= LC_FREQ * 2 / REF_MIN;
1179 r2++) {
1180
1181 /*
1182 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1183 *
1184 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1185 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1186 * VCO_MAX * r2 > n2 * LC_FREQ and
1187 * VCO_MIN * r2 < n2 * LC_FREQ)
1188 *
1189 * Which means the desired boundaries for n2 are:
1190 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1191 */
1192 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1193 n2 <= VCO_MAX * r2 / LC_FREQ;
1194 n2++) {
1195
1196 for (p = P_MIN; p <= P_MAX; p += P_INC)
Damien Lespiau63582982015-05-07 18:38:46 +01001197 hsw_wrpll_update_rnp(freq2k, budget,
1198 r2, n2, p, &best);
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001199 }
1200 }
1201
1202 *n2_out = best.n2;
1203 *p_out = best.p;
1204 *r2_out = best.r2;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001205}
1206
Damien Lespiau0220ab62014-07-29 18:06:22 +01001207static bool
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001208hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001209 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001210 struct intel_encoder *intel_encoder)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001211{
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001212 int clock = crtc_state->port_clock;
1213
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001214 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
Daniel Vettere0b01be2014-06-25 22:02:01 +03001215 struct intel_shared_dpll *pll;
Daniel Vetter716c2e52014-06-25 22:02:02 +03001216 uint32_t val;
Damien Lespiau1c0b85c2013-05-10 14:01:51 +01001217 unsigned p, n2, r2;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001218
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001219 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001220
Daniel Vetter114fe482014-06-25 22:01:48 +03001221 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001222 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1223 WRPLL_DIVIDER_POST(p);
1224
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03001225 memset(&crtc_state->dpll_hw_state, 0,
1226 sizeof(crtc_state->dpll_hw_state));
1227
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001228 crtc_state->dpll_hw_state.wrpll = val;
Daniel Vetter716c2e52014-06-25 22:02:02 +03001229
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001230 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
Daniel Vetter716c2e52014-06-25 22:02:02 +03001231 if (pll == NULL) {
1232 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1233 pipe_name(intel_crtc->pipe));
Paulo Zanoni06940012013-10-30 18:27:43 -02001234 return false;
1235 }
1236
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001237 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
Maarten Lankhorst00490c22015-11-16 14:42:12 +01001238 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1239 struct drm_atomic_state *state = crtc_state->base.state;
1240 struct intel_shared_dpll_config *spll =
1241 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1242
1243 if (spll->crtc_mask &&
1244 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1245 return false;
1246
1247 crtc_state->shared_dpll = DPLL_ID_SPLL;
1248 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1249 spll->crtc_mask |= 1 << intel_crtc->pipe;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001250 }
1251
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001252 return true;
1253}
1254
Damien Lespiaudc253812015-06-25 16:15:06 +01001255struct skl_wrpll_context {
1256 uint64_t min_deviation; /* current minimal deviation */
1257 uint64_t central_freq; /* chosen central freq */
1258 uint64_t dco_freq; /* chosen dco freq */
1259 unsigned int p; /* chosen divider */
1260};
1261
1262static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1263{
1264 memset(ctx, 0, sizeof(*ctx));
1265
1266 ctx->min_deviation = U64_MAX;
1267}
1268
1269/* DCO freq must be within +1%/-6% of the DCO central freq */
1270#define SKL_DCO_MAX_PDEVIATION 100
1271#define SKL_DCO_MAX_NDEVIATION 600
1272
1273static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1274 uint64_t central_freq,
1275 uint64_t dco_freq,
1276 unsigned int divider)
1277{
1278 uint64_t deviation;
1279
1280 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1281 central_freq);
1282
1283 /* positive deviation */
1284 if (dco_freq >= central_freq) {
1285 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1286 deviation < ctx->min_deviation) {
1287 ctx->min_deviation = deviation;
1288 ctx->central_freq = central_freq;
1289 ctx->dco_freq = dco_freq;
1290 ctx->p = divider;
1291 }
1292 /* negative deviation */
1293 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1294 deviation < ctx->min_deviation) {
1295 ctx->min_deviation = deviation;
1296 ctx->central_freq = central_freq;
1297 ctx->dco_freq = dco_freq;
1298 ctx->p = divider;
1299 }
Damien Lespiaudc253812015-06-25 16:15:06 +01001300}
1301
1302static void skl_wrpll_get_multipliers(unsigned int p,
1303 unsigned int *p0 /* out */,
1304 unsigned int *p1 /* out */,
1305 unsigned int *p2 /* out */)
1306{
1307 /* even dividers */
1308 if (p % 2 == 0) {
1309 unsigned int half = p / 2;
1310
1311 if (half == 1 || half == 2 || half == 3 || half == 5) {
1312 *p0 = 2;
1313 *p1 = 1;
1314 *p2 = half;
1315 } else if (half % 2 == 0) {
1316 *p0 = 2;
1317 *p1 = half / 2;
1318 *p2 = 2;
1319 } else if (half % 3 == 0) {
1320 *p0 = 3;
1321 *p1 = half / 3;
1322 *p2 = 2;
1323 } else if (half % 7 == 0) {
1324 *p0 = 7;
1325 *p1 = half / 7;
1326 *p2 = 2;
1327 }
1328 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1329 *p0 = 3;
1330 *p1 = 1;
1331 *p2 = p / 3;
1332 } else if (p == 5 || p == 7) {
1333 *p0 = p;
1334 *p1 = 1;
1335 *p2 = 1;
1336 } else if (p == 15) {
1337 *p0 = 3;
1338 *p1 = 1;
1339 *p2 = 5;
1340 } else if (p == 21) {
1341 *p0 = 7;
1342 *p1 = 1;
1343 *p2 = 3;
1344 } else if (p == 35) {
1345 *p0 = 7;
1346 *p1 = 1;
1347 *p2 = 5;
1348 }
1349}
1350
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001351struct skl_wrpll_params {
1352 uint32_t dco_fraction;
1353 uint32_t dco_integer;
1354 uint32_t qdiv_ratio;
1355 uint32_t qdiv_mode;
1356 uint32_t kdiv;
1357 uint32_t pdiv;
1358 uint32_t central_freq;
1359};
1360
Damien Lespiau76516fb2015-05-07 18:38:42 +01001361static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1362 uint64_t afe_clock,
1363 uint64_t central_freq,
1364 uint32_t p0, uint32_t p1, uint32_t p2)
1365{
1366 uint64_t dco_freq;
1367
Damien Lespiau76516fb2015-05-07 18:38:42 +01001368 switch (central_freq) {
1369 case 9600000000ULL:
1370 params->central_freq = 0;
1371 break;
1372 case 9000000000ULL:
1373 params->central_freq = 1;
1374 break;
1375 case 8400000000ULL:
1376 params->central_freq = 3;
1377 }
1378
1379 switch (p0) {
1380 case 1:
1381 params->pdiv = 0;
1382 break;
1383 case 2:
1384 params->pdiv = 1;
1385 break;
1386 case 3:
1387 params->pdiv = 2;
1388 break;
1389 case 7:
1390 params->pdiv = 4;
1391 break;
1392 default:
1393 WARN(1, "Incorrect PDiv\n");
1394 }
1395
1396 switch (p2) {
1397 case 5:
1398 params->kdiv = 0;
1399 break;
1400 case 2:
1401 params->kdiv = 1;
1402 break;
1403 case 3:
1404 params->kdiv = 2;
1405 break;
1406 case 1:
1407 params->kdiv = 3;
1408 break;
1409 default:
1410 WARN(1, "Incorrect KDiv\n");
1411 }
1412
1413 params->qdiv_ratio = p1;
1414 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1415
1416 dco_freq = p0 * p1 * p2 * afe_clock;
1417
1418 /*
1419 * Intermediate values are in Hz.
1420 * Divide by MHz to match bsepc
1421 */
Damien Lespiau30a78622015-05-07 18:38:43 +01001422 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
Damien Lespiau76516fb2015-05-07 18:38:42 +01001423 params->dco_fraction =
Damien Lespiau30a78622015-05-07 18:38:43 +01001424 div_u64((div_u64(dco_freq, 24) -
1425 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
Damien Lespiau76516fb2015-05-07 18:38:42 +01001426}
1427
Damien Lespiau318bd822015-05-07 18:38:40 +01001428static bool
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001429skl_ddi_calculate_wrpll(int clock /* in Hz */,
1430 struct skl_wrpll_params *wrpll_params)
1431{
1432 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
Damien Lespiau21318cc2014-11-14 14:20:27 +00001433 uint64_t dco_central_freq[3] = {8400000000ULL,
1434 9000000000ULL,
1435 9600000000ULL};
Damien Lespiaudc253812015-06-25 16:15:06 +01001436 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1437 24, 28, 30, 32, 36, 40, 42, 44,
1438 48, 52, 54, 56, 60, 64, 66, 68,
1439 70, 72, 76, 78, 80, 84, 88, 90,
1440 92, 96, 98 };
1441 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1442 static const struct {
1443 const int *list;
1444 int n_dividers;
1445 } dividers[] = {
1446 { even_dividers, ARRAY_SIZE(even_dividers) },
1447 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1448 };
1449 struct skl_wrpll_context ctx;
1450 unsigned int dco, d, i;
1451 unsigned int p0, p1, p2;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001452
Damien Lespiaudc253812015-06-25 16:15:06 +01001453 skl_wrpll_context_init(&ctx);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001454
Damien Lespiaudc253812015-06-25 16:15:06 +01001455 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1456 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1457 for (i = 0; i < dividers[d].n_dividers; i++) {
1458 unsigned int p = dividers[d].list[i];
1459 uint64_t dco_freq = p * afe_clock;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001460
Damien Lespiaudc253812015-06-25 16:15:06 +01001461 skl_wrpll_try_divider(&ctx,
1462 dco_central_freq[dco],
1463 dco_freq,
1464 p);
Damien Lespiaue7ad9872015-06-26 18:34:29 +01001465 /*
1466 * Skip the remaining dividers if we're sure to
1467 * have found the definitive divider, we can't
1468 * improve a 0 deviation.
1469 */
1470 if (ctx.min_deviation == 0)
1471 goto skip_remaining_dividers;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001472 }
1473 }
Damien Lespiau267db662015-06-25 16:19:24 +01001474
Damien Lespiaue7ad9872015-06-26 18:34:29 +01001475skip_remaining_dividers:
Damien Lespiau267db662015-06-25 16:19:24 +01001476 /*
1477 * If a solution is found with an even divider, prefer
1478 * this one.
1479 */
1480 if (d == 0 && ctx.p)
1481 break;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001482 }
1483
Damien Lespiaudc253812015-06-25 16:15:06 +01001484 if (!ctx.p) {
1485 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
Damien Lespiau318bd822015-05-07 18:38:40 +01001486 return false;
Damien Lespiaudc253812015-06-25 16:15:06 +01001487 }
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001488
Damien Lespiaudc253812015-06-25 16:15:06 +01001489 /*
1490 * gcc incorrectly analyses that these can be used without being
1491 * initialized. To be fair, it's hard to guess.
1492 */
1493 p0 = p1 = p2 = 0;
1494 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1495 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1496 p0, p1, p2);
Damien Lespiau9c236752015-05-07 18:38:41 +01001497
Damien Lespiau318bd822015-05-07 18:38:40 +01001498 return true;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001499}
1500
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001501static bool
1502skl_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001503 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001504 struct intel_encoder *intel_encoder)
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001505{
1506 struct intel_shared_dpll *pll;
1507 uint32_t ctrl1, cfgcr1, cfgcr2;
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001508 int clock = crtc_state->port_clock;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001509
1510 /*
1511 * See comment in intel_dpll_hw_state to understand why we always use 0
1512 * as the DPLL id in this function.
1513 */
1514
1515 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1516
1517 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1518 struct skl_wrpll_params wrpll_params = { 0, };
1519
1520 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1521
Damien Lespiau318bd822015-05-07 18:38:40 +01001522 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1523 return false;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001524
1525 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1526 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1527 wrpll_params.dco_integer;
1528
1529 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1530 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1531 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1532 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1533 wrpll_params.central_freq;
Lyude78385cb2016-02-02 10:49:43 -05001534 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1535 intel_encoder->type == INTEL_OUTPUT_DP_MST) {
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001536 switch (crtc_state->port_clock / 2) {
1537 case 81000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001538 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001539 break;
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001540 case 135000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001541 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001542 break;
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001543 case 270000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001544 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001545 break;
1546 }
1547
1548 cfgcr1 = cfgcr2 = 0;
1549 } else /* eDP */
1550 return true;
1551
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03001552 memset(&crtc_state->dpll_hw_state, 0,
1553 sizeof(crtc_state->dpll_hw_state));
1554
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001555 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1556 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1557 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001558
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001559 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001560 if (pll == NULL) {
1561 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1562 pipe_name(intel_crtc->pipe));
1563 return false;
1564 }
1565
1566 /* shared DPLL id 0 is DPLL 1 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001567 crtc_state->ddi_pll_sel = pll->id + 1;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001568
1569 return true;
1570}
Damien Lespiau0220ab62014-07-29 18:06:22 +01001571
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301572/* bxt clock parameters */
1573struct bxt_clk_div {
Sonika Jindal64987fc2015-05-26 17:50:13 +05301574 int clock;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301575 uint32_t p1;
1576 uint32_t p2;
1577 uint32_t m2_int;
1578 uint32_t m2_frac;
1579 bool m2_frac_en;
1580 uint32_t n;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301581};
1582
1583/* pre-calculated values for DP linkrates */
Sonika Jindal64987fc2015-05-26 17:50:13 +05301584static const struct bxt_clk_div bxt_dp_clk_val[] = {
1585 {162000, 4, 2, 32, 1677722, 1, 1},
1586 {270000, 4, 1, 27, 0, 0, 1},
1587 {540000, 2, 1, 27, 0, 0, 1},
1588 {216000, 3, 2, 32, 1677722, 1, 1},
1589 {243000, 4, 1, 24, 1258291, 1, 1},
1590 {324000, 4, 1, 32, 1677722, 1, 1},
1591 {432000, 3, 1, 32, 1677722, 1, 1}
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301592};
1593
1594static bool
1595bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1596 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001597 struct intel_encoder *intel_encoder)
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301598{
1599 struct intel_shared_dpll *pll;
1600 struct bxt_clk_div clk_div = {0};
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301601 int vco = 0;
1602 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
Vandana Kannane6292552015-07-01 17:02:57 +05301603 uint32_t lanestagger;
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001604 int clock = crtc_state->port_clock;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301605
1606 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1607 intel_clock_t best_clock;
1608
1609 /* Calculate HDMI div */
1610 /*
1611 * FIXME: tie the following calculation into
1612 * i9xx_crtc_compute_clock
1613 */
1614 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1615 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1616 clock, pipe_name(intel_crtc->pipe));
1617 return false;
1618 }
1619
1620 clk_div.p1 = best_clock.p1;
1621 clk_div.p2 = best_clock.p2;
1622 WARN_ON(best_clock.m1 != 2);
1623 clk_div.n = best_clock.n;
1624 clk_div.m2_int = best_clock.m2 >> 22;
1625 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1626 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1627
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301628 vco = best_clock.vco;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301629 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1630 intel_encoder->type == INTEL_OUTPUT_EDP) {
Sonika Jindal64987fc2015-05-26 17:50:13 +05301631 int i;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301632
Sonika Jindal64987fc2015-05-26 17:50:13 +05301633 clk_div = bxt_dp_clk_val[0];
1634 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1635 if (bxt_dp_clk_val[i].clock == clock) {
1636 clk_div = bxt_dp_clk_val[i];
1637 break;
1638 }
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301639 }
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301640 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1641 }
1642
Vandana Kannane6292552015-07-01 17:02:57 +05301643 if (vco >= 6200000 && vco <= 6700000) {
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301644 prop_coef = 4;
1645 int_coef = 9;
1646 gain_ctl = 3;
1647 targ_cnt = 8;
1648 } else if ((vco > 5400000 && vco < 6200000) ||
1649 (vco >= 4800000 && vco < 5400000)) {
1650 prop_coef = 5;
1651 int_coef = 11;
1652 gain_ctl = 3;
1653 targ_cnt = 9;
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301654 } else if (vco == 5400000) {
1655 prop_coef = 3;
1656 int_coef = 8;
1657 gain_ctl = 1;
1658 targ_cnt = 9;
1659 } else {
1660 DRM_ERROR("Invalid VCO\n");
1661 return false;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301662 }
1663
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03001664 memset(&crtc_state->dpll_hw_state, 0,
1665 sizeof(crtc_state->dpll_hw_state));
1666
Vandana Kannane0681e32015-05-13 12:20:35 +05301667 if (clock > 270000)
1668 lanestagger = 0x18;
1669 else if (clock > 135000)
1670 lanestagger = 0x0d;
1671 else if (clock > 67000)
1672 lanestagger = 0x07;
1673 else if (clock > 33000)
1674 lanestagger = 0x04;
1675 else
1676 lanestagger = 0x02;
1677
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301678 crtc_state->dpll_hw_state.ebb0 =
1679 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1680 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1681 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1682 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1683
1684 if (clk_div.m2_frac_en)
1685 crtc_state->dpll_hw_state.pll3 =
1686 PORT_PLL_M2_FRAC_ENABLE;
1687
1688 crtc_state->dpll_hw_state.pll6 =
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301689 prop_coef | PORT_PLL_INT_COEFF(int_coef);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301690 crtc_state->dpll_hw_state.pll6 |=
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301691 PORT_PLL_GAIN_CTL(gain_ctl);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301692
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05301693 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1694
Imre Deak05712c12015-06-18 17:25:54 +03001695 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1696
Vandana Kannane6292552015-07-01 17:02:57 +05301697 crtc_state->dpll_hw_state.pll10 =
1698 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1699 | PORT_PLL_DCO_AMP_OVR_EN_H;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301700
Imre Deak05712c12015-06-18 17:25:54 +03001701 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1702
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301703 crtc_state->dpll_hw_state.pcsdw12 =
Vandana Kannane0681e32015-05-13 12:20:35 +05301704 LANESTAGGER_STRAP_OVRD | lanestagger;
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301705
1706 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1707 if (pll == NULL) {
1708 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1709 pipe_name(intel_crtc->pipe));
1710 return false;
1711 }
1712
1713 /* shared DPLL id 0 is DPLL A */
1714 crtc_state->ddi_pll_sel = pll->id;
1715
1716 return true;
1717}
1718
Damien Lespiau0220ab62014-07-29 18:06:22 +01001719/*
1720 * Tries to find a *shared* PLL for the CRTC and store it in
1721 * intel_crtc->ddi_pll_sel.
1722 *
1723 * For private DPLLs, compute_config() should do the selection for us. This
1724 * function should be folded into compute_config() eventually.
1725 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001726bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1727 struct intel_crtc_state *crtc_state)
Damien Lespiau0220ab62014-07-29 18:06:22 +01001728{
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001729 struct drm_device *dev = intel_crtc->base.dev;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02001730 struct intel_encoder *intel_encoder =
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +02001731 intel_ddi_get_crtc_new_encoder(crtc_state);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001732
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001733 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001734 return skl_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001735 intel_encoder);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301736 else if (IS_BROXTON(dev))
1737 return bxt_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001738 intel_encoder);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001739 else
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001740 return hsw_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001741 intel_encoder);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001742}
1743
Paulo Zanonidae84792012-10-15 15:51:30 -03001744void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1745{
1746 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001749 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonidae84792012-10-15 15:51:30 -03001750 int type = intel_encoder->type;
1751 uint32_t temp;
1752
Dave Airlie0e32b392014-05-02 14:02:48 +10001753 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
Paulo Zanonic9809792012-10-23 18:30:00 -02001754 temp = TRANS_MSA_SYNC_CLK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001755 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidae84792012-10-15 15:51:30 -03001756 case 18:
Paulo Zanonic9809792012-10-23 18:30:00 -02001757 temp |= TRANS_MSA_6_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001758 break;
1759 case 24:
Paulo Zanonic9809792012-10-23 18:30:00 -02001760 temp |= TRANS_MSA_8_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001761 break;
1762 case 30:
Paulo Zanonic9809792012-10-23 18:30:00 -02001763 temp |= TRANS_MSA_10_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001764 break;
1765 case 36:
Paulo Zanonic9809792012-10-23 18:30:00 -02001766 temp |= TRANS_MSA_12_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001767 break;
1768 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001769 BUG();
Paulo Zanonidae84792012-10-15 15:51:30 -03001770 }
Paulo Zanonic9809792012-10-23 18:30:00 -02001771 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
Paulo Zanonidae84792012-10-15 15:51:30 -03001772 }
1773}
1774
Dave Airlie0e32b392014-05-02 14:02:48 +10001775void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1776{
1777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1778 struct drm_device *dev = crtc->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001780 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Dave Airlie0e32b392014-05-02 14:02:48 +10001781 uint32_t temp;
1782 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1783 if (state == true)
1784 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1785 else
1786 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1787 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1788}
1789
Damien Lespiau8228c252013-03-07 15:30:27 +00001790void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001791{
1792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Paulo Zanoni7739c332012-10-15 15:51:29 -03001794 struct drm_encoder *encoder = &intel_encoder->base;
Paulo Zanonic7670b12013-11-02 21:07:37 -07001795 struct drm_device *dev = crtc->dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001797 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001798 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001799 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Paulo Zanoni7739c332012-10-15 15:51:29 -03001800 int type = intel_encoder->type;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001801 uint32_t temp;
1802
Paulo Zanoniad80a812012-10-24 16:06:19 -02001803 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1804 temp = TRANS_DDI_FUNC_ENABLE;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001805 temp |= TRANS_DDI_SELECT_PORT(port);
Paulo Zanonidfcef252012-08-08 14:15:29 -03001806
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001807 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidfcef252012-08-08 14:15:29 -03001808 case 18:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001809 temp |= TRANS_DDI_BPC_6;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001810 break;
1811 case 24:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001812 temp |= TRANS_DDI_BPC_8;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001813 break;
1814 case 30:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001815 temp |= TRANS_DDI_BPC_10;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001816 break;
1817 case 36:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001818 temp |= TRANS_DDI_BPC_12;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001819 break;
1820 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001821 BUG();
Paulo Zanonidfcef252012-08-08 14:15:29 -03001822 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001823
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001824 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001825 temp |= TRANS_DDI_PVSYNC;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001826 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001827 temp |= TRANS_DDI_PHSYNC;
Paulo Zanonif63eb7c42012-08-08 14:15:28 -03001828
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001829 if (cpu_transcoder == TRANSCODER_EDP) {
1830 switch (pipe) {
1831 case PIPE_A:
Paulo Zanonic7670b12013-11-02 21:07:37 -07001832 /* On Haswell, can only use the always-on power well for
1833 * eDP when not using the panel fitter, and when not
1834 * using motion blur mitigation (which we don't
1835 * support). */
Daniel Vetterfabf6e52014-05-29 14:10:22 +02001836 if (IS_HASWELL(dev) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001837 (intel_crtc->config->pch_pfit.enabled ||
1838 intel_crtc->config->pch_pfit.force_thru))
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02001839 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1840 else
1841 temp |= TRANS_DDI_EDP_INPUT_A_ON;
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001842 break;
1843 case PIPE_B:
1844 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1845 break;
1846 case PIPE_C:
1847 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1848 break;
1849 default:
1850 BUG();
1851 break;
1852 }
1853 }
1854
Paulo Zanoni7739c332012-10-15 15:51:29 -03001855 if (type == INTEL_OUTPUT_HDMI) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001856 if (intel_crtc->config->has_hdmi_sink)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001857 temp |= TRANS_DDI_MODE_SELECT_HDMI;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001858 else
Paulo Zanoniad80a812012-10-24 16:06:19 -02001859 temp |= TRANS_DDI_MODE_SELECT_DVI;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001860
Paulo Zanoni7739c332012-10-15 15:51:29 -03001861 } else if (type == INTEL_OUTPUT_ANALOG) {
Paulo Zanoniad80a812012-10-24 16:06:19 -02001862 temp |= TRANS_DDI_MODE_SELECT_FDI;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001863 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
Paulo Zanoni7739c332012-10-15 15:51:29 -03001864
1865 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1866 type == INTEL_OUTPUT_EDP) {
1867 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1868
Dave Airlie0e32b392014-05-02 14:02:48 +10001869 if (intel_dp->is_mst) {
1870 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1871 } else
1872 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1873
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001874 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Dave Airlie0e32b392014-05-02 14:02:48 +10001875 } else if (type == INTEL_OUTPUT_DP_MST) {
1876 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1877
1878 if (intel_dp->is_mst) {
1879 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1880 } else
1881 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
Paulo Zanoni7739c332012-10-15 15:51:29 -03001882
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001883 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001884 } else {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001885 WARN(1, "Invalid encoder type %d for pipe %c\n",
1886 intel_encoder->type, pipe_name(pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001887 }
1888
Paulo Zanoniad80a812012-10-24 16:06:19 -02001889 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001890}
1891
Paulo Zanoniad80a812012-10-24 16:06:19 -02001892void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1893 enum transcoder cpu_transcoder)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001894{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001895 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001896 uint32_t val = I915_READ(reg);
1897
Dave Airlie0e32b392014-05-02 14:02:48 +10001898 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001899 val |= TRANS_DDI_PORT_NONE;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001900 I915_WRITE(reg, val);
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001901}
1902
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001903bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1904{
1905 struct drm_device *dev = intel_connector->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct intel_encoder *intel_encoder = intel_connector->encoder;
1908 int type = intel_connector->base.connector_type;
1909 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1910 enum pipe pipe = 0;
1911 enum transcoder cpu_transcoder;
Paulo Zanoni882244a2014-04-01 14:55:12 -03001912 enum intel_display_power_domain power_domain;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001913 uint32_t tmp;
1914
Paulo Zanoni882244a2014-04-01 14:55:12 -03001915 power_domain = intel_display_port_power_domain(intel_encoder);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001916 if (!intel_display_power_is_enabled(dev_priv, power_domain))
Paulo Zanoni882244a2014-04-01 14:55:12 -03001917 return false;
1918
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001919 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1920 return false;
1921
1922 if (port == PORT_A)
1923 cpu_transcoder = TRANSCODER_EDP;
1924 else
Daniel Vetter1a240d42012-11-29 22:18:51 +01001925 cpu_transcoder = (enum transcoder) pipe;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001926
1927 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1928
1929 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1930 case TRANS_DDI_MODE_SELECT_HDMI:
1931 case TRANS_DDI_MODE_SELECT_DVI:
1932 return (type == DRM_MODE_CONNECTOR_HDMIA);
1933
1934 case TRANS_DDI_MODE_SELECT_DP_SST:
1935 if (type == DRM_MODE_CONNECTOR_eDP)
1936 return true;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001937 return (type == DRM_MODE_CONNECTOR_DisplayPort);
Dave Airlie0e32b392014-05-02 14:02:48 +10001938 case TRANS_DDI_MODE_SELECT_DP_MST:
1939 /* if the transcoder is in MST state then
1940 * connector isn't connected */
1941 return false;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001942
1943 case TRANS_DDI_MODE_SELECT_FDI:
1944 return (type == DRM_MODE_CONNECTOR_VGA);
1945
1946 default:
1947 return false;
1948 }
1949}
1950
Daniel Vetter85234cd2012-07-02 13:27:29 +02001951bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1952 enum pipe *pipe)
1953{
1954 struct drm_device *dev = encoder->base.dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001956 enum port port = intel_ddi_get_encoder_port(encoder);
Imre Deak6d129be2014-03-05 16:20:54 +02001957 enum intel_display_power_domain power_domain;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001958 u32 tmp;
1959 int i;
1960
Imre Deak6d129be2014-03-05 16:20:54 +02001961 power_domain = intel_display_port_power_domain(encoder);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001962 if (!intel_display_power_is_enabled(dev_priv, power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +02001963 return false;
1964
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001965 tmp = I915_READ(DDI_BUF_CTL(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001966
1967 if (!(tmp & DDI_BUF_CTL_ENABLE))
1968 return false;
1969
Paulo Zanoniad80a812012-10-24 16:06:19 -02001970 if (port == PORT_A) {
1971 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001972
Paulo Zanoniad80a812012-10-24 16:06:19 -02001973 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1974 case TRANS_DDI_EDP_INPUT_A_ON:
1975 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1976 *pipe = PIPE_A;
1977 break;
1978 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1979 *pipe = PIPE_B;
1980 break;
1981 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1982 *pipe = PIPE_C;
1983 break;
1984 }
1985
1986 return true;
1987 } else {
1988 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1990
1991 if ((tmp & TRANS_DDI_PORT_MASK)
1992 == TRANS_DDI_SELECT_PORT(port)) {
Dave Airlie0e32b392014-05-02 14:02:48 +10001993 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1994 return false;
1995
Paulo Zanoniad80a812012-10-24 16:06:19 -02001996 *pipe = i;
1997 return true;
1998 }
Daniel Vetter85234cd2012-07-02 13:27:29 +02001999 }
2000 }
2001
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002002 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02002003
Jesse Barnes22f9fe52013-04-02 10:03:55 -07002004 return false;
Daniel Vetter85234cd2012-07-02 13:27:29 +02002005}
2006
Paulo Zanonifc914632012-10-05 12:05:54 -03002007void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2008{
2009 struct drm_crtc *crtc = &intel_crtc->base;
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05302010 struct drm_device *dev = crtc->dev;
2011 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonifc914632012-10-05 12:05:54 -03002012 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2013 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002014 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03002015
Paulo Zanonibb523fc2012-10-23 18:29:56 -02002016 if (cpu_transcoder != TRANSCODER_EDP)
2017 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2018 TRANS_CLK_SEL_PORT(port));
Paulo Zanonifc914632012-10-05 12:05:54 -03002019}
2020
2021void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2022{
2023 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002024 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03002025
Paulo Zanonibb523fc2012-10-23 18:29:56 -02002026 if (cpu_transcoder != TRANSCODER_EDP)
2027 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2028 TRANS_CLK_SEL_DISABLED);
Paulo Zanonifc914632012-10-05 12:05:54 -03002029}
2030
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002031static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2032 u32 level, enum port port, int type)
David Weinehallf8896f52015-06-25 11:11:03 +03002033{
David Weinehallf8896f52015-06-25 11:11:03 +03002034 const struct ddi_buf_trans *ddi_translations;
2035 uint8_t iboost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002036 uint8_t dp_iboost, hdmi_iboost;
David Weinehallf8896f52015-06-25 11:11:03 +03002037 int n_entries;
2038 u32 reg;
2039
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002040 /* VBT may override standard boost values */
2041 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2042 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2043
David Weinehallf8896f52015-06-25 11:11:03 +03002044 if (type == INTEL_OUTPUT_DISPLAYPORT) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002045 if (dp_iboost) {
2046 iboost = dp_iboost;
2047 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002048 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02002049 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002050 }
David Weinehallf8896f52015-06-25 11:11:03 +03002051 } else if (type == INTEL_OUTPUT_EDP) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002052 if (dp_iboost) {
2053 iboost = dp_iboost;
2054 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002055 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
Ville Syrjälä10afa0b2015-12-08 19:59:43 +02002056
2057 if (WARN_ON(port != PORT_A &&
2058 port != PORT_E && n_entries > 9))
2059 n_entries = 9;
2060
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02002061 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002062 }
David Weinehallf8896f52015-06-25 11:11:03 +03002063 } else if (type == INTEL_OUTPUT_HDMI) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002064 if (hdmi_iboost) {
2065 iboost = hdmi_iboost;
2066 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002067 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02002068 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03002069 }
David Weinehallf8896f52015-06-25 11:11:03 +03002070 } else {
2071 return;
2072 }
2073
2074 /* Make sure that the requested I_boost is valid */
2075 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2076 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2077 return;
2078 }
2079
2080 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2081 reg &= ~BALANCE_LEG_MASK(port);
2082 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2083
2084 if (iboost)
2085 reg |= iboost << BALANCE_LEG_SHIFT(port);
2086 else
2087 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2088
2089 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2090}
2091
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002092static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2093 u32 level, enum port port, int type)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302094{
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302095 const struct bxt_ddi_buf_trans *ddi_translations;
2096 u32 n_entries, i;
2097 uint32_t val;
2098
Sonika Jindald9d70002015-09-24 10:24:56 +05302099 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2100 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2101 ddi_translations = bxt_ddi_translations_edp;
2102 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2103 || type == INTEL_OUTPUT_EDP) {
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302104 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2105 ddi_translations = bxt_ddi_translations_dp;
2106 } else if (type == INTEL_OUTPUT_HDMI) {
2107 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2108 ddi_translations = bxt_ddi_translations_hdmi;
2109 } else {
2110 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2111 type);
2112 return;
2113 }
2114
2115 /* Check if default value has to be used */
2116 if (level >= n_entries ||
2117 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2118 for (i = 0; i < n_entries; i++) {
2119 if (ddi_translations[i].default_index) {
2120 level = i;
2121 break;
2122 }
2123 }
2124 }
2125
2126 /*
2127 * While we write to the group register to program all lanes at once we
2128 * can read only lane registers and we pick lanes 0/1 for that.
2129 */
2130 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2131 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2132 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2133
2134 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2135 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2136 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2137 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2138 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2139
2140 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
Sonika Jindal9c58a042015-09-24 10:22:54 +05302141 val &= ~SCALE_DCOMP_METHOD;
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302142 if (ddi_translations[level].enable)
Sonika Jindal9c58a042015-09-24 10:22:54 +05302143 val |= SCALE_DCOMP_METHOD;
2144
2145 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2146 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2147
Vandana Kannan96fb9f92014-11-18 15:45:27 +05302148 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2149
2150 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2151 val &= ~DE_EMPHASIS;
2152 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2153 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2154
2155 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2156 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2157 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2158}
2159
David Weinehallf8896f52015-06-25 11:11:03 +03002160static uint32_t translate_signal_level(int signal_levels)
2161{
2162 uint32_t level;
2163
2164 switch (signal_levels) {
2165 default:
2166 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2167 signal_levels);
2168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2169 level = 0;
2170 break;
2171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2172 level = 1;
2173 break;
2174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2175 level = 2;
2176 break;
2177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2178 level = 3;
2179 break;
2180
2181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2182 level = 4;
2183 break;
2184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2185 level = 5;
2186 break;
2187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2188 level = 6;
2189 break;
2190
2191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2192 level = 7;
2193 break;
2194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2195 level = 8;
2196 break;
2197
2198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2199 level = 9;
2200 break;
2201 }
2202
2203 return level;
2204}
2205
2206uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2207{
2208 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002209 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
David Weinehallf8896f52015-06-25 11:11:03 +03002210 struct intel_encoder *encoder = &dport->base;
2211 uint8_t train_set = intel_dp->train_set[0];
2212 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2213 DP_TRAIN_PRE_EMPHASIS_MASK);
2214 enum port port = dport->port;
2215 uint32_t level;
2216
2217 level = translate_signal_level(signal_levels);
2218
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02002219 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2220 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2221 else if (IS_BROXTON(dev_priv))
2222 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
David Weinehallf8896f52015-06-25 11:11:03 +03002223
2224 return DDI_BUF_TRANS_SELECT(level);
2225}
2226
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002227void intel_ddi_clk_select(struct intel_encoder *encoder,
2228 const struct intel_crtc_state *pipe_config)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002229{
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2231 enum port port = intel_ddi_get_encoder_port(encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02002232
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002233 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2234 uint32_t dpll = pipe_config->ddi_pll_sel;
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002235 uint32_t val;
2236
Damien Lespiau5416d872014-11-14 17:24:33 +00002237 /*
2238 * DPLL0 is used for eDP and is the only "private" DPLL (as
2239 * opposed to shared) on SKL
2240 */
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002241 if (encoder->type == INTEL_OUTPUT_EDP) {
Damien Lespiau5416d872014-11-14 17:24:33 +00002242 WARN_ON(dpll != SKL_DPLL0);
2243
2244 val = I915_READ(DPLL_CTRL1);
2245
2246 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2247 DPLL_CTRL1_SSC(dpll) |
Damien Lespiau71cd8422015-04-30 16:39:17 +01002248 DPLL_CTRL1_LINK_RATE_MASK(dpll));
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002249 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
Damien Lespiau5416d872014-11-14 17:24:33 +00002250
2251 I915_WRITE(DPLL_CTRL1, val);
2252 POSTING_READ(DPLL_CTRL1);
2253 }
2254
2255 /* DDI -> PLL mapping */
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002256 val = I915_READ(DPLL_CTRL2);
2257
2258 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2259 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2260 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2261 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2262
2263 I915_WRITE(DPLL_CTRL2, val);
Damien Lespiau5416d872014-11-14 17:24:33 +00002264
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002265 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2266 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2267 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002268 }
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002269}
2270
2271static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2272{
2273 struct drm_encoder *encoder = &intel_encoder->base;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02002274 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002275 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2276 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2277 int type = intel_encoder->type;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02002278
2279 intel_prepare_ddi_buffer(intel_encoder);
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03002280
2281 if (type == INTEL_OUTPUT_EDP) {
2282 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2283 intel_edp_panel_on(intel_dp);
2284 }
2285
2286 intel_ddi_clk_select(intel_encoder, crtc->config);
Paulo Zanonic19b0662012-10-15 15:51:41 -03002287
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02002288 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
Paulo Zanonic19b0662012-10-15 15:51:41 -03002289 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Daniel Vetter30cf6db2014-04-24 23:54:58 +02002290
Ville Syrjälä901c2da2015-08-17 18:05:12 +03002291 intel_dp_set_link_params(intel_dp, crtc->config);
2292
Dave Airlie44905a272014-05-02 13:36:43 +10002293 intel_ddi_init_dp_buf_reg(intel_encoder);
Paulo Zanonic19b0662012-10-15 15:51:41 -03002294
2295 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2296 intel_dp_start_link_train(intel_dp);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02002297 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
Imre Deak3ab9c632013-05-03 12:57:41 +03002298 intel_dp_stop_link_train(intel_dp);
Daniel Vetter30cf6db2014-04-24 23:54:58 +02002299 } else if (type == INTEL_OUTPUT_HDMI) {
2300 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2301
2302 intel_hdmi->set_infoframes(encoder,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002303 crtc->config->has_hdmi_sink,
2304 &crtc->config->base.adjusted_mode);
Paulo Zanonic19b0662012-10-15 15:51:41 -03002305 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002306}
2307
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002308static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002309{
2310 struct drm_encoder *encoder = &intel_encoder->base;
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002311 struct drm_device *dev = encoder->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002313 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02002314 int type = intel_encoder->type;
Paulo Zanoni2886e932012-10-05 12:06:00 -03002315 uint32_t val;
Paulo Zanonia836bdf2012-10-15 15:51:32 -03002316 bool wait = false;
Paulo Zanoni2886e932012-10-05 12:06:00 -03002317
2318 val = I915_READ(DDI_BUF_CTL(port));
2319 if (val & DDI_BUF_CTL_ENABLE) {
2320 val &= ~DDI_BUF_CTL_ENABLE;
2321 I915_WRITE(DDI_BUF_CTL(port), val);
Paulo Zanonia836bdf2012-10-15 15:51:32 -03002322 wait = true;
Paulo Zanoni2886e932012-10-05 12:06:00 -03002323 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002324
Paulo Zanonia836bdf2012-10-15 15:51:32 -03002325 val = I915_READ(DP_TP_CTL(port));
2326 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2327 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2328 I915_WRITE(DP_TP_CTL(port), val);
2329
2330 if (wait)
2331 intel_wait_ddi_buf_idle(dev_priv, port);
2332
Jani Nikula76bb80e2013-11-15 15:29:57 +02002333 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02002334 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jani Nikula76bb80e2013-11-15 15:29:57 +02002335 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Jani Nikula24f3e092014-03-17 16:43:36 +02002336 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01002337 intel_edp_panel_off(intel_dp);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02002338 }
2339
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002340 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002341 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2342 DPLL_CTRL2_DDI_CLK_OFF(port)));
Satheeshakrishna M1ab23382014-08-22 09:49:06 +05302343 else if (INTEL_INFO(dev)->gen < 9)
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00002344 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03002345}
2346
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002347static void intel_enable_ddi(struct intel_encoder *intel_encoder)
Eugeni Dodonov72662e12012-05-09 15:37:31 -03002348{
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002349 struct drm_encoder *encoder = &intel_encoder->base;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08002350 struct drm_crtc *crtc = encoder->crtc;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002352 struct drm_device *dev = encoder->dev;
Eugeni Dodonov72662e12012-05-09 15:37:31 -03002353 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002354 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2355 int type = intel_encoder->type;
Eugeni Dodonov72662e12012-05-09 15:37:31 -03002356
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002357 if (type == INTEL_OUTPUT_HDMI) {
Damien Lespiau876a8cd2012-12-11 18:48:30 +00002358 struct intel_digital_port *intel_dig_port =
2359 enc_to_dig_port(encoder);
2360
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002361 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2362 * are ignored so nothing special needs to be done besides
2363 * enabling the port.
2364 */
Damien Lespiau876a8cd2012-12-11 18:48:30 +00002365 I915_WRITE(DDI_BUF_CTL(port),
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07002366 intel_dig_port->saved_port_bits |
2367 DDI_BUF_CTL_ENABLE);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002368 } else if (type == INTEL_OUTPUT_EDP) {
2369 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2370
Vandana Kannan23f08d82014-11-13 14:55:22 +00002371 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
Imre Deak3ab9c632013-05-03 12:57:41 +03002372 intel_dp_stop_link_train(intel_dp);
2373
Daniel Vetter4be73782014-01-17 14:39:48 +01002374 intel_edp_backlight_on(intel_dp);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08002375 intel_psr_enable(intel_dp);
Vandana Kannanc3955782015-01-22 15:17:40 +05302376 intel_edp_drrs_enable(intel_dp);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03002377 }
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08002378
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002379 if (intel_crtc->config->has_audio) {
Paulo Zanonid45a0bf2014-05-21 17:29:31 -03002380 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
Jani Nikula69bfe1a2014-10-27 16:26:50 +02002381 intel_audio_codec_enable(intel_encoder);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08002382 }
Daniel Vetter5ab432e2012-06-30 08:59:56 +02002383}
2384
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002385static void intel_disable_ddi(struct intel_encoder *intel_encoder)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02002386{
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002387 struct drm_encoder *encoder = &intel_encoder->base;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08002388 struct drm_crtc *crtc = encoder->crtc;
2389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002390 int type = intel_encoder->type;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08002391 struct drm_device *dev = encoder->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002393
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002394 if (intel_crtc->config->has_audio) {
Jani Nikula69bfe1a2014-10-27 16:26:50 +02002395 intel_audio_codec_disable(intel_encoder);
Paulo Zanonid45a0bf2014-05-21 17:29:31 -03002396 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2397 }
Paulo Zanoni2831d8422013-03-06 20:03:09 -03002398
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002399 if (type == INTEL_OUTPUT_EDP) {
2400 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2401
Vandana Kannanc3955782015-01-22 15:17:40 +05302402 intel_edp_drrs_disable(intel_dp);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08002403 intel_psr_disable(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01002404 intel_edp_backlight_off(intel_dp);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02002405 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03002406}
Paulo Zanoni79f689a2012-10-05 12:05:52 -03002407
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002408static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
Daniel Vettere0b01be2014-06-25 22:02:01 +03002409 struct intel_shared_dpll *pll)
2410{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02002411 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
Daniel Vettere0b01be2014-06-25 22:02:01 +03002412 POSTING_READ(WRPLL_CTL(pll->id));
2413 udelay(20);
2414}
2415
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002416static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
Daniel Vetter12030432014-06-25 22:02:00 +03002417 struct intel_shared_dpll *pll)
2418{
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002419 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2420 POSTING_READ(SPLL_CTL);
2421 udelay(20);
2422}
2423
2424static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2425 struct intel_shared_dpll *pll)
2426{
Daniel Vetter12030432014-06-25 22:02:00 +03002427 uint32_t val;
2428
2429 val = I915_READ(WRPLL_CTL(pll->id));
Daniel Vetter12030432014-06-25 22:02:00 +03002430 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2431 POSTING_READ(WRPLL_CTL(pll->id));
2432}
2433
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002434static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2435 struct intel_shared_dpll *pll)
2436{
2437 uint32_t val;
2438
2439 val = I915_READ(SPLL_CTL);
2440 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2441 POSTING_READ(SPLL_CTL);
2442}
2443
2444static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2445 struct intel_shared_dpll *pll,
2446 struct intel_dpll_hw_state *hw_state)
Daniel Vetterd452c5b2014-07-04 11:27:39 -03002447{
2448 uint32_t val;
2449
Daniel Vetterf458ebb2014-09-30 10:56:39 +02002450 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Daniel Vetterd452c5b2014-07-04 11:27:39 -03002451 return false;
2452
2453 val = I915_READ(WRPLL_CTL(pll->id));
2454 hw_state->wrpll = val;
2455
2456 return val & WRPLL_PLL_ENABLE;
2457}
2458
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002459static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2460 struct intel_shared_dpll *pll,
2461 struct intel_dpll_hw_state *hw_state)
2462{
2463 uint32_t val;
2464
2465 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2466 return false;
2467
2468 val = I915_READ(SPLL_CTL);
2469 hw_state->spll = val;
2470
2471 return val & SPLL_PLL_ENABLE;
2472}
2473
2474
Damien Lespiauca1381b2014-07-15 15:05:33 +01002475static const char * const hsw_ddi_pll_names[] = {
Daniel Vetter9cd86932014-06-25 22:01:57 +03002476 "WRPLL 1",
2477 "WRPLL 2",
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002478 "SPLL"
Daniel Vetter9cd86932014-06-25 22:01:57 +03002479};
2480
Damien Lespiau143b3072014-07-29 18:06:19 +01002481static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03002482{
Daniel Vetter9cd86932014-06-25 22:01:57 +03002483 int i;
2484
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002485 dev_priv->num_shared_dpll = 3;
Daniel Vetter9cd86932014-06-25 22:01:57 +03002486
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002487 for (i = 0; i < 2; i++) {
Daniel Vetter9cd86932014-06-25 22:01:57 +03002488 dev_priv->shared_dplls[i].id = i;
2489 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002490 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2491 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03002492 dev_priv->shared_dplls[i].get_hw_state =
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002493 hsw_ddi_wrpll_get_hw_state;
Daniel Vetter9cd86932014-06-25 22:01:57 +03002494 }
Maarten Lankhorst00490c22015-11-16 14:42:12 +01002495
2496 /* SPLL is special, but needs to be initialized anyway.. */
2497 dev_priv->shared_dplls[i].id = i;
2498 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2499 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2500 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2501 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2502
Damien Lespiau143b3072014-07-29 18:06:19 +01002503}
2504
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002505static const char * const skl_ddi_pll_names[] = {
2506 "DPLL 1",
2507 "DPLL 2",
2508 "DPLL 3",
2509};
2510
2511struct skl_dpll_regs {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002512 i915_reg_t ctl, cfgcr1, cfgcr2;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002513};
2514
2515/* this array is indexed by the *shared* pll id */
2516static const struct skl_dpll_regs skl_dpll_regs[3] = {
2517 {
2518 /* DPLL 1 */
2519 .ctl = LCPLL2_CTL,
Ville Syrjälä923c12412015-09-30 17:06:43 +03002520 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2521 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002522 },
2523 {
2524 /* DPLL 2 */
Ville Syrjälä01403de2015-09-18 20:03:33 +03002525 .ctl = WRPLL_CTL(0),
Ville Syrjälä923c12412015-09-30 17:06:43 +03002526 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2527 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002528 },
2529 {
2530 /* DPLL 3 */
Ville Syrjälä01403de2015-09-18 20:03:33 +03002531 .ctl = WRPLL_CTL(1),
Ville Syrjälä923c12412015-09-30 17:06:43 +03002532 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2533 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002534 },
2535};
2536
2537static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2538 struct intel_shared_dpll *pll)
2539{
2540 uint32_t val;
2541 unsigned int dpll;
2542 const struct skl_dpll_regs *regs = skl_dpll_regs;
2543
2544 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2545 dpll = pll->id + 1;
2546
2547 val = I915_READ(DPLL_CTRL1);
2548
2549 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
Damien Lespiau71cd8422015-04-30 16:39:17 +01002550 DPLL_CTRL1_LINK_RATE_MASK(dpll));
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002551 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2552
2553 I915_WRITE(DPLL_CTRL1, val);
2554 POSTING_READ(DPLL_CTRL1);
2555
2556 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2557 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2558 POSTING_READ(regs[pll->id].cfgcr1);
2559 POSTING_READ(regs[pll->id].cfgcr2);
2560
2561 /* the enable bit is always bit 31 */
2562 I915_WRITE(regs[pll->id].ctl,
2563 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2564
2565 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2566 DRM_ERROR("DPLL %d not locked\n", dpll);
2567}
2568
2569static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2570 struct intel_shared_dpll *pll)
2571{
2572 const struct skl_dpll_regs *regs = skl_dpll_regs;
2573
2574 /* the enable bit is always bit 31 */
2575 I915_WRITE(regs[pll->id].ctl,
2576 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2577 POSTING_READ(regs[pll->id].ctl);
2578}
2579
2580static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2581 struct intel_shared_dpll *pll,
2582 struct intel_dpll_hw_state *hw_state)
2583{
2584 uint32_t val;
2585 unsigned int dpll;
2586 const struct skl_dpll_regs *regs = skl_dpll_regs;
2587
2588 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2589 return false;
2590
2591 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2592 dpll = pll->id + 1;
2593
2594 val = I915_READ(regs[pll->id].ctl);
2595 if (!(val & LCPLL_PLL_ENABLE))
2596 return false;
2597
2598 val = I915_READ(DPLL_CTRL1);
2599 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2600
2601 /* avoid reading back stale values if HDMI mode is not enabled */
2602 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2603 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2604 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2605 }
2606
2607 return true;
2608}
2609
2610static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2611{
2612 int i;
2613
2614 dev_priv->num_shared_dpll = 3;
2615
2616 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2617 dev_priv->shared_dplls[i].id = i;
2618 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2619 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2620 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2621 dev_priv->shared_dplls[i].get_hw_state =
2622 skl_ddi_pll_get_hw_state;
2623 }
2624}
2625
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302626static void broxton_phy_init(struct drm_i915_private *dev_priv,
2627 enum dpio_phy phy)
2628{
2629 enum port port;
2630 uint32_t val;
2631
2632 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2633 val |= GT_DISPLAY_POWER_ON(phy);
2634 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2635
2636 /* Considering 10ms timeout until BSpec is updated */
2637 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2638 DRM_ERROR("timeout during PHY%d power on\n", phy);
2639
2640 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2641 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2642 int lane;
2643
2644 for (lane = 0; lane < 4; lane++) {
2645 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2646 /*
2647 * Note that on CHV this flag is called UPAR, but has
2648 * the same function.
2649 */
2650 val &= ~LATENCY_OPTIM;
2651 if (lane != 1)
2652 val |= LATENCY_OPTIM;
2653
2654 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2655 }
2656 }
2657
2658 /* Program PLL Rcomp code offset */
2659 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2660 val &= ~IREF0RC_OFFSET_MASK;
2661 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2662 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2663
2664 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2665 val &= ~IREF1RC_OFFSET_MASK;
2666 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2667 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2668
2669 /* Program power gating */
2670 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2671 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2672 SUS_CLK_CONFIG;
2673 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2674
2675 if (phy == DPIO_PHY0) {
2676 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2677 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2678 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2679 }
2680
2681 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2682 val &= ~OCL2_LDOFUSE_PWR_DIS;
2683 /*
2684 * On PHY1 disable power on the second channel, since no port is
2685 * connected there. On PHY0 both channels have a port, so leave it
2686 * enabled.
2687 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2688 * power down the second channel on PHY0 as well.
2689 */
2690 if (phy == DPIO_PHY1)
2691 val |= OCL2_LDOFUSE_PWR_DIS;
2692 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2693
2694 if (phy == DPIO_PHY0) {
2695 uint32_t grc_code;
2696 /*
2697 * PHY0 isn't connected to an RCOMP resistor so copy over
2698 * the corresponding calibrated value from PHY1, and disable
2699 * the automatic calibration on PHY0.
2700 */
2701 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2702 10))
2703 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2704
2705 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2706 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2707 grc_code = val << GRC_CODE_FAST_SHIFT |
2708 val << GRC_CODE_SLOW_SHIFT |
2709 val;
2710 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2711
2712 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2713 val |= GRC_DIS | GRC_RDY_OVRD;
2714 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2715 }
2716
2717 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2718 val |= COMMON_RESET_DIS;
2719 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2720}
2721
2722void broxton_ddi_phy_init(struct drm_device *dev)
2723{
2724 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2725 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2726 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2727}
2728
2729static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2730 enum dpio_phy phy)
2731{
2732 uint32_t val;
2733
2734 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2735 val &= ~COMMON_RESET_DIS;
2736 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2737}
2738
2739void broxton_ddi_phy_uninit(struct drm_device *dev)
2740{
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742
2743 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2744 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2745
2746 /* FIXME: do this in broxton_phy_uninit per phy */
2747 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2748}
2749
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302750static const char * const bxt_ddi_pll_names[] = {
2751 "PORT PLL A",
2752 "PORT PLL B",
2753 "PORT PLL C",
2754};
2755
2756static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2757 struct intel_shared_dpll *pll)
2758{
2759 uint32_t temp;
2760 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2761
2762 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2763 temp &= ~PORT_PLL_REF_SEL;
2764 /* Non-SSC reference */
2765 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2766
2767 /* Disable 10 bit clock */
2768 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2769 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2770 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2771
2772 /* Write P1 & P2 */
2773 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2774 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2775 temp |= pll->config.hw_state.ebb0;
2776 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2777
2778 /* Write M2 integer */
2779 temp = I915_READ(BXT_PORT_PLL(port, 0));
2780 temp &= ~PORT_PLL_M2_MASK;
2781 temp |= pll->config.hw_state.pll0;
2782 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2783
2784 /* Write N */
2785 temp = I915_READ(BXT_PORT_PLL(port, 1));
2786 temp &= ~PORT_PLL_N_MASK;
2787 temp |= pll->config.hw_state.pll1;
2788 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2789
2790 /* Write M2 fraction */
2791 temp = I915_READ(BXT_PORT_PLL(port, 2));
2792 temp &= ~PORT_PLL_M2_FRAC_MASK;
2793 temp |= pll->config.hw_state.pll2;
2794 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2795
2796 /* Write M2 fraction enable */
2797 temp = I915_READ(BXT_PORT_PLL(port, 3));
2798 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2799 temp |= pll->config.hw_state.pll3;
2800 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2801
2802 /* Write coeff */
2803 temp = I915_READ(BXT_PORT_PLL(port, 6));
2804 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2805 temp &= ~PORT_PLL_INT_COEFF_MASK;
2806 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2807 temp |= pll->config.hw_state.pll6;
2808 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2809
2810 /* Write calibration val */
2811 temp = I915_READ(BXT_PORT_PLL(port, 8));
2812 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2813 temp |= pll->config.hw_state.pll8;
2814 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2815
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05302816 temp = I915_READ(BXT_PORT_PLL(port, 9));
2817 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
Imre Deak05712c12015-06-18 17:25:54 +03002818 temp |= pll->config.hw_state.pll9;
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05302819 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2820
2821 temp = I915_READ(BXT_PORT_PLL(port, 10));
2822 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2823 temp &= ~PORT_PLL_DCO_AMP_MASK;
2824 temp |= pll->config.hw_state.pll10;
2825 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302826
2827 /* Recalibrate with new settings */
2828 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2829 temp |= PORT_PLL_RECALIBRATE;
2830 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
Imre Deak05712c12015-06-18 17:25:54 +03002831 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2832 temp |= pll->config.hw_state.ebb4;
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302833 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2834
2835 /* Enable PLL */
2836 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2837 temp |= PORT_PLL_ENABLE;
2838 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2839 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2840
2841 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2842 PORT_PLL_LOCK), 200))
2843 DRM_ERROR("PLL %d not locked\n", port);
2844
2845 /*
2846 * While we write to the group register to program all lanes at once we
2847 * can read only lane registers and we pick lanes 0/1 for that.
2848 */
2849 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2850 temp &= ~LANE_STAGGER_MASK;
2851 temp &= ~LANESTAGGER_STRAP_OVRD;
2852 temp |= pll->config.hw_state.pcsdw12;
2853 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2854}
2855
2856static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2857 struct intel_shared_dpll *pll)
2858{
2859 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2860 uint32_t temp;
2861
2862 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2863 temp &= ~PORT_PLL_ENABLE;
2864 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2865 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2866}
2867
2868static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2869 struct intel_shared_dpll *pll,
2870 struct intel_dpll_hw_state *hw_state)
2871{
2872 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2873 uint32_t val;
2874
2875 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2876 return false;
2877
2878 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2879 if (!(val & PORT_PLL_ENABLE))
2880 return false;
2881
2882 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
Imre Deak793dfa52015-06-18 17:25:53 +03002883 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2884
Imre Deak05712c12015-06-18 17:25:54 +03002885 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2886 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2887
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302888 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
Imre Deak793dfa52015-06-18 17:25:53 +03002889 hw_state->pll0 &= PORT_PLL_M2_MASK;
2890
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302891 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
Imre Deak793dfa52015-06-18 17:25:53 +03002892 hw_state->pll1 &= PORT_PLL_N_MASK;
2893
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302894 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
Imre Deak793dfa52015-06-18 17:25:53 +03002895 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2896
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302897 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
Imre Deak793dfa52015-06-18 17:25:53 +03002898 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2899
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302900 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
Imre Deak793dfa52015-06-18 17:25:53 +03002901 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2902 PORT_PLL_INT_COEFF_MASK |
2903 PORT_PLL_GAIN_CTL_MASK;
2904
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302905 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
Imre Deak793dfa52015-06-18 17:25:53 +03002906 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2907
Imre Deak05712c12015-06-18 17:25:54 +03002908 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2909 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2910
Vandana Kannanb6dc71f2015-05-13 12:18:52 +05302911 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
Imre Deak793dfa52015-06-18 17:25:53 +03002912 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2913 PORT_PLL_DCO_AMP_MASK;
2914
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302915 /*
2916 * While we write to the group register to program all lanes at once we
2917 * can read only lane registers. We configure all lanes the same way, so
2918 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2919 */
2920 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
Damien Lespiaub5dada82015-09-17 14:20:32 +01002921 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302922 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2923 hw_state->pcsdw12,
2924 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
Imre Deak793dfa52015-06-18 17:25:53 +03002925 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302926
2927 return true;
2928}
2929
2930static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2931{
2932 int i;
2933
2934 dev_priv->num_shared_dpll = 3;
2935
2936 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2937 dev_priv->shared_dplls[i].id = i;
2938 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2939 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2940 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2941 dev_priv->shared_dplls[i].get_hw_state =
2942 bxt_ddi_pll_get_hw_state;
2943 }
2944}
2945
Damien Lespiau143b3072014-07-29 18:06:19 +01002946void intel_ddi_pll_init(struct drm_device *dev)
2947{
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 uint32_t val = I915_READ(LCPLL_CTL);
2950
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002951 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002952 skl_shared_dplls_init(dev_priv);
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +05302953 else if (IS_BROXTON(dev))
2954 bxt_shared_dplls_init(dev_priv);
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +00002955 else
2956 hsw_shared_dplls_init(dev_priv);
Paulo Zanoni79f689a2012-10-05 12:05:52 -03002957
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002958 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Damien Lespiaud9062ae2015-06-04 18:21:32 +01002959 int cdclk_freq;
2960
2961 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01002962 dev_priv->skl_boot_cdclk = cdclk_freq;
Shobhit Kumarc73666f2015-10-20 18:13:12 +05302963 if (skl_sanitize_cdclk(dev_priv))
2964 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
Damien Lespiau2f693e22015-11-04 19:24:12 +02002965 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2966 DRM_ERROR("LCPLL1 is disabled\n");
Vandana Kannanf8437dd12014-11-24 13:37:39 +05302967 } else if (IS_BROXTON(dev)) {
2968 broxton_init_cdclk(dev);
Vandana Kannan5c6706e2014-11-24 13:37:39 +05302969 broxton_ddi_phy_init(dev);
Satheeshakrishna M121643c2014-11-13 14:55:15 +00002970 } else {
2971 /*
2972 * The LCPLL register should be turned on by the BIOS. For now
2973 * let's just check its state and print errors in case
2974 * something is wrong. Don't even try to turn it on.
2975 */
Paulo Zanoni79f689a2012-10-05 12:05:52 -03002976
Satheeshakrishna M121643c2014-11-13 14:55:15 +00002977 if (val & LCPLL_CD_SOURCE_FCLK)
2978 DRM_ERROR("CDCLK source is not LCPLL\n");
2979
2980 if (val & LCPLL_PLL_DISABLE)
2981 DRM_ERROR("LCPLL is disabled\n");
2982 }
Paulo Zanoni79f689a2012-10-05 12:05:52 -03002983}
Paulo Zanonic19b0662012-10-15 15:51:41 -03002984
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03002985void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
Paulo Zanonic19b0662012-10-15 15:51:41 -03002986{
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03002987 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2988 struct drm_i915_private *dev_priv =
2989 to_i915(intel_dig_port->base.base.dev);
Paulo Zanoni174edf12012-10-26 19:05:50 -02002990 enum port port = intel_dig_port->port;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002991 uint32_t val;
Syam Sidhardhanf3e227d2013-02-25 04:05:38 +05302992 bool wait = false;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002993
2994 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2995 val = I915_READ(DDI_BUF_CTL(port));
2996 if (val & DDI_BUF_CTL_ENABLE) {
2997 val &= ~DDI_BUF_CTL_ENABLE;
2998 I915_WRITE(DDI_BUF_CTL(port), val);
2999 wait = true;
3000 }
3001
3002 val = I915_READ(DP_TP_CTL(port));
3003 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3004 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3005 I915_WRITE(DP_TP_CTL(port), val);
3006 POSTING_READ(DP_TP_CTL(port));
3007
3008 if (wait)
3009 intel_wait_ddi_buf_idle(dev_priv, port);
3010 }
3011
Dave Airlie0e32b392014-05-02 14:02:48 +10003012 val = DP_TP_CTL_ENABLE |
Paulo Zanonic19b0662012-10-15 15:51:41 -03003013 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
Dave Airlie0e32b392014-05-02 14:02:48 +10003014 if (intel_dp->is_mst)
3015 val |= DP_TP_CTL_MODE_MST;
3016 else {
3017 val |= DP_TP_CTL_MODE_SST;
3018 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3019 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3020 }
Paulo Zanonic19b0662012-10-15 15:51:41 -03003021 I915_WRITE(DP_TP_CTL(port), val);
3022 POSTING_READ(DP_TP_CTL(port));
3023
3024 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3025 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3026 POSTING_READ(DDI_BUF_CTL(port));
3027
3028 udelay(600);
3029}
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003030
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003031void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3032{
3033 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3034 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3035 uint32_t val;
3036
3037 intel_ddi_post_disable(intel_encoder);
3038
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003039 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003040 val &= ~FDI_RX_ENABLE;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003041 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003042
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003043 val = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003044 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3045 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003046 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003047
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003048 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003049 val &= ~FDI_PCDCLK;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003050 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003051
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003052 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003053 val &= ~FDI_RX_PLL_ENABLE;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03003054 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003055}
3056
Libin Yang3d52ccf2015-12-02 14:09:44 +08003057bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3058 struct intel_crtc *intel_crtc)
3059{
3060 u32 temp;
3061
3062 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3063 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3064 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3065 return true;
3066 }
3067 return false;
3068}
3069
Ville Syrjälä6801c182013-09-24 14:24:05 +03003070void intel_ddi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02003071 struct intel_crtc_state *pipe_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -07003072{
3073 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3074 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Ander Conselvan de Oliveira0cb09a92015-01-30 12:17:23 +02003075 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01003076 struct intel_hdmi *intel_hdmi;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07003077 u32 temp, flags = 0;
3078
3079 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3080 if (temp & TRANS_DDI_PHSYNC)
3081 flags |= DRM_MODE_FLAG_PHSYNC;
3082 else
3083 flags |= DRM_MODE_FLAG_NHSYNC;
3084 if (temp & TRANS_DDI_PVSYNC)
3085 flags |= DRM_MODE_FLAG_PVSYNC;
3086 else
3087 flags |= DRM_MODE_FLAG_NVSYNC;
3088
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02003089 pipe_config->base.adjusted_mode.flags |= flags;
Ville Syrjälä42571ae2013-09-06 23:29:00 +03003090
3091 switch (temp & TRANS_DDI_BPC_MASK) {
3092 case TRANS_DDI_BPC_6:
3093 pipe_config->pipe_bpp = 18;
3094 break;
3095 case TRANS_DDI_BPC_8:
3096 pipe_config->pipe_bpp = 24;
3097 break;
3098 case TRANS_DDI_BPC_10:
3099 pipe_config->pipe_bpp = 30;
3100 break;
3101 case TRANS_DDI_BPC_12:
3102 pipe_config->pipe_bpp = 36;
3103 break;
3104 default:
3105 break;
3106 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03003107
3108 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3109 case TRANS_DDI_MODE_SELECT_HDMI:
Daniel Vetter6897b4b2014-04-24 23:54:47 +02003110 pipe_config->has_hdmi_sink = true;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01003111 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3112
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +02003113 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
Daniel Vetterbbd440f2014-11-20 22:33:59 +01003114 pipe_config->has_infoframe = true;
Jesse Barnescbc572a2014-11-17 13:08:47 -08003115 break;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03003116 case TRANS_DDI_MODE_SELECT_DVI:
3117 case TRANS_DDI_MODE_SELECT_FDI:
3118 break;
3119 case TRANS_DDI_MODE_SELECT_DP_SST:
3120 case TRANS_DDI_MODE_SELECT_DP_MST:
3121 pipe_config->has_dp_encoder = true;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03003122 pipe_config->lane_count =
3123 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03003124 intel_dp_get_m_n(intel_crtc, pipe_config);
3125 break;
3126 default:
3127 break;
3128 }
Daniel Vetter10214422013-11-18 07:38:16 +01003129
Libin Yang3d52ccf2015-12-02 14:09:44 +08003130 pipe_config->has_audio =
3131 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
Daniel Vetter9ed109a2014-04-24 23:54:52 +02003132
Daniel Vetter10214422013-11-18 07:38:16 +01003133 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3134 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3135 /*
3136 * This is a big fat ugly hack.
3137 *
3138 * Some machines in UEFI boot mode provide us a VBT that has 18
3139 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3140 * unknown we fail to light up. Yet the same BIOS boots up with
3141 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3142 * max, not what it tells us to use.
3143 *
3144 * Note: This will still be broken if the eDP panel is not lit
3145 * up by the BIOS, and thus we can't get the mode at module
3146 * load.
3147 */
3148 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3149 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3150 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3151 }
Jesse Barnes11578552014-01-21 12:42:10 -08003152
Damien Lespiau22606a12014-12-12 14:26:57 +00003153 intel_ddi_clock_get(encoder, pipe_config);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07003154}
3155
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003156static void intel_ddi_destroy(struct drm_encoder *encoder)
3157{
3158 /* HDMI has nothing special to destroy, so we can go with this. */
3159 intel_dp_encoder_destroy(encoder);
3160}
3161
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003162static bool intel_ddi_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02003163 struct intel_crtc_state *pipe_config)
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003164{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003165 int type = encoder->type;
Daniel Vettereccb1402013-05-22 00:50:22 +02003166 int port = intel_ddi_get_encoder_port(encoder);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003167
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003168 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003169
Daniel Vettereccb1402013-05-22 00:50:22 +02003170 if (port == PORT_A)
3171 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3172
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003173 if (type == INTEL_OUTPUT_HDMI)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003174 return intel_hdmi_compute_config(encoder, pipe_config);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003175 else
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003176 return intel_dp_compute_config(encoder, pipe_config);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003177}
3178
3179static const struct drm_encoder_funcs intel_ddi_funcs = {
3180 .destroy = intel_ddi_destroy,
3181};
3182
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03003183static struct intel_connector *
3184intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3185{
3186 struct intel_connector *connector;
3187 enum port port = intel_dig_port->port;
3188
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03003189 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03003190 if (!connector)
3191 return NULL;
3192
3193 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3194 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3195 kfree(connector);
3196 return NULL;
3197 }
3198
3199 return connector;
3200}
3201
3202static struct intel_connector *
3203intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3204{
3205 struct intel_connector *connector;
3206 enum port port = intel_dig_port->port;
3207
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03003208 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03003209 if (!connector)
3210 return NULL;
3211
3212 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3213 intel_hdmi_init_connector(intel_dig_port, connector);
3214
3215 return connector;
3216}
3217
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003218void intel_ddi_init(struct drm_device *dev, enum port port)
3219{
Damien Lespiau876a8cd2012-12-11 18:48:30 +00003220 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003221 struct intel_digital_port *intel_dig_port;
3222 struct intel_encoder *intel_encoder;
3223 struct drm_encoder *encoder;
Paulo Zanoni311a2092013-09-12 17:12:18 -03003224 bool init_hdmi, init_dp;
Ville Syrjälä10e7bec2015-12-08 19:59:37 +02003225 int max_lanes;
3226
3227 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3228 switch (port) {
3229 case PORT_A:
3230 max_lanes = 4;
3231 break;
3232 case PORT_E:
3233 max_lanes = 0;
3234 break;
3235 default:
3236 max_lanes = 4;
3237 break;
3238 }
3239 } else {
3240 switch (port) {
3241 case PORT_A:
3242 max_lanes = 2;
3243 break;
3244 case PORT_E:
3245 max_lanes = 2;
3246 break;
3247 default:
3248 max_lanes = 4;
3249 break;
3250 }
3251 }
Paulo Zanoni311a2092013-09-12 17:12:18 -03003252
3253 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3254 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3255 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3256 if (!init_dp && !init_hdmi) {
Rodrigo Vivi500ea702015-08-07 17:01:16 -07003257 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
Paulo Zanoni311a2092013-09-12 17:12:18 -03003258 port_name(port));
Rodrigo Vivi500ea702015-08-07 17:01:16 -07003259 return;
Paulo Zanoni311a2092013-09-12 17:12:18 -03003260 }
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003261
Daniel Vetterb14c5672013-09-19 12:18:32 +02003262 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003263 if (!intel_dig_port)
3264 return;
3265
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003266 intel_encoder = &intel_dig_port->base;
3267 encoder = &intel_encoder->base;
3268
3269 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
Ville Syrjälä13a3d912015-12-09 16:20:18 +02003270 DRM_MODE_ENCODER_TMDS, NULL);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003271
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003272 intel_encoder->compute_config = intel_ddi_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003273 intel_encoder->enable = intel_enable_ddi;
3274 intel_encoder->pre_enable = intel_ddi_pre_enable;
3275 intel_encoder->disable = intel_disable_ddi;
3276 intel_encoder->post_disable = intel_ddi_post_disable;
3277 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07003278 intel_encoder->get_config = intel_ddi_get_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003279
3280 intel_dig_port->port = port;
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01003281 dev_priv->dig_port_map[port] = intel_encoder;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07003282 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3283 (DDI_BUF_PORT_REVERSAL |
3284 DDI_A_4_LANES);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003285
Matt Roper6c566dc2015-11-05 14:53:32 -08003286 /*
3287 * Bspec says that DDI_A_4_LANES is the only supported configuration
3288 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3289 * wasn't lit up at boot. Force this bit on in our internal
3290 * configuration so that we use the proper lane count for our
3291 * calculations.
3292 */
3293 if (IS_BROXTON(dev) && port == PORT_A) {
3294 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3295 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3296 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
Matt Ropered8d60f2016-01-28 15:09:37 -08003297 max_lanes = 4;
Matt Roper6c566dc2015-11-05 14:53:32 -08003298 }
3299 }
3300
Matt Ropered8d60f2016-01-28 15:09:37 -08003301 intel_dig_port->max_lanes = max_lanes;
3302
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003303 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
Chris Wilsonf68d6972014-08-04 07:15:09 +01003304 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Ville Syrjäläbc079e82014-03-03 16:15:28 +02003305 intel_encoder->cloneable = 0;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003306
Chris Wilsonf68d6972014-08-04 07:15:09 +01003307 if (init_dp) {
3308 if (!intel_ddi_init_dp_connector(intel_dig_port))
3309 goto err;
Dave Airlie13cf5502014-06-18 11:29:35 +10003310
Chris Wilsonf68d6972014-08-04 07:15:09 +01003311 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
Sonika Jindalcf1d5882015-08-10 10:35:36 +05303312 /*
3313 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3314 * interrupts to check the external panel connection.
3315 */
Jani Nikulae87a0052015-10-20 15:22:02 +03003316 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
Sonika Jindalcf1d5882015-08-10 10:35:36 +05303317 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3318 else
3319 dev_priv->hotplug.irq_port[port] = intel_dig_port;
Chris Wilsonf68d6972014-08-04 07:15:09 +01003320 }
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02003321
Paulo Zanoni311a2092013-09-12 17:12:18 -03003322 /* In theory we don't need the encoder->type check, but leave it just in
3323 * case we have some really bad VBTs... */
Chris Wilsonf68d6972014-08-04 07:15:09 +01003324 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3325 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3326 goto err;
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02003327 }
Chris Wilsonf68d6972014-08-04 07:15:09 +01003328
3329 return;
3330
3331err:
3332 drm_encoder_cleanup(encoder);
3333 kfree(intel_dig_port);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003334}