Stephen Warren | ae278a9 | 2012-11-19 16:41:20 -0700 | [diff] [blame] | 1 | config CLKSRC_OF |
| 2 | bool |
| 3 | |
Russell King | 89c0b8e | 2011-05-08 18:47:58 +0100 | [diff] [blame] | 4 | config CLKSRC_I8253 |
| 5 | bool |
Russell King | 442c817 | 2011-05-08 14:06:52 +0100 | [diff] [blame] | 6 | |
Thomas Gleixner | e6220bd | 2011-06-09 13:08:25 +0000 | [diff] [blame] | 7 | config CLKEVT_I8253 |
| 8 | bool |
| 9 | |
Ralf Baechle | 15f304b | 2011-06-01 19:04:59 +0100 | [diff] [blame] | 10 | config I8253_LOCK |
| 11 | bool |
| 12 | |
| 13 | config CLKBLD_I8253 |
Thomas Gleixner | e6220bd | 2011-06-09 13:08:25 +0000 | [diff] [blame] | 14 | def_bool y if CLKSRC_I8253 || CLKEVT_I8253 || I8253_LOCK |
Ralf Baechle | 15f304b | 2011-06-01 19:04:59 +0100 | [diff] [blame] | 15 | |
Russell King | 442c817 | 2011-05-08 14:06:52 +0100 | [diff] [blame] | 16 | config CLKSRC_MMIO |
| 17 | bool |
Jamie Iles | 06c3df4 | 2011-06-06 12:43:07 +0100 | [diff] [blame] | 18 | |
| 19 | config DW_APB_TIMER |
| 20 | bool |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 21 | |
Dinh Nguyen | cfda590 | 2012-07-11 15:13:16 -0500 | [diff] [blame] | 22 | config DW_APB_TIMER_OF |
| 23 | bool |
Heiko Stuebner | 1b4eca0 | 2013-06-04 11:38:11 +0200 | [diff] [blame] | 24 | select DW_APB_TIMER |
Heiko Stuebner | 1002148 | 2013-06-04 11:38:42 +0200 | [diff] [blame] | 25 | select CLKSRC_OF |
Dinh Nguyen | cfda590 | 2012-07-11 15:13:16 -0500 | [diff] [blame] | 26 | |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 27 | config ARMADA_370_XP_TIMER |
| 28 | bool |
| 29 | |
Maxime Ripard | 119fd63 | 2013-03-24 11:49:25 +0100 | [diff] [blame] | 30 | config SUN4I_TIMER |
Maxime Ripard | b2ac5d7 | 2012-11-12 15:07:50 +0100 | [diff] [blame] | 31 | bool |
| 32 | |
Tony Prisk | ff7ec34 | 2013-01-14 17:58:21 +1300 | [diff] [blame] | 33 | config VT8500_TIMER |
| 34 | bool |
| 35 | |
Michal Simek | 4f0f234 | 2013-03-20 10:46:01 +0100 | [diff] [blame] | 36 | config CADENCE_TTC_TIMER |
| 37 | bool |
| 38 | |
Linus Walleij | 694e33a | 2012-10-18 14:01:25 +0200 | [diff] [blame] | 39 | config CLKSRC_NOMADIK_MTU |
| 40 | bool |
| 41 | depends on (ARCH_NOMADIK || ARCH_U8500) |
| 42 | select CLKSRC_MMIO |
| 43 | help |
| 44 | Support for Multi Timer Unit. MTU provides access |
| 45 | to multiple interrupt generating programmable |
| 46 | 32-bit free running decrementing counters. |
| 47 | |
| 48 | config CLKSRC_NOMADIK_MTU_SCHED_CLOCK |
| 49 | bool |
| 50 | depends on CLKSRC_NOMADIK_MTU |
| 51 | help |
| 52 | Use the Multi Timer Unit as the sched_clock. |
| 53 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 54 | config CLKSRC_DBX500_PRCMU |
| 55 | bool "Clocksource PRCMU Timer" |
Linus Walleij | 29746f4 | 2012-04-13 13:16:31 +0200 | [diff] [blame] | 56 | depends on UX500_SOC_DB8500 |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 57 | default y |
| 58 | help |
| 59 | Use the always on PRCMU Timer as clocksource |
| 60 | |
| 61 | config CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
| 62 | bool "Clocksource PRCMU Timer sched_clock" |
Linus Walleij | 694e33a | 2012-10-18 14:01:25 +0200 | [diff] [blame] | 63 | depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 64 | default y |
| 65 | help |
| 66 | Use the always on PRCMU Timer as sched_clock |
Marc Zyngier | 985c067 | 2012-03-05 11:49:30 +0000 | [diff] [blame] | 67 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 68 | config ARM_ARCH_TIMER |
| 69 | bool |
Rob Herring | 0583fe4 | 2013-04-10 18:27:51 -0500 | [diff] [blame] | 70 | select CLKSRC_OF if OF |
James Hogan | a2c5d4e | 2012-10-09 10:54:39 +0100 | [diff] [blame] | 71 | |
| 72 | config CLKSRC_METAG_GENERIC |
| 73 | def_bool y if METAG |
| 74 | help |
| 75 | This option enables support for the Meta per-thread timers. |
Thomas Abraham | 6938d75a | 2013-03-09 16:16:13 +0900 | [diff] [blame] | 76 | |
| 77 | config CLKSRC_EXYNOS_MCT |
| 78 | def_bool y if ARCH_EXYNOS |
| 79 | help |
| 80 | Support for Multi Core Timer controller on Exynos SoCs. |
Arnd Bergmann | 241a987 | 2013-05-06 23:49:09 +0200 | [diff] [blame] | 81 | |
Tomasz Figa | f118998 | 2013-04-20 23:22:13 +0200 | [diff] [blame] | 82 | config CLKSRC_SAMSUNG_PWM |
Tomasz Figa | 77d8443 | 2013-04-23 17:46:23 +0200 | [diff] [blame] | 83 | bool |
Tomasz Figa | f118998 | 2013-04-20 23:22:13 +0200 | [diff] [blame] | 84 | select CLKSRC_MMIO |
| 85 | help |
| 86 | This is a new clocksource driver for the PWM timer found in |
| 87 | Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver |
| 88 | for all devicetree enabled platforms. This driver will be |
| 89 | needed only on systems that do not have the Exynos MCT available. |