Harini Katakam | 38ed018 | 2014-07-08 16:32:36 +0530 | [diff] [blame] | 1 | Xilinx Zynq GPIO controller Device Tree Bindings |
| 2 | ------------------------------------------- |
| 3 | |
| 4 | Required properties: |
| 5 | - #gpio-cells : Should be two |
| 6 | - First cell is the GPIO line number |
| 7 | - Second cell is used to specify optional |
| 8 | parameters (unused) |
Anurag Kumar Vulisha | bdf7a4a | 2015-06-04 17:40:32 +0530 | [diff] [blame] | 9 | - compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" |
Harini Katakam | 38ed018 | 2014-07-08 16:32:36 +0530 | [diff] [blame] | 10 | - clocks : Clock specifier (see clock bindings for details) |
| 11 | - gpio-controller : Marks the device node as a GPIO controller. |
| 12 | - interrupts : Interrupt specifier (see interrupt bindings for |
| 13 | details) |
| 14 | - interrupt-parent : Must be core interrupt controller |
Soren Brinkmann | 787dfbb | 2015-10-23 09:25:30 -0700 | [diff] [blame^] | 15 | - interrupt-controller : Marks the device node as an interrupt controller. |
| 16 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. |
| 17 | The second cell bits[3:0] is used to specify trigger type and level flags: |
| 18 | 1 = low-to-high edge triggered. |
| 19 | 2 = high-to-low edge triggered. |
| 20 | 4 = active high level-sensitive. |
| 21 | 8 = active low level-sensitive. |
Harini Katakam | 38ed018 | 2014-07-08 16:32:36 +0530 | [diff] [blame] | 22 | - reg : Address and length of the register set for the device |
| 23 | |
| 24 | Example: |
| 25 | gpio@e000a000 { |
| 26 | #gpio-cells = <2>; |
| 27 | compatible = "xlnx,zynq-gpio-1.0"; |
| 28 | clocks = <&clkc 42>; |
| 29 | gpio-controller; |
| 30 | interrupt-parent = <&intc>; |
| 31 | interrupts = <0 20 4>; |
Soren Brinkmann | 787dfbb | 2015-10-23 09:25:30 -0700 | [diff] [blame^] | 32 | interrupt-controller; |
| 33 | #interrupt-cells = <2>; |
Harini Katakam | 38ed018 | 2014-07-08 16:32:36 +0530 | [diff] [blame] | 34 | reg = <0xe000a000 0x1000>; |
| 35 | }; |