Ken Wang | 220ab9b | 2017-03-06 14:49:53 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/firmware.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/module.h> |
| 26 | #include "drmP.h" |
| 27 | #include "amdgpu.h" |
| 28 | #include "amdgpu_atombios.h" |
| 29 | #include "amdgpu_ih.h" |
| 30 | #include "amdgpu_uvd.h" |
| 31 | #include "amdgpu_vce.h" |
| 32 | #include "amdgpu_ucode.h" |
| 33 | #include "amdgpu_psp.h" |
| 34 | #include "atom.h" |
| 35 | #include "amd_pcie.h" |
| 36 | |
| 37 | #include "vega10/soc15ip.h" |
| 38 | #include "vega10/UVD/uvd_7_0_offset.h" |
| 39 | #include "vega10/GC/gc_9_0_offset.h" |
| 40 | #include "vega10/GC/gc_9_0_sh_mask.h" |
| 41 | #include "vega10/SDMA0/sdma0_4_0_offset.h" |
| 42 | #include "vega10/SDMA1/sdma1_4_0_offset.h" |
| 43 | #include "vega10/HDP/hdp_4_0_offset.h" |
| 44 | #include "vega10/HDP/hdp_4_0_sh_mask.h" |
| 45 | #include "vega10/MP/mp_9_0_offset.h" |
| 46 | #include "vega10/MP/mp_9_0_sh_mask.h" |
| 47 | #include "vega10/SMUIO/smuio_9_0_offset.h" |
| 48 | #include "vega10/SMUIO/smuio_9_0_sh_mask.h" |
| 49 | |
| 50 | #include "soc15.h" |
| 51 | #include "soc15_common.h" |
| 52 | #include "gfx_v9_0.h" |
| 53 | #include "gmc_v9_0.h" |
| 54 | #include "gfxhub_v1_0.h" |
| 55 | #include "mmhub_v1_0.h" |
| 56 | #include "vega10_ih.h" |
| 57 | #include "sdma_v4_0.h" |
| 58 | #include "uvd_v7_0.h" |
| 59 | #include "vce_v4_0.h" |
| 60 | #include "amdgpu_powerplay.h" |
Xiangliang Yu | 796b656 | 2017-02-28 17:22:03 +0800 | [diff] [blame^] | 61 | #include "dce_virtual.h" |
Xiangliang Yu | f1a3446 | 2017-03-08 15:06:47 +0800 | [diff] [blame] | 62 | #include "mxgpu_ai.h" |
Ken Wang | 220ab9b | 2017-03-06 14:49:53 -0500 | [diff] [blame] | 63 | |
| 64 | MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); |
| 65 | |
| 66 | #define mmFabricConfigAccessControl 0x0410 |
| 67 | #define mmFabricConfigAccessControl_BASE_IDX 0 |
| 68 | #define mmFabricConfigAccessControl_DEFAULT 0x00000000 |
| 69 | //FabricConfigAccessControl |
| 70 | #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0 |
| 71 | #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1 |
| 72 | #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10 |
| 73 | #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L |
| 74 | #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L |
| 75 | #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L |
| 76 | |
| 77 | |
| 78 | #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc |
| 79 | #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0 |
| 80 | //DF_PIE_AON0_DfGlobalClkGater |
| 81 | #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 |
| 82 | #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL |
| 83 | |
| 84 | enum { |
| 85 | DF_MGCG_DISABLE = 0, |
| 86 | DF_MGCG_ENABLE_00_CYCLE_DELAY =1, |
| 87 | DF_MGCG_ENABLE_01_CYCLE_DELAY =2, |
| 88 | DF_MGCG_ENABLE_15_CYCLE_DELAY =13, |
| 89 | DF_MGCG_ENABLE_31_CYCLE_DELAY =14, |
| 90 | DF_MGCG_ENABLE_63_CYCLE_DELAY =15 |
| 91 | }; |
| 92 | |
| 93 | #define mmMP0_MISC_CGTT_CTRL0 0x01b9 |
| 94 | #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 |
| 95 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba |
| 96 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 |
| 97 | |
| 98 | /* |
| 99 | * Indirect registers accessor |
| 100 | */ |
| 101 | static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) |
| 102 | { |
| 103 | unsigned long flags, address, data; |
| 104 | u32 r; |
| 105 | struct nbio_pcie_index_data *nbio_pcie_id; |
| 106 | |
| 107 | if (adev->asic_type == CHIP_VEGA10) |
| 108 | nbio_pcie_id = &nbio_v6_1_pcie_index_data; |
| 109 | |
| 110 | address = nbio_pcie_id->index_offset; |
| 111 | data = nbio_pcie_id->data_offset; |
| 112 | |
| 113 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 114 | WREG32(address, reg); |
| 115 | (void)RREG32(address); |
| 116 | r = RREG32(data); |
| 117 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 118 | return r; |
| 119 | } |
| 120 | |
| 121 | static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 122 | { |
| 123 | unsigned long flags, address, data; |
| 124 | struct nbio_pcie_index_data *nbio_pcie_id; |
| 125 | |
| 126 | if (adev->asic_type == CHIP_VEGA10) |
| 127 | nbio_pcie_id = &nbio_v6_1_pcie_index_data; |
| 128 | |
| 129 | address = nbio_pcie_id->index_offset; |
| 130 | data = nbio_pcie_id->data_offset; |
| 131 | |
| 132 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 133 | WREG32(address, reg); |
| 134 | (void)RREG32(address); |
| 135 | WREG32(data, v); |
| 136 | (void)RREG32(data); |
| 137 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 138 | } |
| 139 | |
| 140 | static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
| 141 | { |
| 142 | unsigned long flags, address, data; |
| 143 | u32 r; |
| 144 | |
| 145 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
| 146 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
| 147 | |
| 148 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
| 149 | WREG32(address, ((reg) & 0x1ff)); |
| 150 | r = RREG32(data); |
| 151 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); |
| 152 | return r; |
| 153 | } |
| 154 | |
| 155 | static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 156 | { |
| 157 | unsigned long flags, address, data; |
| 158 | |
| 159 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
| 160 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
| 161 | |
| 162 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
| 163 | WREG32(address, ((reg) & 0x1ff)); |
| 164 | WREG32(data, (v)); |
| 165 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); |
| 166 | } |
| 167 | |
| 168 | static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) |
| 169 | { |
| 170 | unsigned long flags, address, data; |
| 171 | u32 r; |
| 172 | |
| 173 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
| 174 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
| 175 | |
| 176 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
| 177 | WREG32(address, (reg)); |
| 178 | r = RREG32(data); |
| 179 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); |
| 180 | return r; |
| 181 | } |
| 182 | |
| 183 | static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 184 | { |
| 185 | unsigned long flags, address, data; |
| 186 | |
| 187 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
| 188 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
| 189 | |
| 190 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
| 191 | WREG32(address, (reg)); |
| 192 | WREG32(data, (v)); |
| 193 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); |
| 194 | } |
| 195 | |
| 196 | static u32 soc15_get_config_memsize(struct amdgpu_device *adev) |
| 197 | { |
| 198 | return nbio_v6_1_get_memsize(adev); |
| 199 | } |
| 200 | |
| 201 | static const u32 vega10_golden_init[] = |
| 202 | { |
| 203 | }; |
| 204 | |
| 205 | static void soc15_init_golden_registers(struct amdgpu_device *adev) |
| 206 | { |
| 207 | /* Some of the registers might be dependent on GRBM_GFX_INDEX */ |
| 208 | mutex_lock(&adev->grbm_idx_mutex); |
| 209 | |
| 210 | switch (adev->asic_type) { |
| 211 | case CHIP_VEGA10: |
| 212 | amdgpu_program_register_sequence(adev, |
| 213 | vega10_golden_init, |
| 214 | (const u32)ARRAY_SIZE(vega10_golden_init)); |
| 215 | break; |
| 216 | default: |
| 217 | break; |
| 218 | } |
| 219 | mutex_unlock(&adev->grbm_idx_mutex); |
| 220 | } |
| 221 | static u32 soc15_get_xclk(struct amdgpu_device *adev) |
| 222 | { |
| 223 | if (adev->asic_type == CHIP_VEGA10) |
| 224 | return adev->clock.spll.reference_freq/4; |
| 225 | else |
| 226 | return adev->clock.spll.reference_freq; |
| 227 | } |
| 228 | |
| 229 | |
| 230 | void soc15_grbm_select(struct amdgpu_device *adev, |
| 231 | u32 me, u32 pipe, u32 queue, u32 vmid) |
| 232 | { |
| 233 | u32 grbm_gfx_cntl = 0; |
| 234 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); |
| 235 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); |
| 236 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); |
| 237 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); |
| 238 | |
| 239 | WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); |
| 240 | } |
| 241 | |
| 242 | static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) |
| 243 | { |
| 244 | /* todo */ |
| 245 | } |
| 246 | |
| 247 | static bool soc15_read_disabled_bios(struct amdgpu_device *adev) |
| 248 | { |
| 249 | /* todo */ |
| 250 | return false; |
| 251 | } |
| 252 | |
| 253 | static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, |
| 254 | u8 *bios, u32 length_bytes) |
| 255 | { |
| 256 | u32 *dw_ptr; |
| 257 | u32 i, length_dw; |
| 258 | |
| 259 | if (bios == NULL) |
| 260 | return false; |
| 261 | if (length_bytes == 0) |
| 262 | return false; |
| 263 | /* APU vbios image is part of sbios image */ |
| 264 | if (adev->flags & AMD_IS_APU) |
| 265 | return false; |
| 266 | |
| 267 | dw_ptr = (u32 *)bios; |
| 268 | length_dw = ALIGN(length_bytes, 4) / 4; |
| 269 | |
| 270 | /* set rom index to 0 */ |
| 271 | WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); |
| 272 | /* read out the rom data */ |
| 273 | for (i = 0; i < length_dw; i++) |
| 274 | dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); |
| 275 | |
| 276 | return true; |
| 277 | } |
| 278 | |
| 279 | static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = { |
| 280 | /* todo */ |
| 281 | }; |
| 282 | |
| 283 | static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { |
| 284 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false}, |
| 285 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false}, |
| 286 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false}, |
| 287 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false}, |
| 288 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false}, |
| 289 | { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false}, |
| 290 | { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false}, |
| 291 | { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false}, |
| 292 | { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false}, |
| 293 | { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false}, |
| 294 | { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false}, |
| 295 | { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false}, |
| 296 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false}, |
| 297 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false}, |
| 298 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false}, |
| 299 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false}, |
| 300 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false}, |
| 301 | { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false}, |
| 302 | { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false}, |
| 303 | { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true}, |
| 304 | { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true}, |
| 305 | { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false}, |
| 306 | }; |
| 307 | |
| 308 | static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, |
| 309 | u32 sh_num, u32 reg_offset) |
| 310 | { |
| 311 | uint32_t val; |
| 312 | |
| 313 | mutex_lock(&adev->grbm_idx_mutex); |
| 314 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
| 315 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); |
| 316 | |
| 317 | val = RREG32(reg_offset); |
| 318 | |
| 319 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
| 320 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| 321 | mutex_unlock(&adev->grbm_idx_mutex); |
| 322 | return val; |
| 323 | } |
| 324 | |
| 325 | static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, |
| 326 | u32 sh_num, u32 reg_offset, u32 *value) |
| 327 | { |
| 328 | struct amdgpu_allowed_register_entry *asic_register_table = NULL; |
| 329 | struct amdgpu_allowed_register_entry *asic_register_entry; |
| 330 | uint32_t size, i; |
| 331 | |
| 332 | *value = 0; |
| 333 | switch (adev->asic_type) { |
| 334 | case CHIP_VEGA10: |
| 335 | asic_register_table = vega10_allowed_read_registers; |
| 336 | size = ARRAY_SIZE(vega10_allowed_read_registers); |
| 337 | break; |
| 338 | default: |
| 339 | return -EINVAL; |
| 340 | } |
| 341 | |
| 342 | if (asic_register_table) { |
| 343 | for (i = 0; i < size; i++) { |
| 344 | asic_register_entry = asic_register_table + i; |
| 345 | if (reg_offset != asic_register_entry->reg_offset) |
| 346 | continue; |
| 347 | if (!asic_register_entry->untouched) |
| 348 | *value = asic_register_entry->grbm_indexed ? |
| 349 | soc15_read_indexed_register(adev, se_num, |
| 350 | sh_num, reg_offset) : |
| 351 | RREG32(reg_offset); |
| 352 | return 0; |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { |
| 357 | if (reg_offset != soc15_allowed_read_registers[i].reg_offset) |
| 358 | continue; |
| 359 | |
| 360 | if (!soc15_allowed_read_registers[i].untouched) |
| 361 | *value = soc15_allowed_read_registers[i].grbm_indexed ? |
| 362 | soc15_read_indexed_register(adev, se_num, |
| 363 | sh_num, reg_offset) : |
| 364 | RREG32(reg_offset); |
| 365 | return 0; |
| 366 | } |
| 367 | return -EINVAL; |
| 368 | } |
| 369 | |
| 370 | static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev) |
| 371 | { |
| 372 | u32 i; |
| 373 | |
| 374 | dev_info(adev->dev, "GPU pci config reset\n"); |
| 375 | |
| 376 | /* disable BM */ |
| 377 | pci_clear_master(adev->pdev); |
| 378 | /* reset */ |
| 379 | amdgpu_pci_config_reset(adev); |
| 380 | |
| 381 | udelay(100); |
| 382 | |
| 383 | /* wait for asic to come out of reset */ |
| 384 | for (i = 0; i < adev->usec_timeout; i++) { |
| 385 | if (nbio_v6_1_get_memsize(adev) != 0xffffffff) |
| 386 | break; |
| 387 | udelay(1); |
| 388 | } |
| 389 | |
| 390 | } |
| 391 | |
| 392 | static int soc15_asic_reset(struct amdgpu_device *adev) |
| 393 | { |
| 394 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); |
| 395 | |
| 396 | soc15_gpu_pci_config_reset(adev); |
| 397 | |
| 398 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |
| 404 | u32 cntl_reg, u32 status_reg) |
| 405 | { |
| 406 | return 0; |
| 407 | }*/ |
| 408 | |
| 409 | static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) |
| 410 | { |
| 411 | /*int r; |
| 412 | |
| 413 | r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); |
| 414 | if (r) |
| 415 | return r; |
| 416 | |
| 417 | r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); |
| 418 | */ |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) |
| 423 | { |
| 424 | /* todo */ |
| 425 | |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) |
| 430 | { |
| 431 | if (pci_is_root_bus(adev->pdev->bus)) |
| 432 | return; |
| 433 | |
| 434 | if (amdgpu_pcie_gen2 == 0) |
| 435 | return; |
| 436 | |
| 437 | if (adev->flags & AMD_IS_APU) |
| 438 | return; |
| 439 | |
| 440 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
| 441 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) |
| 442 | return; |
| 443 | |
| 444 | /* todo */ |
| 445 | } |
| 446 | |
| 447 | static void soc15_program_aspm(struct amdgpu_device *adev) |
| 448 | { |
| 449 | |
| 450 | if (amdgpu_aspm == 0) |
| 451 | return; |
| 452 | |
| 453 | /* todo */ |
| 454 | } |
| 455 | |
| 456 | static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, |
| 457 | bool enable) |
| 458 | { |
| 459 | nbio_v6_1_enable_doorbell_aperture(adev, enable); |
| 460 | nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); |
| 461 | } |
| 462 | |
| 463 | static const struct amdgpu_ip_block_version vega10_common_ip_block = |
| 464 | { |
| 465 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
| 466 | .major = 2, |
| 467 | .minor = 0, |
| 468 | .rev = 0, |
| 469 | .funcs = &soc15_common_ip_funcs, |
| 470 | }; |
| 471 | |
| 472 | int soc15_set_ip_blocks(struct amdgpu_device *adev) |
| 473 | { |
Xiangliang Yu | 1b92242 | 2017-03-08 15:00:48 +0800 | [diff] [blame] | 474 | nbio_v6_1_detect_hw_virt(adev); |
| 475 | |
Xiangliang Yu | f1a3446 | 2017-03-08 15:06:47 +0800 | [diff] [blame] | 476 | if (amdgpu_sriov_vf(adev)) |
| 477 | adev->virt.ops = &xgpu_ai_virt_ops; |
| 478 | |
Ken Wang | 220ab9b | 2017-03-06 14:49:53 -0500 | [diff] [blame] | 479 | switch (adev->asic_type) { |
| 480 | case CHIP_VEGA10: |
| 481 | amdgpu_ip_block_add(adev, &vega10_common_ip_block); |
| 482 | amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block); |
| 483 | amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block); |
| 484 | amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); |
| 485 | amdgpu_ip_block_add(adev, &vega10_ih_ip_block); |
Xiangliang Yu | 86d3798 | 2017-02-28 16:59:28 +0800 | [diff] [blame] | 486 | if (!amdgpu_sriov_vf(adev)) |
| 487 | amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); |
Ken Wang | 220ab9b | 2017-03-06 14:49:53 -0500 | [diff] [blame] | 488 | amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); |
Xiangliang Yu | 796b656 | 2017-02-28 17:22:03 +0800 | [diff] [blame^] | 489 | if (amdgpu_sriov_vf(adev)) |
| 490 | amdgpu_ip_block_add(adev, &dce_virtual_ip_block); |
Ken Wang | 220ab9b | 2017-03-06 14:49:53 -0500 | [diff] [blame] | 491 | amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); |
| 492 | amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); |
| 493 | amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); |
| 494 | amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); |
| 495 | break; |
| 496 | default: |
| 497 | return -EINVAL; |
| 498 | } |
| 499 | |
| 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) |
| 504 | { |
| 505 | return nbio_v6_1_get_rev_id(adev); |
| 506 | } |
| 507 | |
| 508 | |
| 509 | int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev) |
| 510 | { |
| 511 | /* to be implemented in MC IP*/ |
| 512 | return 0; |
| 513 | } |
| 514 | |
| 515 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
| 516 | { |
| 517 | .read_disabled_bios = &soc15_read_disabled_bios, |
| 518 | .read_bios_from_rom = &soc15_read_bios_from_rom, |
| 519 | .read_register = &soc15_read_register, |
| 520 | .reset = &soc15_asic_reset, |
| 521 | .set_vga_state = &soc15_vga_set_state, |
| 522 | .get_xclk = &soc15_get_xclk, |
| 523 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
| 524 | .set_vce_clocks = &soc15_set_vce_clocks, |
| 525 | .get_config_memsize = &soc15_get_config_memsize, |
| 526 | }; |
| 527 | |
| 528 | static int soc15_common_early_init(void *handle) |
| 529 | { |
| 530 | bool psp_enabled = false; |
| 531 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 532 | |
| 533 | adev->smc_rreg = NULL; |
| 534 | adev->smc_wreg = NULL; |
| 535 | adev->pcie_rreg = &soc15_pcie_rreg; |
| 536 | adev->pcie_wreg = &soc15_pcie_wreg; |
| 537 | adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; |
| 538 | adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; |
| 539 | adev->didt_rreg = &soc15_didt_rreg; |
| 540 | adev->didt_wreg = &soc15_didt_wreg; |
| 541 | |
| 542 | adev->asic_funcs = &soc15_asic_funcs; |
| 543 | |
| 544 | if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && |
| 545 | (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) |
| 546 | psp_enabled = true; |
| 547 | |
| 548 | /* |
| 549 | * nbio need be used for both sdma and gfx9, but only |
| 550 | * initializes once |
| 551 | */ |
| 552 | switch(adev->asic_type) { |
| 553 | case CHIP_VEGA10: |
| 554 | nbio_v6_1_init(adev); |
| 555 | break; |
| 556 | default: |
| 557 | return -EINVAL; |
| 558 | } |
| 559 | |
| 560 | adev->rev_id = soc15_get_rev_id(adev); |
| 561 | adev->external_rev_id = 0xFF; |
| 562 | switch (adev->asic_type) { |
| 563 | case CHIP_VEGA10: |
| 564 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 565 | AMD_CG_SUPPORT_GFX_MGLS | |
| 566 | AMD_CG_SUPPORT_GFX_RLC_LS | |
| 567 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 568 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 569 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 570 | AMD_CG_SUPPORT_GFX_CGCG | |
| 571 | AMD_CG_SUPPORT_GFX_CGLS | |
| 572 | AMD_CG_SUPPORT_BIF_MGCG | |
| 573 | AMD_CG_SUPPORT_BIF_LS | |
| 574 | AMD_CG_SUPPORT_HDP_LS | |
| 575 | AMD_CG_SUPPORT_DRM_MGCG | |
| 576 | AMD_CG_SUPPORT_DRM_LS | |
| 577 | AMD_CG_SUPPORT_ROM_MGCG | |
| 578 | AMD_CG_SUPPORT_DF_MGCG | |
| 579 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 580 | AMD_CG_SUPPORT_SDMA_LS | |
| 581 | AMD_CG_SUPPORT_MC_MGCG | |
| 582 | AMD_CG_SUPPORT_MC_LS; |
| 583 | adev->pg_flags = 0; |
| 584 | adev->external_rev_id = 0x1; |
| 585 | break; |
| 586 | default: |
| 587 | /* FIXME: not supported yet */ |
| 588 | return -EINVAL; |
| 589 | } |
| 590 | |
| 591 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
| 592 | |
| 593 | amdgpu_get_pcie_info(adev); |
| 594 | |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | static int soc15_common_sw_init(void *handle) |
| 599 | { |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | static int soc15_common_sw_fini(void *handle) |
| 604 | { |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | static int soc15_common_hw_init(void *handle) |
| 609 | { |
| 610 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 611 | |
| 612 | /* move the golden regs per IP block */ |
| 613 | soc15_init_golden_registers(adev); |
| 614 | /* enable pcie gen2/3 link */ |
| 615 | soc15_pcie_gen3_enable(adev); |
| 616 | /* enable aspm */ |
| 617 | soc15_program_aspm(adev); |
| 618 | /* enable the doorbell aperture */ |
| 619 | soc15_enable_doorbell_aperture(adev, true); |
| 620 | |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int soc15_common_hw_fini(void *handle) |
| 625 | { |
| 626 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 627 | |
| 628 | /* disable the doorbell aperture */ |
| 629 | soc15_enable_doorbell_aperture(adev, false); |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | static int soc15_common_suspend(void *handle) |
| 635 | { |
| 636 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 637 | |
| 638 | return soc15_common_hw_fini(adev); |
| 639 | } |
| 640 | |
| 641 | static int soc15_common_resume(void *handle) |
| 642 | { |
| 643 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 644 | |
| 645 | return soc15_common_hw_init(adev); |
| 646 | } |
| 647 | |
| 648 | static bool soc15_common_is_idle(void *handle) |
| 649 | { |
| 650 | return true; |
| 651 | } |
| 652 | |
| 653 | static int soc15_common_wait_for_idle(void *handle) |
| 654 | { |
| 655 | return 0; |
| 656 | } |
| 657 | |
| 658 | static int soc15_common_soft_reset(void *handle) |
| 659 | { |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) |
| 664 | { |
| 665 | uint32_t def, data; |
| 666 | |
| 667 | def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); |
| 668 | |
| 669 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) |
| 670 | data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; |
| 671 | else |
| 672 | data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; |
| 673 | |
| 674 | if (def != data) |
| 675 | WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); |
| 676 | } |
| 677 | |
| 678 | static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) |
| 679 | { |
| 680 | uint32_t def, data; |
| 681 | |
| 682 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); |
| 683 | |
| 684 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) |
| 685 | data &= ~(0x01000000 | |
| 686 | 0x02000000 | |
| 687 | 0x04000000 | |
| 688 | 0x08000000 | |
| 689 | 0x10000000 | |
| 690 | 0x20000000 | |
| 691 | 0x40000000 | |
| 692 | 0x80000000); |
| 693 | else |
| 694 | data |= (0x01000000 | |
| 695 | 0x02000000 | |
| 696 | 0x04000000 | |
| 697 | 0x08000000 | |
| 698 | 0x10000000 | |
| 699 | 0x20000000 | |
| 700 | 0x40000000 | |
| 701 | 0x80000000); |
| 702 | |
| 703 | if (def != data) |
| 704 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); |
| 705 | } |
| 706 | |
| 707 | static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) |
| 708 | { |
| 709 | uint32_t def, data; |
| 710 | |
| 711 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); |
| 712 | |
| 713 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) |
| 714 | data |= 1; |
| 715 | else |
| 716 | data &= ~1; |
| 717 | |
| 718 | if (def != data) |
| 719 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); |
| 720 | } |
| 721 | |
| 722 | static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, |
| 723 | bool enable) |
| 724 | { |
| 725 | uint32_t def, data; |
| 726 | |
| 727 | def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); |
| 728 | |
| 729 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) |
| 730 | data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | |
| 731 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); |
| 732 | else |
| 733 | data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | |
| 734 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; |
| 735 | |
| 736 | if (def != data) |
| 737 | WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); |
| 738 | } |
| 739 | |
| 740 | static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev, |
| 741 | bool enable) |
| 742 | { |
| 743 | uint32_t data; |
| 744 | |
| 745 | /* Put DF on broadcast mode */ |
| 746 | data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl)); |
| 747 | data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; |
| 748 | WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data); |
| 749 | |
| 750 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { |
| 751 | data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); |
| 752 | data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; |
| 753 | data |= DF_MGCG_ENABLE_15_CYCLE_DELAY; |
| 754 | WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); |
| 755 | } else { |
| 756 | data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); |
| 757 | data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; |
| 758 | data |= DF_MGCG_DISABLE; |
| 759 | WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); |
| 760 | } |
| 761 | |
| 762 | WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), |
| 763 | mmFabricConfigAccessControl_DEFAULT); |
| 764 | } |
| 765 | |
| 766 | static int soc15_common_set_clockgating_state(void *handle, |
| 767 | enum amd_clockgating_state state) |
| 768 | { |
| 769 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 770 | |
| 771 | switch (adev->asic_type) { |
| 772 | case CHIP_VEGA10: |
| 773 | nbio_v6_1_update_medium_grain_clock_gating(adev, |
| 774 | state == AMD_CG_STATE_GATE ? true : false); |
| 775 | nbio_v6_1_update_medium_grain_light_sleep(adev, |
| 776 | state == AMD_CG_STATE_GATE ? true : false); |
| 777 | soc15_update_hdp_light_sleep(adev, |
| 778 | state == AMD_CG_STATE_GATE ? true : false); |
| 779 | soc15_update_drm_clock_gating(adev, |
| 780 | state == AMD_CG_STATE_GATE ? true : false); |
| 781 | soc15_update_drm_light_sleep(adev, |
| 782 | state == AMD_CG_STATE_GATE ? true : false); |
| 783 | soc15_update_rom_medium_grain_clock_gating(adev, |
| 784 | state == AMD_CG_STATE_GATE ? true : false); |
| 785 | soc15_update_df_medium_grain_clock_gating(adev, |
| 786 | state == AMD_CG_STATE_GATE ? true : false); |
| 787 | break; |
| 788 | default: |
| 789 | break; |
| 790 | } |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | static int soc15_common_set_powergating_state(void *handle, |
| 795 | enum amd_powergating_state state) |
| 796 | { |
| 797 | /* todo */ |
| 798 | return 0; |
| 799 | } |
| 800 | |
| 801 | const struct amd_ip_funcs soc15_common_ip_funcs = { |
| 802 | .name = "soc15_common", |
| 803 | .early_init = soc15_common_early_init, |
| 804 | .late_init = NULL, |
| 805 | .sw_init = soc15_common_sw_init, |
| 806 | .sw_fini = soc15_common_sw_fini, |
| 807 | .hw_init = soc15_common_hw_init, |
| 808 | .hw_fini = soc15_common_hw_fini, |
| 809 | .suspend = soc15_common_suspend, |
| 810 | .resume = soc15_common_resume, |
| 811 | .is_idle = soc15_common_is_idle, |
| 812 | .wait_for_idle = soc15_common_wait_for_idle, |
| 813 | .soft_reset = soc15_common_soft_reset, |
| 814 | .set_clockgating_state = soc15_common_set_clockgating_state, |
| 815 | .set_powergating_state = soc15_common_set_powergating_state, |
| 816 | }; |