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gerrit-public.fairphone.software / kernel / msm-4.19 / 7ab0a48420c95dc4099d1777a5a24dffad102cf1 / . / arch / arm / boot / dts / wm8505.dtsi
blob: bcf668d31b28471602dc86c2b1555c9bcbb73be6 [file] [log] [blame]
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]1/*
2 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8505";
13
14 cpus {
15 cpu@0 {
16 compatible = "arm,arm926ejs";
17 };
18 };
19
20 soc {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 compatible = "simple-bus";
24 ranges;
25 interrupt-parent = <&intc0>;
26
27 intc0: interrupt-controller@d8140000 {
28 compatible = "via,vt8500-intc";
29 interrupt-controller;
30 reg = <0xd8140000 0x10000>;
31 #interrupt-cells = <1>;
32 };
33
34 /* Secondary IC cascaded to intc0 */
35 intc1: interrupt-controller@d8150000 {
36 compatible = "via,vt8500-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xD8150000 0x10000>;
40 interrupts = <56 57 58 59 60 61 62 63>;
41 };
42
43 gpio: gpio-controller@d8110000 {
44 compatible = "wm,wm8505-gpio";
45 gpio-controller;
46 reg = <0xd8110000 0x10000>;
47 #gpio-cells = <3>;
48 };
49
50 pmc@d8130000 {
51 compatible = "via,vt8500-pmc";
52 reg = <0xd8130000 0x1000>;
53 clocks {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 ref24: ref24M {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]62
63 clkuart0: uart0 {
64 #clock-cells = <0>;
65 compatible = "via,vt8500-device-clock";
66 clocks = <&ref24>;
67 enable-reg = <0x250>;
68 enable-bit = <1>;
69 };
70
71 clkuart1: uart1 {
72 #clock-cells = <0>;
73 compatible = "via,vt8500-device-clock";
74 clocks = <&ref24>;
75 enable-reg = <0x250>;
76 enable-bit = <2>;
77 };
78
79 clkuart2: uart2 {
80 #clock-cells = <0>;
81 compatible = "via,vt8500-device-clock";
82 clocks = <&ref24>;
83 enable-reg = <0x250>;
84 enable-bit = <3>;
85 };
86
87 clkuart3: uart3 {
88 #clock-cells = <0>;
89 compatible = "via,vt8500-device-clock";
90 clocks = <&ref24>;
91 enable-reg = <0x250>;
92 enable-bit = <4>;
93 };
94
95 clkuart4: uart4 {
96 #clock-cells = <0>;
97 compatible = "via,vt8500-device-clock";
98 clocks = <&ref24>;
99 enable-reg = <0x250>;
100 enable-bit = <22>;
101 };
102
103 clkuart5: uart5 {
104 #clock-cells = <0>;
105 compatible = "via,vt8500-device-clock";
106 clocks = <&ref24>;
107 enable-reg = <0x250>;
108 enable-bit = <23>;
109 };
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]110 };
111 };
112
113 timer@d8130100 {
114 compatible = "via,vt8500-timer";
115 reg = <0xd8130100 0x28>;
116 interrupts = <36>;
117 };
118
119 ehci@d8007100 {
120 compatible = "via,vt8500-ehci";
121 reg = <0xd8007100 0x200>;
Tony Prisk5448a272012-10-13 17:18:02 +1300[diff] [blame]122 interrupts = <1>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]123 };
124
125 uhci@d8007300 {
126 compatible = "platform-uhci";
127 reg = <0xd8007300 0x200>;
Tony Prisk5448a272012-10-13 17:18:02 +1300[diff] [blame]128 interrupts = <0>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]129 };
130
Tony Prisk7ab0a482013-04-03 07:20:38 +1300[diff] [blame^]131 fb: fb@d8050800 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]132 compatible = "wm,wm8505-fb";
133 reg = <0xd8050800 0x200>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]134 };
135
136 ge_rops@d8050400 {
137 compatible = "wm,prizm-ge-rops";
138 reg = <0xd8050400 0x100>;
139 };
140
141 uart@d8200000 {
142 compatible = "via,vt8500-uart";
143 reg = <0xd8200000 0x1040>;
144 interrupts = <32>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]145 clocks = <&clkuart0>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]146 };
147
148 uart@d82b0000 {
149 compatible = "via,vt8500-uart";
150 reg = <0xd82b0000 0x1040>;
151 interrupts = <33>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]152 clocks = <&clkuart1>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]153 };
154
155 uart@d8210000 {
156 compatible = "via,vt8500-uart";
157 reg = <0xd8210000 0x1040>;
158 interrupts = <47>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]159 clocks = <&clkuart2>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]160 };
161
162 uart@d82c0000 {
163 compatible = "via,vt8500-uart";
164 reg = <0xd82c0000 0x1040>;
165 interrupts = <50>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]166 clocks = <&clkuart3>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]167 };
168
169 uart@d8370000 {
170 compatible = "via,vt8500-uart";
171 reg = <0xd8370000 0x1040>;
172 interrupts = <31>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]173 clocks = <&clkuart4>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]174 };
175
176 uart@d8380000 {
177 compatible = "via,vt8500-uart";
178 reg = <0xd8380000 0x1040>;
179 interrupts = <30>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]180 clocks = <&clkuart5>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]181 };
182
183 rtc@d8100000 {
184 compatible = "via,vt8500-rtc";
185 reg = <0xd8100000 0x10000>;
186 interrupts = <48>;
187 };
188 };
189};