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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/ppc/platforms/4xx/ibm440gp.c
3 *
4 * PPC440GP I/O descriptions
5 *
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002-2004 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440gp.h>
21#include <asm/ocp.h>
22#include <asm/ppc4xx_pic.h>
23
24static struct ocp_func_emac_data ibm440gp_emac0_def = {
25 .rgmii_idx = -1, /* No RGMII */
26 .rgmii_mux = -1, /* No RGMII */
27 .zmii_idx = 0, /* ZMII device index */
28 .zmii_mux = 0, /* ZMII input of this EMAC */
29 .mal_idx = 0, /* MAL device index */
30 .mal_rx_chan = 0, /* MAL rx channel number */
31 .mal_tx_chan = 0, /* MAL tx channel number */
32 .wol_irq = 61, /* WOL interrupt number */
33 .mdio_idx = -1, /* No shared MDIO */
34 .tah_idx = -1, /* No TAH */
35};
36
37static struct ocp_func_emac_data ibm440gp_emac1_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = 0, /* ZMII device index */
41 .zmii_mux = 1, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 1, /* MAL rx channel number */
44 .mal_tx_chan = 2, /* MAL tx channel number */
45 .wol_irq = 63, /* WOL interrupt number */
46 .mdio_idx = -1, /* No shared MDIO */
47 .tah_idx = -1, /* No TAH */
48};
49OCP_SYSFS_EMAC_DATA()
50
51static struct ocp_func_mal_data ibm440gp_mal0_def = {
52 .num_tx_chans = 4, /* Number of TX channels */
53 .num_rx_chans = 2, /* Number of RX channels */
54 .txeob_irq = 10, /* TX End Of Buffer IRQ */
55 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
56 .txde_irq = 33, /* TX Descriptor Error IRQ */
57 .rxde_irq = 34, /* RX Descriptor Error IRQ */
58 .serr_irq = 32, /* MAL System Error IRQ */
Eugene Surovegin3a0a4012005-09-03 15:55:53 -070059 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
Linus Torvalds1da177e2005-04-16 15:20:36 -070060};
61OCP_SYSFS_MAL_DATA()
62
63static struct ocp_func_iic_data ibm440gp_iic0_def = {
64 .fast_mode = 0, /* Use standad mode (100Khz) */
65};
66
67static struct ocp_func_iic_data ibm440gp_iic1_def = {
68 .fast_mode = 0, /* Use standad mode (100Khz) */
69};
70OCP_SYSFS_IIC_DATA()
71
72struct ocp_def core_ocp[] = {
73 { .vendor = OCP_VENDOR_IBM,
74 .function = OCP_FUNC_OPB,
75 .index = 0,
76 .paddr = 0x0000000140000000ULL,
77 .irq = OCP_IRQ_NA,
78 .pm = OCP_CPM_NA,
79 },
80 { .vendor = OCP_VENDOR_IBM,
81 .function = OCP_FUNC_16550,
82 .index = 0,
83 .paddr = PPC440GP_UART0_ADDR,
84 .irq = UART0_INT,
85 .pm = IBM_CPM_UART0,
86 },
87 { .vendor = OCP_VENDOR_IBM,
88 .function = OCP_FUNC_16550,
89 .index = 1,
90 .paddr = PPC440GP_UART1_ADDR,
91 .irq = UART1_INT,
92 .pm = IBM_CPM_UART1,
93 },
94 { .vendor = OCP_VENDOR_IBM,
95 .function = OCP_FUNC_IIC,
96 .index = 0,
97 .paddr = 0x0000000140000400ULL,
98 .irq = 2,
99 .pm = IBM_CPM_IIC0,
100 .additions = &ibm440gp_iic0_def,
101 .show = &ocp_show_iic_data
102 },
103 { .vendor = OCP_VENDOR_IBM,
104 .function = OCP_FUNC_IIC,
105 .index = 1,
106 .paddr = 0x0000000140000500ULL,
107 .irq = 3,
108 .pm = IBM_CPM_IIC1,
109 .additions = &ibm440gp_iic1_def,
110 .show = &ocp_show_iic_data
111 },
112 { .vendor = OCP_VENDOR_IBM,
113 .function = OCP_FUNC_GPIO,
114 .index = 0,
115 .paddr = 0x0000000140000700ULL,
116 .irq = OCP_IRQ_NA,
117 .pm = IBM_CPM_GPIO0,
118 },
119 { .vendor = OCP_VENDOR_IBM,
120 .function = OCP_FUNC_MAL,
121 .paddr = OCP_PADDR_NA,
122 .irq = OCP_IRQ_NA,
123 .pm = OCP_CPM_NA,
124 .additions = &ibm440gp_mal0_def,
125 .show = &ocp_show_mal_data,
126 },
127 { .vendor = OCP_VENDOR_IBM,
128 .function = OCP_FUNC_EMAC,
129 .index = 0,
130 .paddr = 0x0000000140000800ULL,
131 .irq = 60,
132 .pm = OCP_CPM_NA,
133 .additions = &ibm440gp_emac0_def,
134 .show = &ocp_show_emac_data,
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_EMAC,
138 .index = 1,
139 .paddr = 0x0000000140000900ULL,
140 .irq = 62,
141 .pm = OCP_CPM_NA,
142 .additions = &ibm440gp_emac1_def,
143 .show = &ocp_show_emac_data,
144 },
145 { .vendor = OCP_VENDOR_IBM,
146 .function = OCP_FUNC_ZMII,
147 .paddr = 0x0000000140000780ULL,
148 .irq = OCP_IRQ_NA,
149 .pm = OCP_CPM_NA,
150 },
151 { .vendor = OCP_VENDOR_INVALID
152 }
153};
154
155/* Polarity and triggering settings for internal interrupt sources */
156struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
157 { .polarity = 0xfffffe03,
158 .triggering = 0x01c00000,
159 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
160 },
161 { .polarity = 0xffffc0ff,
162 .triggering = 0x00ff8000,
163 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
164 },
165};