blob: adf175f614961cebcb6d1bf89fbe7810471da68d [file] [log] [blame]
Len Brown103a8fe2010-10-22 23:53:03 -04001.TH TURBOSTAT 8
2.SH NAME
3turbostat \- Report processor frequency and idle statistics
4.SH SYNOPSIS
5.ft B
6.B turbostat
Len Browne23da032012-02-06 18:37:16 -05007.RB [ "\-s" ]
Len Brown103a8fe2010-10-22 23:53:03 -04008.RB [ "\-v" ]
9.RB [ "\-M MSR#" ]
10.RB command
11.br
12.B turbostat
Len Browne23da032012-02-06 18:37:16 -050013.RB [ "\-s" ]
Len Brown103a8fe2010-10-22 23:53:03 -040014.RB [ "\-v" ]
15.RB [ "\-M MSR#" ]
16.RB [ "\-i interval_sec" ]
17.SH DESCRIPTION
18\fBturbostat \fP reports processor topology, frequency
19and idle power state statistics on modern X86 processors.
20Either \fBcommand\fP is forked and statistics are printed
21upon its completion, or statistics are printed periodically.
22
23\fBturbostat \fP
24requires that the processor
25supports an "invariant" TSC, plus the APERF and MPERF MSRs.
26\fBturbostat \fP will report idle cpu power state residency
27on processors that additionally support C-state residency counters.
28
29.SS Options
Len Browne23da032012-02-06 18:37:16 -050030The \fB-s\fP option prints only a 1-line summary for each sample interval.
31.PP
Len Brown103a8fe2010-10-22 23:53:03 -040032The \fB-v\fP option increases verbosity.
33.PP
34The \fB-M MSR#\fP option dumps the specified MSR,
35in addition to the usual frequency and idle statistics.
36.PP
37The \fB-i interval_sec\fP option prints statistics every \fiinterval_sec\fP seconds.
38The default is 5 seconds.
39.PP
40The \fBcommand\fP parameter forks \fBcommand\fP and upon its exit,
41displays the statistics gathered since it was forked.
42.PP
43.SH FIELD DESCRIPTIONS
44.nf
Arun Thomas9b6cf1a2011-08-17 00:34:14 +020045\fBpk\fP processor package number.
Len Browne23da032012-02-06 18:37:16 -050046\fBcor\fP processor core number.
Len Brown103a8fe2010-10-22 23:53:03 -040047\fBCPU\fP Linux CPU (logical processor) number.
Len Browne23da032012-02-06 18:37:16 -050048Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading Technology.
Len Brown103a8fe2010-10-22 23:53:03 -040049\fB%c0\fP percent of the interval that the CPU retired instructions.
50\fBGHz\fP average clock rate while the CPU was in c0 state.
51\fBTSC\fP average GHz that the TSC ran during the entire interval.
Len Browne23da032012-02-06 18:37:16 -050052\fB%c1, %c3, %c6, %c7\fP show the percentage residency in hardware core idle states.
53\fB%pc2, %pc3, %pc6, %pc7\fP percentage residency in hardware package idle states.
Len Brown103a8fe2010-10-22 23:53:03 -040054.fi
55.PP
56.SH EXAMPLE
57Without any parameters, turbostat prints out counters ever 5 seconds.
58(override interval with "-i sec" option, or specify a command
59for turbostat to fork).
60
Len Browne23da032012-02-06 18:37:16 -050061The first row of statistics is a summary for the entire system.
62Note that the summary is a weighted average.
Len Brown103a8fe2010-10-22 23:53:03 -040063Subsequent rows show per-CPU statistics.
64
65.nf
66[root@x980]# ./turbostat
Len Browne23da032012-02-06 18:37:16 -050067cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
68 0.60 1.63 3.38 2.91 0.00 96.49 0.00 76.64
69 0 0 0.59 1.62 3.38 4.51 0.00 94.90 0.00 76.64
70 0 6 1.13 1.64 3.38 3.97 0.00 94.90 0.00 76.64
71 1 2 0.08 1.62 3.38 0.07 0.00 99.85 0.00 76.64
72 1 8 0.03 1.62 3.38 0.12 0.00 99.85 0.00 76.64
73 2 4 0.01 1.62 3.38 0.06 0.00 99.93 0.00 76.64
74 2 10 0.04 1.62 3.38 0.02 0.00 99.93 0.00 76.64
75 8 1 2.85 1.62 3.38 11.71 0.00 85.44 0.00 76.64
76 8 7 1.98 1.62 3.38 12.58 0.00 85.44 0.00 76.64
77 9 3 0.36 1.62 3.38 0.71 0.00 98.93 0.00 76.64
78 9 9 0.09 1.62 3.38 0.98 0.00 98.93 0.00 76.64
79 10 5 0.03 1.62 3.38 0.09 0.00 99.87 0.00 76.64
80 10 11 0.07 1.62 3.38 0.06 0.00 99.87 0.00 76.64
81.fi
82.SH SUMMARY EXAMPLE
83The "-s" option prints the column headers just once,
84and then the one line system summary for each sample interval.
85
86.nf
87[root@x980]# ./turbostat -s
88 %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
89 0.61 1.89 3.38 5.95 0.00 93.44 0.00 66.33
90 0.52 1.62 3.38 6.83 0.00 92.65 0.00 61.11
91 0.62 1.92 3.38 5.47 0.00 93.91 0.00 67.31
Len Brown103a8fe2010-10-22 23:53:03 -040092.fi
93.SH VERBOSE EXAMPLE
94The "-v" option adds verbosity to the output:
95
96.nf
97GenuineIntel 11 CPUID levels; family:model:stepping 0x6:2c:2 (6:44:2)
9812 * 133 = 1600 MHz max efficiency
9925 * 133 = 3333 MHz TSC frequency
10026 * 133 = 3467 MHz max turbo 4 active cores
10126 * 133 = 3467 MHz max turbo 3 active cores
10227 * 133 = 3600 MHz max turbo 2 active cores
10327 * 133 = 3600 MHz max turbo 1 active cores
104
105.fi
106The \fBmax efficiency\fP frequency, a.k.a. Low Frequency Mode, is the frequency
107available at the minimum package voltage. The \fBTSC frequency\fP is the nominal
108maximum frequency of the processor if turbo-mode were not available. This frequency
109should be sustainable on all CPUs indefinitely, given nominal power and cooling.
110The remaining rows show what maximum turbo frequency is possible
111depending on the number of idle cores. Note that this information is
112not available on all processors.
113.SH FORK EXAMPLE
114If turbostat is invoked with a command, it will fork that command
115and output the statistics gathered when the command exits.
116eg. Here a cycle soaker is run on 1 CPU (see %c0) for a few seconds
117until ^C while the other CPUs are mostly idle:
118
119.nf
120[root@x980 lenb]# ./turbostat cat /dev/zero > /dev/null
Len Browne23da032012-02-06 18:37:16 -0500121^C
122cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
123 8.63 3.64 3.38 14.46 0.49 76.42 0.00 0.00
124 0 0 0.34 3.36 3.38 99.66 0.00 0.00 0.00 0.00
125 0 6 99.96 3.64 3.38 0.04 0.00 0.00 0.00 0.00
126 1 2 0.14 3.50 3.38 1.75 2.04 96.07 0.00 0.00
127 1 8 0.38 3.57 3.38 1.51 2.04 96.07 0.00 0.00
128 2 4 0.01 2.65 3.38 0.06 0.00 99.93 0.00 0.00
129 2 10 0.03 2.12 3.38 0.04 0.00 99.93 0.00 0.00
130 8 1 0.91 3.59 3.38 35.27 0.92 62.90 0.00 0.00
131 8 7 1.61 3.63 3.38 34.57 0.92 62.90 0.00 0.00
132 9 3 0.04 3.38 3.38 0.20 0.00 99.76 0.00 0.00
133 9 9 0.04 3.29 3.38 0.20 0.00 99.76 0.00 0.00
134 10 5 0.03 3.08 3.38 0.12 0.00 99.85 0.00 0.00
135 10 11 0.05 3.07 3.38 0.10 0.00 99.85 0.00 0.00
1364.907015 sec
Len Brown103a8fe2010-10-22 23:53:03 -0400137
138.fi
Len Browne23da032012-02-06 18:37:16 -0500139Above the cycle soaker drives cpu6 up 3.6 Ghz turbo limit
Len Brown103a8fe2010-10-22 23:53:03 -0400140while the other processors are generally in various states of idle.
141
Len Browne23da032012-02-06 18:37:16 -0500142Note that cpu0 is an HT sibling sharing core0
143with cpu6, and thus it is unable to get to an idle state
144deeper than c1 while cpu6 is busy.
Len Brown103a8fe2010-10-22 23:53:03 -0400145
Len Browne23da032012-02-06 18:37:16 -0500146Note that turbostat reports average GHz of 3.64, while
147the arithmetic average of the GHz column above is lower.
Len Brown103a8fe2010-10-22 23:53:03 -0400148This is a weighted average, where the weight is %c0. ie. it is the total number of
149un-halted cycles elapsed per time divided by the number of CPUs.
150.SH NOTES
151
152.B "turbostat "
153must be run as root.
154
155.B "turbostat "
156reads hardware counters, but doesn't write them.
157So it will not interfere with the OS or other programs, including
158multiple invocations of itself.
159
160\fBturbostat \fP
161may work poorly on Linux-2.6.20 through 2.6.29,
162as \fBacpi-cpufreq \fPperiodically cleared the APERF and MPERF
163in those kernels.
164
165The APERF, MPERF MSRs are defined to count non-halted cycles.
166Although it is not guaranteed by the architecture, turbostat assumes
167that they count at TSC rate, which is true on all processors tested to date.
168
169.SH REFERENCES
170"Intel® Turbo Boost Technology
171in Intel® Core™ Microarchitecture (Nehalem) Based Processors"
172http://download.intel.com/design/processor/applnots/320354.pdf
173
174"Intel® 64 and IA-32 Architectures Software Developer's Manual
175Volume 3B: System Programming Guide"
176http://www.intel.com/products/processor/manuals/
177
178.SH FILES
179.ta
180.nf
181/dev/cpu/*/msr
182.fi
183
184.SH "SEE ALSO"
185msr(4), vmstat(8)
186.PP
Len Browne23da032012-02-06 18:37:16 -0500187.SH AUTHOR
Len Brown103a8fe2010-10-22 23:53:03 -0400188.nf
189Written by Len Brown <len.brown@intel.com>