blob: 4393c4565fe596d0ad4b750aa6ae4eb92c52d3db [file] [log] [blame]
Dinh Nguyen66314222012-07-18 16:07:18 -06001/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
Steffen Trumtrar7da9b432014-04-02 21:31:31 -050018#include "skeleton.dtsi"
Dinh Nguyen66314222012-07-18 16:07:18 -060019
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
Dinh Nguyen3d954cf2013-06-05 10:02:53 -050026 ethernet1 = &gmac1;
Dinh Nguyen66314222012-07-18 16:07:18 -060027 serial0 = &uart0;
28 serial1 = &uart1;
Dinh Nguyenc2ad2842013-02-11 17:30:30 -060029 timer0 = &timer0;
30 timer1 = &timer1;
31 timer2 = &timer2;
32 timer3 = &timer3;
Dinh Nguyen66314222012-07-18 16:07:18 -060033 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,cortex-a9";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 reg = <1>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: intc@fffed000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 interrupt-controller;
57 reg = <0xfffed000 0x1000>,
58 <0xfffec100 0x100>;
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 device_type = "soc";
66 interrupt-parent = <&intc>;
67 ranges;
68
69 amba {
70 compatible = "arm,amba-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 pdma: pdma@ffe01000 {
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
Steffen Trumtrar18d56192014-04-02 10:40:30 -050078 interrupts = <0 104 4>,
79 <0 105 4>,
80 <0 106 4>,
81 <0 107 4>,
82 <0 108 4>,
83 <0 109 4>,
84 <0 110 4>,
85 <0 111 4>;
Padmavathi Venna0d8abbf2013-03-04 11:04:28 +053086 #dma-cells = <1>;
87 #dma-channels = <8>;
88 #dma-requests = <32>;
Steffen Trumtrar672ef902014-01-08 12:01:26 -060089 clocks = <&l4_main_clk>;
90 clock-names = "apb_pclk";
Dinh Nguyen66314222012-07-18 16:07:18 -060091 };
92 };
93
Steffen Trumtrar36fe3f52014-04-02 11:11:26 -050094 can0: can@ffc00000 {
95 compatible = "bosch,d_can";
96 reg = <0xffc00000 0x1000>;
97 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
98 clocks = <&can0_clk>;
99 status = "disabled";
100 };
101
102 can1: can@ffc01000 {
103 compatible = "bosch,d_can";
104 reg = <0xffc01000 0x1000>;
105 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
106 clocks = <&can1_clk>;
107 status = "disabled";
108 };
109
Dinh Nguyen042000b2013-04-11 10:55:25 -0500110 clkmgr@ffd04000 {
111 compatible = "altr,clk-mgr";
112 reg = <0xffd04000 0x1000>;
113
114 clocks {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
Dinh Nguyenf1ce1a92014-02-19 14:56:38 -0600118 osc1: osc1 {
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 };
122
123 osc2: osc2 {
Dinh Nguyen042000b2013-04-11 10:55:25 -0500124 #clock-cells = <0>;
125 compatible = "fixed-clock";
126 };
127
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500128 f2s_periph_ref_clk: f2s_periph_ref_clk {
129 #clock-cells = <0>;
130 compatible = "fixed-clock";
Dinh Nguyenf1ce1a92014-02-19 14:56:38 -0600131 };
132
133 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500136 };
137
Dinh Nguyen042000b2013-04-11 10:55:25 -0500138 main_pll: main_pll {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 #clock-cells = <0>;
142 compatible = "altr,socfpga-pll-clock";
Dinh Nguyenf1ce1a92014-02-19 14:56:38 -0600143 clocks = <&osc1>;
Dinh Nguyen042000b2013-04-11 10:55:25 -0500144 reg = <0x40>;
145
146 mpuclk: mpuclk {
147 #clock-cells = <0>;
148 compatible = "altr,socfpga-perip-clk";
149 clocks = <&main_pll>;
150 fixed-divider = <2>;
151 reg = <0x48>;
152 };
153
154 mainclk: mainclk {
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
158 fixed-divider = <4>;
159 reg = <0x4C>;
160 };
161
162 dbg_base_clk: dbg_base_clk {
163 #clock-cells = <0>;
164 compatible = "altr,socfpga-perip-clk";
165 clocks = <&main_pll>;
166 fixed-divider = <4>;
167 reg = <0x50>;
168 };
169
170 main_qspi_clk: main_qspi_clk {
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-perip-clk";
173 clocks = <&main_pll>;
174 reg = <0x54>;
175 };
176
177 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
178 #clock-cells = <0>;
179 compatible = "altr,socfpga-perip-clk";
180 clocks = <&main_pll>;
181 reg = <0x58>;
182 };
183
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500184 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
Dinh Nguyen042000b2013-04-11 10:55:25 -0500185 #clock-cells = <0>;
186 compatible = "altr,socfpga-perip-clk";
187 clocks = <&main_pll>;
188 reg = <0x5C>;
189 };
190 };
191
192 periph_pll: periph_pll {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-pll-clock";
Dinh Nguyenf1ce1a92014-02-19 14:56:38 -0600197 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
Dinh Nguyen042000b2013-04-11 10:55:25 -0500198 reg = <0x80>;
199
200 emac0_clk: emac0_clk {
201 #clock-cells = <0>;
202 compatible = "altr,socfpga-perip-clk";
203 clocks = <&periph_pll>;
204 reg = <0x88>;
205 };
206
207 emac1_clk: emac1_clk {
208 #clock-cells = <0>;
209 compatible = "altr,socfpga-perip-clk";
210 clocks = <&periph_pll>;
211 reg = <0x8C>;
212 };
213
214 per_qspi_clk: per_qsi_clk {
215 #clock-cells = <0>;
216 compatible = "altr,socfpga-perip-clk";
217 clocks = <&periph_pll>;
218 reg = <0x90>;
219 };
220
221 per_nand_mmc_clk: per_nand_mmc_clk {
222 #clock-cells = <0>;
223 compatible = "altr,socfpga-perip-clk";
224 clocks = <&periph_pll>;
225 reg = <0x94>;
226 };
227
228 per_base_clk: per_base_clk {
229 #clock-cells = <0>;
230 compatible = "altr,socfpga-perip-clk";
231 clocks = <&periph_pll>;
232 reg = <0x98>;
233 };
234
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500235 h2f_usr1_clk: h2f_usr1_clk {
Dinh Nguyen042000b2013-04-11 10:55:25 -0500236 #clock-cells = <0>;
237 compatible = "altr,socfpga-perip-clk";
238 clocks = <&periph_pll>;
239 reg = <0x9C>;
240 };
241 };
242
243 sdram_pll: sdram_pll {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 #clock-cells = <0>;
247 compatible = "altr,socfpga-pll-clock";
Dinh Nguyenf1ce1a92014-02-19 14:56:38 -0600248 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
Dinh Nguyen042000b2013-04-11 10:55:25 -0500249 reg = <0xC0>;
250
251 ddr_dqs_clk: ddr_dqs_clk {
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-perip-clk";
254 clocks = <&sdram_pll>;
255 reg = <0xC8>;
256 };
257
258 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-perip-clk";
261 clocks = <&sdram_pll>;
262 reg = <0xCC>;
263 };
264
265 ddr_dq_clk: ddr_dq_clk {
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-perip-clk";
268 clocks = <&sdram_pll>;
269 reg = <0xD0>;
270 };
271
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500272 h2f_usr2_clk: h2f_usr2_clk {
Dinh Nguyen042000b2013-04-11 10:55:25 -0500273 #clock-cells = <0>;
274 compatible = "altr,socfpga-perip-clk";
275 clocks = <&sdram_pll>;
276 reg = <0xD4>;
277 };
278 };
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500279
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500280 mpu_periph_clk: mpu_periph_clk {
281 #clock-cells = <0>;
Dinh Nguyena5c6e872013-12-03 14:32:10 -0600282 compatible = "altr,socfpga-perip-clk";
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500283 clocks = <&mpuclk>;
284 fixed-divider = <4>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500285 };
286
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500287 mpu_l2_ram_clk: mpu_l2_ram_clk {
288 #clock-cells = <0>;
Dinh Nguyena5c6e872013-12-03 14:32:10 -0600289 compatible = "altr,socfpga-perip-clk";
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500290 clocks = <&mpuclk>;
291 fixed-divider = <2>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500292 };
293
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500294 l4_main_clk: l4_main_clk {
295 #clock-cells = <0>;
296 compatible = "altr,socfpga-gate-clk";
297 clocks = <&mainclk>;
298 clk-gate = <0x60 0>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500299 };
300
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500301 l3_main_clk: l3_main_clk {
302 #clock-cells = <0>;
Dinh Nguyena5c6e872013-12-03 14:32:10 -0600303 compatible = "altr,socfpga-perip-clk";
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500304 clocks = <&mainclk>;
Dinh Nguyena5c6e872013-12-03 14:32:10 -0600305 fixed-divider = <1>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500306 };
307
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500308 l3_mp_clk: l3_mp_clk {
309 #clock-cells = <0>;
310 compatible = "altr,socfpga-gate-clk";
311 clocks = <&mainclk>;
312 div-reg = <0x64 0 2>;
313 clk-gate = <0x60 1>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500314 };
315
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500316 l3_sp_clk: l3_sp_clk {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-gate-clk";
319 clocks = <&mainclk>;
320 div-reg = <0x64 2 2>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500321 };
322
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500323 l4_mp_clk: l4_mp_clk {
324 #clock-cells = <0>;
325 compatible = "altr,socfpga-gate-clk";
326 clocks = <&mainclk>, <&per_base_clk>;
327 div-reg = <0x64 4 3>;
328 clk-gate = <0x60 2>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500329 };
330
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500331 l4_sp_clk: l4_sp_clk {
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&mainclk>, <&per_base_clk>;
335 div-reg = <0x64 7 3>;
336 clk-gate = <0x60 3>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500337 };
338
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500339 dbg_at_clk: dbg_at_clk {
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&dbg_base_clk>;
343 div-reg = <0x68 0 2>;
344 clk-gate = <0x60 4>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500345 };
346
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500347 dbg_clk: dbg_clk {
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&dbg_base_clk>;
351 div-reg = <0x68 2 2>;
352 clk-gate = <0x60 5>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500353 };
354
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500355 dbg_trace_clk: dbg_trace_clk {
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-gate-clk";
358 clocks = <&dbg_base_clk>;
359 div-reg = <0x6C 0 3>;
360 clk-gate = <0x60 6>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500361 };
362
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500363 dbg_timer_clk: dbg_timer_clk {
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&dbg_base_clk>;
367 clk-gate = <0x60 7>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500368 };
369
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500370 cfg_clk: cfg_clk {
371 #clock-cells = <0>;
372 compatible = "altr,socfpga-gate-clk";
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500373 clocks = <&cfg_h2f_usr0_clk>;
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500374 clk-gate = <0x60 8>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500375 };
376
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500377 h2f_user0_clk: h2f_user0_clk {
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500378 #clock-cells = <0>;
379 compatible = "altr,socfpga-gate-clk";
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500380 clocks = <&cfg_h2f_usr0_clk>;
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500381 clk-gate = <0x60 9>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500382 };
383
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500384 emac_0_clk: emac_0_clk {
385 #clock-cells = <0>;
386 compatible = "altr,socfpga-gate-clk";
387 clocks = <&emac0_clk>;
388 clk-gate = <0xa0 0>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500389 };
390
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500391 emac_1_clk: emac_1_clk {
392 #clock-cells = <0>;
393 compatible = "altr,socfpga-gate-clk";
394 clocks = <&emac1_clk>;
395 clk-gate = <0xa0 1>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500396 };
397
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500398 usb_mp_clk: usb_mp_clk {
399 #clock-cells = <0>;
400 compatible = "altr,socfpga-gate-clk";
401 clocks = <&per_base_clk>;
402 clk-gate = <0xa0 2>;
403 div-reg = <0xa4 0 3>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500404 };
405
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500406 spi_m_clk: spi_m_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&per_base_clk>;
410 clk-gate = <0xa0 3>;
411 div-reg = <0xa4 3 3>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500412 };
413
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500414 can0_clk: can0_clk {
415 #clock-cells = <0>;
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
418 clk-gate = <0xa0 4>;
419 div-reg = <0xa4 6 3>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500420 };
421
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500422 can1_clk: can1_clk {
423 #clock-cells = <0>;
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&per_base_clk>;
426 clk-gate = <0xa0 5>;
427 div-reg = <0xa4 9 3>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500428 };
429
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500430 gpio_db_clk: gpio_db_clk {
431 #clock-cells = <0>;
432 compatible = "altr,socfpga-gate-clk";
433 clocks = <&per_base_clk>;
434 clk-gate = <0xa0 6>;
435 div-reg = <0xa8 0 24>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500436 };
437
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500438 h2f_user1_clk: h2f_user1_clk {
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500439 #clock-cells = <0>;
440 compatible = "altr,socfpga-gate-clk";
Steffen Trumtrar01ed80b2013-10-07 11:11:38 -0500441 clocks = <&h2f_usr1_clk>;
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500442 clk-gate = <0xa0 7>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500443 };
444
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500445 sdmmc_clk: sdmmc_clk {
446 #clock-cells = <0>;
447 compatible = "altr,socfpga-gate-clk";
448 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
449 clk-gate = <0xa0 8>;
Dinh Nguyen044abbd2014-01-06 12:17:24 -0600450 clk-phase = <0 135>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500451 };
452
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500453 nand_x_clk: nand_x_clk {
454 #clock-cells = <0>;
455 compatible = "altr,socfpga-gate-clk";
456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
457 clk-gate = <0xa0 9>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500458 };
459
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500460 nand_clk: nand_clk {
461 #clock-cells = <0>;
462 compatible = "altr,socfpga-gate-clk";
463 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
464 clk-gate = <0xa0 10>;
465 fixed-divider = <4>;
466 };
467
468 qspi_clk: qspi_clk {
469 #clock-cells = <0>;
470 compatible = "altr,socfpga-gate-clk";
471 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
472 clk-gate = <0xa0 11>;
Dinh Nguyena92b83a2013-06-05 10:02:54 -0500473 };
Dinh Nguyen042000b2013-04-11 10:55:25 -0500474 };
475 };
476
Dinh Nguyen3d954cf2013-06-05 10:02:53 -0500477 gmac0: ethernet@ff700000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600478 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
Dinh Nguyen2755e182014-03-26 22:45:11 -0500479 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600480 reg = <0xff700000 0x2000>;
481 interrupts = <0 115 4>;
482 interrupt-names = "macirq";
483 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
Dinh Nguyen3d954cf2013-06-05 10:02:53 -0500484 clocks = <&emac0_clk>;
485 clock-names = "stmmaceth";
486 status = "disabled";
487 };
488
489 gmac1: ethernet@ff702000 {
490 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
Dinh Nguyen2755e182014-03-26 22:45:11 -0500491 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
Dinh Nguyen3d954cf2013-06-05 10:02:53 -0500492 reg = <0xff702000 0x2000>;
493 interrupts = <0 120 4>;
494 interrupt-names = "macirq";
495 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
496 clocks = <&emac1_clk>;
497 clock-names = "stmmaceth";
498 status = "disabled";
Dinh Nguyen66314222012-07-18 16:07:18 -0600499 };
500
Steffen Trumtrarfdeda152014-04-02 11:05:31 -0500501 i2c0: i2c@ffc04000 {
502 #address-cells = <1>;
503 #size-cells = <0>;
504 compatible = "snps,designware-i2c";
505 reg = <0xffc04000 0x1000>;
506 clocks = <&l4_sp_clk>;
507 interrupts = <0 158 0x4>;
508 status = "disabled";
509 };
510
511 i2c1: i2c@ffc05000 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "snps,designware-i2c";
515 reg = <0xffc05000 0x1000>;
516 clocks = <&l4_sp_clk>;
517 interrupts = <0 159 0x4>;
518 status = "disabled";
519 };
520
521 i2c2: i2c@ffc06000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "snps,designware-i2c";
525 reg = <0xffc06000 0x1000>;
526 clocks = <&l4_sp_clk>;
527 interrupts = <0 160 0x4>;
528 status = "disabled";
529 };
530
531 i2c3: i2c@ffc07000 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "snps,designware-i2c";
535 reg = <0xffc07000 0x1000>;
536 clocks = <&l4_sp_clk>;
537 interrupts = <0 161 0x4>;
538 status = "disabled";
539 };
540
Dinh Nguyen66314222012-07-18 16:07:18 -0600541 L2: l2-cache@fffef000 {
542 compatible = "arm,pl310-cache";
543 reg = <0xfffef000 0x1000>;
544 interrupts = <0 38 0x04>;
545 cache-unified;
546 cache-level = <2>;
Dinh Nguyen9a21e552014-01-06 20:54:43 -0600547 arm,tag-latency = <1 1 1>;
548 arm,data-latency = <2 1 1>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600549 };
550
Dinh Nguyen9b931362014-02-17 20:31:02 -0600551 mmc: dwmmc0@ff704000 {
552 compatible = "altr,socfpga-dw-mshc";
553 reg = <0xff704000 0x1000>;
554 interrupts = <0 139 4>;
555 fifo-depth = <0x400>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
559 clock-names = "biu", "ciu";
560 };
561
Dinh Nguyen66314222012-07-18 16:07:18 -0600562 /* Local timer */
563 timer@fffec600 {
564 compatible = "arm,cortex-a9-twd-timer";
565 reg = <0xfffec600 0x100>;
566 interrupts = <1 13 0xf04>;
Dinh Nguyen159c7f82013-10-01 14:42:27 -0500567 clocks = <&mpu_periph_clk>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600568 };
569
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600570 timer0: timer0@ffc08000 {
Dinh Nguyen620f5e12013-08-21 15:28:49 -0500571 compatible = "snps,dw-apb-timer";
Dinh Nguyen66314222012-07-18 16:07:18 -0600572 interrupts = <0 167 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600573 reg = <0xffc08000 0x1000>;
574 };
575
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600576 timer1: timer1@ffc09000 {
Dinh Nguyen620f5e12013-08-21 15:28:49 -0500577 compatible = "snps,dw-apb-timer";
Dinh Nguyen66314222012-07-18 16:07:18 -0600578 interrupts = <0 168 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600579 reg = <0xffc09000 0x1000>;
580 };
581
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600582 timer2: timer2@ffd00000 {
Dinh Nguyen620f5e12013-08-21 15:28:49 -0500583 compatible = "snps,dw-apb-timer";
Dinh Nguyen66314222012-07-18 16:07:18 -0600584 interrupts = <0 169 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600585 reg = <0xffd00000 0x1000>;
586 };
587
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600588 timer3: timer3@ffd01000 {
Dinh Nguyen620f5e12013-08-21 15:28:49 -0500589 compatible = "snps,dw-apb-timer";
Dinh Nguyen66314222012-07-18 16:07:18 -0600590 interrupts = <0 170 4>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600591 reg = <0xffd01000 0x1000>;
592 };
593
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600594 uart0: serial0@ffc02000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600595 compatible = "snps,dw-apb-uart";
596 reg = <0xffc02000 0x1000>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600597 interrupts = <0 162 4>;
598 reg-shift = <2>;
599 reg-io-width = <4>;
600 };
601
Dinh Nguyenc2ad2842013-02-11 17:30:30 -0600602 uart1: serial1@ffc03000 {
Dinh Nguyen66314222012-07-18 16:07:18 -0600603 compatible = "snps,dw-apb-uart";
604 reg = <0xffc03000 0x1000>;
Dinh Nguyen66314222012-07-18 16:07:18 -0600605 interrupts = <0 163 4>;
606 reg-shift = <2>;
607 reg-io-width = <4>;
608 };
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600609
610 rstmgr@ffd05000 {
Steffen Trumtrar7857d562013-10-07 10:44:07 -0500611 compatible = "altr,rst-mgr";
612 reg = <0xffd05000 0x1000>;
613 };
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600614
Dinh Nguyena5d6ac22014-03-09 23:12:14 -0500615 sysmgr: sysmgr@ffd08000 {
Dinh Nguyen9b931362014-02-17 20:31:02 -0600616 compatible = "altr,sys-mgr", "syscon";
617 reg = <0xffd08000 0x4000>;
618 };
Dinh Nguyen66314222012-07-18 16:07:18 -0600619 };
620};