Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | /include/ "skeleton.dtsi" |
| 14 | |
| 15 | / { |
| 16 | aliases { |
Richard Zhao | 8f9ffec | 2011-12-14 09:26:45 +0800 | [diff] [blame] | 17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; |
| 19 | serial2 = &uart3; |
| 20 | serial3 = &uart4; |
| 21 | serial4 = &uart5; |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | tzic: tz-interrupt-controller@0fffc000 { |
| 32 | compatible = "fsl,imx53-tzic", "fsl,tzic"; |
| 33 | interrupt-controller; |
| 34 | #interrupt-cells = <1>; |
| 35 | reg = <0x0fffc000 0x4000>; |
| 36 | }; |
| 37 | |
| 38 | clocks { |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <0>; |
| 41 | |
| 42 | ckil { |
| 43 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 44 | clock-frequency = <32768>; |
| 45 | }; |
| 46 | |
| 47 | ckih1 { |
| 48 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 49 | clock-frequency = <22579200>; |
| 50 | }; |
| 51 | |
| 52 | ckih2 { |
| 53 | compatible = "fsl,imx-ckih2", "fixed-clock"; |
| 54 | clock-frequency = <0>; |
| 55 | }; |
| 56 | |
| 57 | osc { |
| 58 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 59 | clock-frequency = <24000000>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc { |
| 64 | #address-cells = <1>; |
| 65 | #size-cells = <1>; |
| 66 | compatible = "simple-bus"; |
| 67 | interrupt-parent = <&tzic>; |
| 68 | ranges; |
| 69 | |
| 70 | aips@50000000 { /* AIPS1 */ |
| 71 | compatible = "fsl,aips-bus", "simple-bus"; |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <1>; |
| 74 | reg = <0x50000000 0x10000000>; |
| 75 | ranges; |
| 76 | |
| 77 | spba@50000000 { |
| 78 | compatible = "fsl,spba-bus", "simple-bus"; |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | reg = <0x50000000 0x40000>; |
| 82 | ranges; |
| 83 | |
| 84 | esdhc@50004000 { /* ESDHC1 */ |
| 85 | compatible = "fsl,imx53-esdhc"; |
| 86 | reg = <0x50004000 0x4000>; |
| 87 | interrupts = <1>; |
| 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | esdhc@50008000 { /* ESDHC2 */ |
| 92 | compatible = "fsl,imx53-esdhc"; |
| 93 | reg = <0x50008000 0x4000>; |
| 94 | interrupts = <2>; |
| 95 | status = "disabled"; |
| 96 | }; |
| 97 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 98 | uart3: serial@5000c000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 99 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 100 | reg = <0x5000c000 0x4000>; |
| 101 | interrupts = <33>; |
| 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | ecspi@50010000 { /* ECSPI1 */ |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 109 | reg = <0x50010000 0x4000>; |
| 110 | interrupts = <36>; |
| 111 | status = "disabled"; |
| 112 | }; |
| 113 | |
Shawn Guo | ffc505c | 2012-05-11 13:12:01 +0800 | [diff] [blame] | 114 | ssi2: ssi@50014000 { |
| 115 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 116 | reg = <0x50014000 0x4000>; |
| 117 | interrupts = <30>; |
| 118 | fsl,fifo-depth = <15>; |
| 119 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ |
| 120 | status = "disabled"; |
| 121 | }; |
| 122 | |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 123 | esdhc@50020000 { /* ESDHC3 */ |
| 124 | compatible = "fsl,imx53-esdhc"; |
| 125 | reg = <0x50020000 0x4000>; |
| 126 | interrupts = <3>; |
| 127 | status = "disabled"; |
| 128 | }; |
| 129 | |
| 130 | esdhc@50024000 { /* ESDHC4 */ |
| 131 | compatible = "fsl,imx53-esdhc"; |
| 132 | reg = <0x50024000 0x4000>; |
| 133 | interrupts = <4>; |
| 134 | status = "disabled"; |
| 135 | }; |
| 136 | }; |
| 137 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 138 | gpio1: gpio@53f84000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 139 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 140 | reg = <0x53f84000 0x4000>; |
| 141 | interrupts = <50 51>; |
| 142 | gpio-controller; |
| 143 | #gpio-cells = <2>; |
| 144 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 145 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 146 | }; |
| 147 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 148 | gpio2: gpio@53f88000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 149 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 150 | reg = <0x53f88000 0x4000>; |
| 151 | interrupts = <52 53>; |
| 152 | gpio-controller; |
| 153 | #gpio-cells = <2>; |
| 154 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 155 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 156 | }; |
| 157 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 158 | gpio3: gpio@53f8c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 159 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 160 | reg = <0x53f8c000 0x4000>; |
| 161 | interrupts = <54 55>; |
| 162 | gpio-controller; |
| 163 | #gpio-cells = <2>; |
| 164 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 165 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 166 | }; |
| 167 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 168 | gpio4: gpio@53f90000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 169 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 170 | reg = <0x53f90000 0x4000>; |
| 171 | interrupts = <56 57>; |
| 172 | gpio-controller; |
| 173 | #gpio-cells = <2>; |
| 174 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 175 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | wdog@53f98000 { /* WDOG1 */ |
| 179 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 180 | reg = <0x53f98000 0x4000>; |
| 181 | interrupts = <58>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | wdog@53f9c000 { /* WDOG2 */ |
| 185 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 186 | reg = <0x53f9c000 0x4000>; |
| 187 | interrupts = <59>; |
| 188 | status = "disabled"; |
| 189 | }; |
| 190 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 191 | uart1: serial@53fbc000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 192 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 193 | reg = <0x53fbc000 0x4000>; |
| 194 | interrupts = <31>; |
| 195 | status = "disabled"; |
| 196 | }; |
| 197 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 198 | uart2: serial@53fc0000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 199 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 200 | reg = <0x53fc0000 0x4000>; |
| 201 | interrupts = <32>; |
| 202 | status = "disabled"; |
| 203 | }; |
| 204 | |
Steffen Trumtrar | a9d1f92 | 2012-07-18 11:42:43 +0200 | [diff] [blame] | 205 | can1: can@53fc8000 { |
| 206 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 207 | reg = <0x53fc8000 0x4000>; |
| 208 | interrupts = <82>; |
| 209 | status = "disabled"; |
| 210 | }; |
| 211 | |
| 212 | can2: can@53fcc000 { |
| 213 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
| 214 | reg = <0x53fcc000 0x4000>; |
| 215 | interrupts = <83>; |
| 216 | status = "disabled"; |
| 217 | }; |
| 218 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 219 | gpio5: gpio@53fdc000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 220 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 221 | reg = <0x53fdc000 0x4000>; |
| 222 | interrupts = <103 104>; |
| 223 | gpio-controller; |
| 224 | #gpio-cells = <2>; |
| 225 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 226 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 227 | }; |
| 228 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 229 | gpio6: gpio@53fe0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 230 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 231 | reg = <0x53fe0000 0x4000>; |
| 232 | interrupts = <105 106>; |
| 233 | gpio-controller; |
| 234 | #gpio-cells = <2>; |
| 235 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 236 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 237 | }; |
| 238 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 239 | gpio7: gpio@53fe4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 240 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 241 | reg = <0x53fe4000 0x4000>; |
| 242 | interrupts = <107 108>; |
| 243 | gpio-controller; |
| 244 | #gpio-cells = <2>; |
| 245 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 246 | #interrupt-cells = <2>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | i2c@53fec000 { /* I2C3 */ |
| 250 | #address-cells = <1>; |
| 251 | #size-cells = <0>; |
| 252 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 253 | reg = <0x53fec000 0x4000>; |
| 254 | interrupts = <64>; |
| 255 | status = "disabled"; |
| 256 | }; |
| 257 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 258 | uart4: serial@53ff0000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 259 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 260 | reg = <0x53ff0000 0x4000>; |
| 261 | interrupts = <13>; |
| 262 | status = "disabled"; |
| 263 | }; |
| 264 | }; |
| 265 | |
| 266 | aips@60000000 { /* AIPS2 */ |
| 267 | compatible = "fsl,aips-bus", "simple-bus"; |
| 268 | #address-cells = <1>; |
| 269 | #size-cells = <1>; |
| 270 | reg = <0x60000000 0x10000000>; |
| 271 | ranges; |
| 272 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 273 | uart5: serial@63f90000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 274 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 275 | reg = <0x63f90000 0x4000>; |
| 276 | interrupts = <86>; |
| 277 | status = "disabled"; |
| 278 | }; |
| 279 | |
| 280 | ecspi@63fac000 { /* ECSPI2 */ |
| 281 | #address-cells = <1>; |
| 282 | #size-cells = <0>; |
| 283 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
| 284 | reg = <0x63fac000 0x4000>; |
| 285 | interrupts = <37>; |
| 286 | status = "disabled"; |
| 287 | }; |
| 288 | |
| 289 | sdma@63fb0000 { |
| 290 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 291 | reg = <0x63fb0000 0x4000>; |
| 292 | interrupts = <6>; |
Fabio Estevam | 7e4f036 | 2012-08-08 11:28:07 -0300 | [diff] [blame^] | 293 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | cspi@63fc0000 { |
| 297 | #address-cells = <1>; |
| 298 | #size-cells = <0>; |
| 299 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; |
| 300 | reg = <0x63fc0000 0x4000>; |
| 301 | interrupts = <38>; |
| 302 | status = "disabled"; |
| 303 | }; |
| 304 | |
| 305 | i2c@63fc4000 { /* I2C2 */ |
| 306 | #address-cells = <1>; |
| 307 | #size-cells = <0>; |
| 308 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 309 | reg = <0x63fc4000 0x4000>; |
| 310 | interrupts = <63>; |
| 311 | status = "disabled"; |
| 312 | }; |
| 313 | |
| 314 | i2c@63fc8000 { /* I2C1 */ |
| 315 | #address-cells = <1>; |
| 316 | #size-cells = <0>; |
| 317 | compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; |
| 318 | reg = <0x63fc8000 0x4000>; |
| 319 | interrupts = <62>; |
| 320 | status = "disabled"; |
| 321 | }; |
| 322 | |
Shawn Guo | ffc505c | 2012-05-11 13:12:01 +0800 | [diff] [blame] | 323 | ssi1: ssi@63fcc000 { |
| 324 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 325 | reg = <0x63fcc000 0x4000>; |
| 326 | interrupts = <29>; |
| 327 | fsl,fifo-depth = <15>; |
| 328 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ |
| 329 | status = "disabled"; |
| 330 | }; |
| 331 | |
| 332 | audmux@63fd0000 { |
| 333 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 334 | reg = <0x63fd0000 0x4000>; |
| 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
| 338 | ssi3: ssi@63fe8000 { |
| 339 | compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; |
| 340 | reg = <0x63fe8000 0x4000>; |
| 341 | interrupts = <96>; |
| 342 | fsl,fifo-depth = <15>; |
| 343 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ |
| 344 | status = "disabled"; |
| 345 | }; |
| 346 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 347 | ethernet@63fec000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 348 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 349 | reg = <0x63fec000 0x4000>; |
| 350 | interrupts = <87>; |
| 351 | status = "disabled"; |
| 352 | }; |
| 353 | }; |
| 354 | }; |
| 355 | }; |