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gerrit-public.fairphone.software / kernel / msm-4.19 / f722406faae2d073cc1d01063d1123c35425939e / . / arch / arm / boot / dts / wm8850.dtsi
blob: fc790d0aee66e6399865802adc49bfe58fd9af71 [file] [log] [blame]
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]1/*
2 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8850";
13
14 aliases {
15 serial0 = &uart0;
16 serial1 = &uart1;
17 serial2 = &uart2;
18 serial3 = &uart3;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 ranges;
26 interrupt-parent = <&intc0>;
27
28 intc0: interrupt-controller@d8140000 {
29 compatible = "via,vt8500-intc";
30 interrupt-controller;
31 reg = <0xd8140000 0x10000>;
32 #interrupt-cells = <1>;
33 };
34
35 /* Secondary IC cascaded to intc0 */
36 intc1: interrupt-controller@d8150000 {
37 compatible = "via,vt8500-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0xD8150000 0x10000>;
41 interrupts = <56 57 58 59 60 61 62 63>;
42 };
43
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]44 pinctrl: pinctrl@d8110000 {
45 compatible = "wm,wm8850-pinctrl";
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]46 reg = <0xd8110000 0x10000>;
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]47 interrupt-controller;
48 #interrupt-cells = <2>;
49 gpio-controller;
50 #gpio-cells = <2>;
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]51 };
52
53 pmc@d8130000 {
54 compatible = "via,vt8500-pmc";
55 reg = <0xd8130000 0x1000>;
56
57 clocks {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 ref25: ref25M {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <25000000>;
65 };
66
67 ref24: ref24M {
68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <24000000>;
71 };
72
73 plla: plla {
74 #clock-cells = <0>;
75 compatible = "wm,wm8750-pll-clock";
76 clocks = <&ref25>;
77 reg = <0x200>;
78 };
79
80 pllb: pllb {
81 #clock-cells = <0>;
82 compatible = "wm,wm8750-pll-clock";
83 clocks = <&ref25>;
84 reg = <0x204>;
85 };
86
87 clkuart0: uart0 {
88 #clock-cells = <0>;
89 compatible = "via,vt8500-device-clock";
90 clocks = <&ref24>;
91 enable-reg = <0x254>;
92 enable-bit = <24>;
93 };
94
95 clkuart1: uart1 {
96 #clock-cells = <0>;
97 compatible = "via,vt8500-device-clock";
98 clocks = <&ref24>;
99 enable-reg = <0x254>;
100 enable-bit = <25>;
101 };
102
103 clkuart2: uart2 {
104 #clock-cells = <0>;
105 compatible = "via,vt8500-device-clock";
106 clocks = <&ref24>;
107 enable-reg = <0x254>;
108 enable-bit = <26>;
109 };
110
111 clkuart3: uart3 {
112 #clock-cells = <0>;
113 compatible = "via,vt8500-device-clock";
114 clocks = <&ref24>;
115 enable-reg = <0x254>;
116 enable-bit = <27>;
117 };
118
119 clkpwm: pwm {
120 #clock-cells = <0>;
121 compatible = "via,vt8500-device-clock";
122 clocks = <&pllb>;
123 divisor-reg = <0x350>;
124 enable-reg = <0x250>;
125 enable-bit = <17>;
126 };
127
128 clksdhc: sdhc {
129 #clock-cells = <0>;
130 compatible = "via,vt8500-device-clock";
131 clocks = <&pllb>;
132 divisor-reg = <0x330>;
133 divisor-mask = <0x3f>;
134 enable-reg = <0x250>;
135 enable-bit = <0>;
136 };
137 };
138 };
139
Tony Prisk7ab0a482013-04-03 07:20:38 +1300[diff] [blame]140 fb: fb@d8051700 {
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]141 compatible = "wm,wm8505-fb";
142 reg = <0xd8051700 0x200>;
Tony Priskdef4d6c2013-01-19 19:44:28 +1300[diff] [blame]143 };
144
145 ge_rops@d8050400 {
146 compatible = "wm,prizm-ge-rops";
147 reg = <0xd8050400 0x100>;
148 };
149
150 pwm: pwm@d8220000 {
151 #pwm-cells = <3>;
152 compatible = "via,vt8500-pwm";
153 reg = <0xd8220000 0x100>;
154 clocks = <&clkpwm>;
155 };
156
157 timer@d8130100 {
158 compatible = "via,vt8500-timer";
159 reg = <0xd8130100 0x28>;
160 interrupts = <36>;
161 };
162
163 ehci@d8007900 {
164 compatible = "via,vt8500-ehci";
165 reg = <0xd8007900 0x200>;
166 interrupts = <26>;
167 };
168
169 uhci@d8007b00 {
170 compatible = "platform-uhci";
171 reg = <0xd8007b00 0x200>;
172 interrupts = <26>;
173 };
174
175 uhci@d8008d00 {
176 compatible = "platform-uhci";
177 reg = <0xd8008d00 0x200>;
178 interrupts = <26>;
179 };
180
181 uart0: uart@d8200000 {
182 compatible = "via,vt8500-uart";
183 reg = <0xd8200000 0x1040>;
184 interrupts = <32>;
185 clocks = <&clkuart0>;
186 };
187
188 uart1: uart@d82b0000 {
189 compatible = "via,vt8500-uart";
190 reg = <0xd82b0000 0x1040>;
191 interrupts = <33>;
192 clocks = <&clkuart1>;
193 };
194
195 uart2: uart@d8210000 {
196 compatible = "via,vt8500-uart";
197 reg = <0xd8210000 0x1040>;
198 interrupts = <47>;
199 clocks = <&clkuart2>;
200 };
201
202 uart3: uart@d82c0000 {
203 compatible = "via,vt8500-uart";
204 reg = <0xd82c0000 0x1040>;
205 interrupts = <50>;
206 clocks = <&clkuart3>;
207 };
208
209 rtc@d8100000 {
210 compatible = "via,vt8500-rtc";
211 reg = <0xd8100000 0x10000>;
212 interrupts = <48>;
213 };
214
215 sdhc@d800a000 {
216 compatible = "wm,wm8505-sdhc";
217 reg = <0xd800a000 0x1000>;
218 interrupts = <20 21>;
219 clocks = <&clksdhc>;
220 bus-width = <4>;
221 sdon-inverted;
222 };
223 };
224};