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gerrit-public.fairphone.software / kernel / msm-4.19 / 7f107887d1995c819389f292828097cac4ec4396 / . / arch / arm / boot / dts / imx28.dtsi
blob: 3aabf65a6a5224f5681d6ba189087a550824e964 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame^]16 #address-cells = <1>;
17 #size-cells = <1>;
18
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]19 interrupt-parent = <&icoll>;
20
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]21 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]22 ethernet0 = &mac0;
23 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]24 gpio0 = &gpio0;
25 gpio1 = &gpio1;
26 gpio2 = &gpio2;
27 gpio3 = &gpio3;
28 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]29 saif0 = &saif0;
30 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]31 serial0 = &auart0;
32 serial1 = &auart1;
33 serial2 = &auart2;
34 serial3 = &auart3;
35 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]36 spi0 = &ssp1;
37 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]38 usbphy0 = &usbphy0;
39 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]40 };
41
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]42 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]43 #address-cells = <0>;
44 #size-cells = <0>;
45
46 cpu {
47 compatible = "arm,arm926ej-s";
48 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]49 };
50 };
51
52 apb@80000000 {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0x80000000 0x80000>;
57 ranges;
58
59 apbh@80000000 {
60 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0x80000000 0x3c900>;
64 ranges;
65
66 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]67 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]68 interrupt-controller;
69 #interrupt-cells = <1>;
70 reg = <0x80000000 0x2000>;
71 };
72
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]73 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]74 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]75 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]76 dmas = <&dma_apbh 12>;
77 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]78 status = "disabled";
79 };
80
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]81 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]82 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]83 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]84 interrupts = <82 83 84 85
85 88 88 88 88
86 88 88 88 88
87 87 86 0 0>;
88 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
89 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
90 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
91 "hsadc", "lcdif", "empty", "empty";
92 #dma-cells = <1>;
93 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]94 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]95 };
96
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]97 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]98 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]99 interrupts = <27>;
100 status = "disabled";
101 };
102
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]103 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]104 compatible = "fsl,imx28-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]107 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]108 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]109 interrupts = <41>;
110 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]111 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]112 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]113 dmas = <&dma_apbh 4>;
114 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]115 status = "disabled";
116 };
117
118 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]119 #address-cells = <1>;
120 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]121 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]122 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]123 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]124 dmas = <&dma_apbh 0>;
125 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]126 status = "disabled";
127 };
128
129 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]130 #address-cells = <1>;
131 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]132 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]133 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]134 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]135 dmas = <&dma_apbh 1>;
136 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]137 status = "disabled";
138 };
139
140 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]141 #address-cells = <1>;
142 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]143 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]144 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]145 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]146 dmas = <&dma_apbh 2>;
147 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]148 status = "disabled";
149 };
150
151 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]152 #address-cells = <1>;
153 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]154 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]155 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]156 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]157 dmas = <&dma_apbh 3>;
158 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]159 status = "disabled";
160 };
161
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]162 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]163 #address-cells = <1>;
164 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]165 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]166 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]167
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]168 gpio0: gpio@0 {
169 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]170 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]171 interrupts = <127>;
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 };
177
178 gpio1: gpio@1 {
179 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]180 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]181 interrupts = <126>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
187
188 gpio2: gpio@2 {
189 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]190 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]191 interrupts = <125>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 };
197
198 gpio3: gpio@3 {
199 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]200 reg = <3>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]201 interrupts = <124>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
208 gpio4: gpio@4 {
209 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]210 reg = <4>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]211 interrupts = <123>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 };
217
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]218 duart_pins_a: duart@0 {
219 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]220 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]221 MX28_PAD_PWM0__DUART_RX
222 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]223 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]224 fsl,drive-strength = <MXS_DRIVE_4mA>;
225 fsl,voltage = <MXS_VOLTAGE_HIGH>;
226 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]227 };
228
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]229 duart_pins_b: duart@1 {
230 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]231 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]232 MX28_PAD_AUART0_CTS__DUART_RX
233 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]234 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]235 fsl,drive-strength = <MXS_DRIVE_4mA>;
236 fsl,voltage = <MXS_VOLTAGE_HIGH>;
237 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]238 };
239
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]240 duart_4pins_a: duart-4pins@0 {
241 reg = <0>;
242 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]243 MX28_PAD_AUART0_CTS__DUART_RX
244 MX28_PAD_AUART0_RTS__DUART_TX
245 MX28_PAD_AUART0_RX__DUART_CTS
246 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]247 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]248 fsl,drive-strength = <MXS_DRIVE_4mA>;
249 fsl,voltage = <MXS_VOLTAGE_HIGH>;
250 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]251 };
252
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]253 gpmi_pins_a: gpmi-nand@0 {
254 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]255 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]256 MX28_PAD_GPMI_D00__GPMI_D0
257 MX28_PAD_GPMI_D01__GPMI_D1
258 MX28_PAD_GPMI_D02__GPMI_D2
259 MX28_PAD_GPMI_D03__GPMI_D3
260 MX28_PAD_GPMI_D04__GPMI_D4
261 MX28_PAD_GPMI_D05__GPMI_D5
262 MX28_PAD_GPMI_D06__GPMI_D6
263 MX28_PAD_GPMI_D07__GPMI_D7
264 MX28_PAD_GPMI_CE0N__GPMI_CE0N
265 MX28_PAD_GPMI_RDY0__GPMI_READY0
266 MX28_PAD_GPMI_RDN__GPMI_RDN
267 MX28_PAD_GPMI_WRN__GPMI_WRN
268 MX28_PAD_GPMI_ALE__GPMI_ALE
269 MX28_PAD_GPMI_CLE__GPMI_CLE
270 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]271 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]272 fsl,drive-strength = <MXS_DRIVE_4mA>;
273 fsl,voltage = <MXS_VOLTAGE_HIGH>;
274 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]275 };
276
277 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]278 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]279 MX28_PAD_GPMI_RDN__GPMI_RDN
280 MX28_PAD_GPMI_WRN__GPMI_WRN
281 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]282 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]283 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]284 };
285
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]286 auart0_pins_a: auart0@0 {
287 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]288 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]289 MX28_PAD_AUART0_RX__AUART0_RX
290 MX28_PAD_AUART0_TX__AUART0_TX
291 MX28_PAD_AUART0_CTS__AUART0_CTS
292 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]293 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]294 fsl,drive-strength = <MXS_DRIVE_4mA>;
295 fsl,voltage = <MXS_VOLTAGE_HIGH>;
296 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]297 };
298
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]299 auart0_2pins_a: auart0-2pins@0 {
300 reg = <0>;
301 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]302 MX28_PAD_AUART0_RX__AUART0_RX
303 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]304 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]305 fsl,drive-strength = <MXS_DRIVE_4mA>;
306 fsl,voltage = <MXS_VOLTAGE_HIGH>;
307 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]308 };
309
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]310 auart1_pins_a: auart1@0 {
311 reg = <0>;
312 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]313 MX28_PAD_AUART1_RX__AUART1_RX
314 MX28_PAD_AUART1_TX__AUART1_TX
315 MX28_PAD_AUART1_CTS__AUART1_CTS
316 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]317 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]318 fsl,drive-strength = <MXS_DRIVE_4mA>;
319 fsl,voltage = <MXS_VOLTAGE_HIGH>;
320 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]321 };
322
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]323 auart1_2pins_a: auart1-2pins@0 {
324 reg = <0>;
325 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]326 MX28_PAD_AUART1_RX__AUART1_RX
327 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]328 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]329 fsl,drive-strength = <MXS_DRIVE_4mA>;
330 fsl,voltage = <MXS_VOLTAGE_HIGH>;
331 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]332 };
333
334 auart2_2pins_a: auart2-2pins@0 {
335 reg = <0>;
336 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]337 MX28_PAD_SSP2_SCK__AUART2_RX
338 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]339 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]340 fsl,drive-strength = <MXS_DRIVE_4mA>;
341 fsl,voltage = <MXS_VOLTAGE_HIGH>;
342 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]343 };
344
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]345 auart2_2pins_b: auart2-2pins@1 {
346 reg = <1>;
347 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]348 MX28_PAD_AUART2_RX__AUART2_RX
349 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]350 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]351 fsl,drive-strength = <MXS_DRIVE_4mA>;
352 fsl,voltage = <MXS_VOLTAGE_HIGH>;
353 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]354 };
355
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]356 auart2_pins_a: auart2-pins@0 {
357 reg = <0>;
358 fsl,pinmux-ids = <
359 MX28_PAD_AUART2_RX__AUART2_RX
360 MX28_PAD_AUART2_TX__AUART2_TX
361 MX28_PAD_AUART2_CTS__AUART2_CTS
362 MX28_PAD_AUART2_RTS__AUART2_RTS
363 >;
364 fsl,drive-strength = <MXS_DRIVE_4mA>;
365 fsl,voltage = <MXS_VOLTAGE_HIGH>;
366 fsl,pull-up = <MXS_PULL_DISABLE>;
367 };
368
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]369 auart3_pins_a: auart3@0 {
370 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]371 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]372 MX28_PAD_AUART3_RX__AUART3_RX
373 MX28_PAD_AUART3_TX__AUART3_TX
374 MX28_PAD_AUART3_CTS__AUART3_CTS
375 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]376 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]377 fsl,drive-strength = <MXS_DRIVE_4mA>;
378 fsl,voltage = <MXS_VOLTAGE_HIGH>;
379 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]380 };
381
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]382 auart3_2pins_a: auart3-2pins@0 {
383 reg = <0>;
384 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]385 MX28_PAD_SSP2_MISO__AUART3_RX
386 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]387 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]388 fsl,drive-strength = <MXS_DRIVE_4mA>;
389 fsl,voltage = <MXS_VOLTAGE_HIGH>;
390 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]391 };
392
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]393 auart3_2pins_b: auart3-2pins@1 {
394 reg = <1>;
395 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]396 MX28_PAD_AUART3_RX__AUART3_RX
397 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]398 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]399 fsl,drive-strength = <MXS_DRIVE_4mA>;
400 fsl,voltage = <MXS_VOLTAGE_HIGH>;
401 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]402 };
403
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]404 auart4_2pins_a: auart4@0 {
405 reg = <0>;
406 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]407 MX28_PAD_SSP3_SCK__AUART4_TX
408 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]409 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]410 fsl,drive-strength = <MXS_DRIVE_4mA>;
411 fsl,voltage = <MXS_VOLTAGE_HIGH>;
412 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]413 };
414
Mans Rullgardcfa1dd92015-12-11 13:36:26 +0000[diff] [blame]415 auart4_2pins_b: auart4@1 {
416 reg = <1>;
417 fsl,pinmux-ids = <
418 MX28_PAD_AUART0_CTS__AUART4_RX
419 MX28_PAD_AUART0_RTS__AUART4_TX
420 >;
421 fsl,drive-strength = <MXS_DRIVE_4mA>;
422 fsl,voltage = <MXS_VOLTAGE_HIGH>;
423 fsl,pull-up = <MXS_PULL_DISABLE>;
424 };
425
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]426 mac0_pins_a: mac0@0 {
427 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]428 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]429 MX28_PAD_ENET0_MDC__ENET0_MDC
430 MX28_PAD_ENET0_MDIO__ENET0_MDIO
431 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
432 MX28_PAD_ENET0_RXD0__ENET0_RXD0
433 MX28_PAD_ENET0_RXD1__ENET0_RXD1
434 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
435 MX28_PAD_ENET0_TXD0__ENET0_TXD0
436 MX28_PAD_ENET0_TXD1__ENET0_TXD1
437 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]438 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]439 fsl,drive-strength = <MXS_DRIVE_8mA>;
440 fsl,voltage = <MXS_VOLTAGE_HIGH>;
441 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]442 };
443
Uwe Kleine-König9eb7db12016-04-06 09:32:59 +0200[diff] [blame]444 mac0_pins_b: mac0@1 {
445 reg = <1>;
446 fsl,pinmux-ids = <
447 MX28_PAD_ENET0_MDC__ENET0_MDC
448 MX28_PAD_ENET0_MDIO__ENET0_MDIO
449 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
450 MX28_PAD_ENET0_RXD0__ENET0_RXD0
451 MX28_PAD_ENET0_RXD1__ENET0_RXD1
452 MX28_PAD_ENET0_RXD2__ENET0_RXD2
453 MX28_PAD_ENET0_RXD3__ENET0_RXD3
454 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
455 MX28_PAD_ENET0_TXD0__ENET0_TXD0
456 MX28_PAD_ENET0_TXD1__ENET0_TXD1
457 MX28_PAD_ENET0_TXD2__ENET0_TXD2
458 MX28_PAD_ENET0_TXD3__ENET0_TXD3
459 MX28_PAD_ENET_CLK__CLKCTRL_ENET
460 MX28_PAD_ENET0_COL__ENET0_COL
461 MX28_PAD_ENET0_CRS__ENET0_CRS
462 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
463 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
464 >;
465 fsl,drive-strength = <MXS_DRIVE_8mA>;
466 fsl,voltage = <MXS_VOLTAGE_HIGH>;
467 fsl,pull-up = <MXS_PULL_ENABLE>;
468 };
469
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]470 mac1_pins_a: mac1@0 {
471 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]472 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]473 MX28_PAD_ENET0_CRS__ENET1_RX_EN
474 MX28_PAD_ENET0_RXD2__ENET1_RXD0
475 MX28_PAD_ENET0_RXD3__ENET1_RXD1
476 MX28_PAD_ENET0_COL__ENET1_TX_EN
477 MX28_PAD_ENET0_TXD2__ENET1_TXD0
478 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]479 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]480 fsl,drive-strength = <MXS_DRIVE_8mA>;
481 fsl,voltage = <MXS_VOLTAGE_HIGH>;
482 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]483 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]484
485 mmc0_8bit_pins_a: mmc0-8bit@0 {
486 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]487 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]488 MX28_PAD_SSP0_DATA0__SSP0_D0
489 MX28_PAD_SSP0_DATA1__SSP0_D1
490 MX28_PAD_SSP0_DATA2__SSP0_D2
491 MX28_PAD_SSP0_DATA3__SSP0_D3
492 MX28_PAD_SSP0_DATA4__SSP0_D4
493 MX28_PAD_SSP0_DATA5__SSP0_D5
494 MX28_PAD_SSP0_DATA6__SSP0_D6
495 MX28_PAD_SSP0_DATA7__SSP0_D7
496 MX28_PAD_SSP0_CMD__SSP0_CMD
497 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
498 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]499 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]500 fsl,drive-strength = <MXS_DRIVE_8mA>;
501 fsl,voltage = <MXS_VOLTAGE_HIGH>;
502 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]503 };
504
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]505 mmc0_4bit_pins_a: mmc0-4bit@0 {
506 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]507 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]508 MX28_PAD_SSP0_DATA0__SSP0_D0
509 MX28_PAD_SSP0_DATA1__SSP0_D1
510 MX28_PAD_SSP0_DATA2__SSP0_D2
511 MX28_PAD_SSP0_DATA3__SSP0_D3
512 MX28_PAD_SSP0_CMD__SSP0_CMD
513 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
514 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]515 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]516 fsl,drive-strength = <MXS_DRIVE_8mA>;
517 fsl,voltage = <MXS_VOLTAGE_HIGH>;
518 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]519 };
520
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]521 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]522 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]523 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]524 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]525 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]526 };
527
528 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]529 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]530 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]531 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]532 fsl,drive-strength = <MXS_DRIVE_12mA>;
533 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]534 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]535
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]536 mmc1_4bit_pins_a: mmc1-4bit@0 {
537 reg = <0>;
538 fsl,pinmux-ids = <
539 MX28_PAD_GPMI_D00__SSP1_D0
540 MX28_PAD_GPMI_D01__SSP1_D1
541 MX28_PAD_GPMI_D02__SSP1_D2
542 MX28_PAD_GPMI_D03__SSP1_D3
543 MX28_PAD_GPMI_RDY1__SSP1_CMD
544 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
545 MX28_PAD_GPMI_WRN__SSP1_SCK
546 >;
547 fsl,drive-strength = <MXS_DRIVE_8mA>;
548 fsl,voltage = <MXS_VOLTAGE_HIGH>;
549 fsl,pull-up = <MXS_PULL_ENABLE>;
550 };
551
552 mmc1_cd_cfg: mmc1-cd-cfg {
553 fsl,pinmux-ids = <
554 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
555 >;
556 fsl,pull-up = <MXS_PULL_DISABLE>;
557 };
558
559 mmc1_sck_cfg: mmc1-sck-cfg {
560 fsl,pinmux-ids = <
561 MX28_PAD_GPMI_WRN__SSP1_SCK
562 >;
563 fsl,drive-strength = <MXS_DRIVE_12mA>;
564 fsl,pull-up = <MXS_PULL_DISABLE>;
565 };
566
567
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]568 mmc2_4bit_pins_a: mmc2-4bit@0 {
569 reg = <0>;
570 fsl,pinmux-ids = <
571 MX28_PAD_SSP0_DATA4__SSP2_D0
572 MX28_PAD_SSP1_SCK__SSP2_D1
573 MX28_PAD_SSP1_CMD__SSP2_D2
574 MX28_PAD_SSP0_DATA5__SSP2_D3
575 MX28_PAD_SSP0_DATA6__SSP2_CMD
576 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
577 MX28_PAD_SSP0_DATA7__SSP2_SCK
578 >;
579 fsl,drive-strength = <MXS_DRIVE_8mA>;
580 fsl,voltage = <MXS_VOLTAGE_HIGH>;
581 fsl,pull-up = <MXS_PULL_ENABLE>;
582 };
583
584 mmc2_cd_cfg: mmc2-cd-cfg {
585 fsl,pinmux-ids = <
586 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
587 >;
588 fsl,pull-up = <MXS_PULL_DISABLE>;
589 };
590
591 mmc2_sck_cfg: mmc2-sck-cfg {
592 fsl,pinmux-ids = <
593 MX28_PAD_SSP0_DATA7__SSP2_SCK
594 >;
595 fsl,drive-strength = <MXS_DRIVE_12mA>;
596 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]597 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]598
599 i2c0_pins_a: i2c0@0 {
600 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]601 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]602 MX28_PAD_I2C0_SCL__I2C0_SCL
603 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]604 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]605 fsl,drive-strength = <MXS_DRIVE_8mA>;
606 fsl,voltage = <MXS_VOLTAGE_HIGH>;
607 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]608 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]609
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]610 i2c0_pins_b: i2c0@1 {
611 reg = <1>;
612 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]613 MX28_PAD_AUART0_RX__I2C0_SCL
614 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]615 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]616 fsl,drive-strength = <MXS_DRIVE_8mA>;
617 fsl,voltage = <MXS_VOLTAGE_HIGH>;
618 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]619 };
620
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]621 i2c1_pins_a: i2c1@0 {
622 reg = <0>;
623 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]624 MX28_PAD_PWM0__I2C1_SCL
625 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]626 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]627 fsl,drive-strength = <MXS_DRIVE_8mA>;
628 fsl,voltage = <MXS_VOLTAGE_HIGH>;
629 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]630 };
631
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]632 i2c1_pins_b: i2c1@1 {
633 reg = <1>;
634 fsl,pinmux-ids = <
635 MX28_PAD_AUART2_CTS__I2C1_SCL
636 MX28_PAD_AUART2_RTS__I2C1_SDA
637 >;
638 fsl,drive-strength = <MXS_DRIVE_8mA>;
639 fsl,voltage = <MXS_VOLTAGE_HIGH>;
640 fsl,pull-up = <MXS_PULL_ENABLE>;
641 };
642
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]643 saif0_pins_a: saif0@0 {
644 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]645 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]646 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
647 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
648 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
649 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]650 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]651 fsl,drive-strength = <MXS_DRIVE_12mA>;
652 fsl,voltage = <MXS_VOLTAGE_HIGH>;
653 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]654 };
655
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]656 saif0_pins_b: saif0@1 {
657 reg = <1>;
658 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]659 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
660 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
661 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]662 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]663 fsl,drive-strength = <MXS_DRIVE_12mA>;
664 fsl,voltage = <MXS_VOLTAGE_HIGH>;
665 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]666 };
667
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]668 saif1_pins_a: saif1@0 {
669 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]670 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]671 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]672 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]673 fsl,drive-strength = <MXS_DRIVE_12mA>;
674 fsl,voltage = <MXS_VOLTAGE_HIGH>;
675 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]676 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]677
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]678 pwm0_pins_a: pwm0@0 {
679 reg = <0>;
680 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]681 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]682 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]683 fsl,drive-strength = <MXS_DRIVE_4mA>;
684 fsl,voltage = <MXS_VOLTAGE_HIGH>;
685 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]686 };
687
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]688 pwm2_pins_a: pwm2@0 {
689 reg = <0>;
690 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]691 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]692 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]693 fsl,drive-strength = <MXS_DRIVE_4mA>;
694 fsl,voltage = <MXS_VOLTAGE_HIGH>;
695 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]696 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]697
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]698 pwm3_pins_a: pwm3@0 {
699 reg = <0>;
700 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]701 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]702 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]703 fsl,drive-strength = <MXS_DRIVE_4mA>;
704 fsl,voltage = <MXS_VOLTAGE_HIGH>;
705 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]706 };
707
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]708 pwm3_pins_b: pwm3@1 {
709 reg = <1>;
710 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]711 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]712 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]713 fsl,drive-strength = <MXS_DRIVE_4mA>;
714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
715 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]716 };
717
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]718 pwm4_pins_a: pwm4@0 {
719 reg = <0>;
720 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]721 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]722 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]723 fsl,drive-strength = <MXS_DRIVE_4mA>;
724 fsl,voltage = <MXS_VOLTAGE_HIGH>;
725 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]726 };
727
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]728 lcdif_24bit_pins_a: lcdif-24bit@0 {
729 reg = <0>;
730 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]731 MX28_PAD_LCD_D00__LCD_D0
732 MX28_PAD_LCD_D01__LCD_D1
733 MX28_PAD_LCD_D02__LCD_D2
734 MX28_PAD_LCD_D03__LCD_D3
735 MX28_PAD_LCD_D04__LCD_D4
736 MX28_PAD_LCD_D05__LCD_D5
737 MX28_PAD_LCD_D06__LCD_D6
738 MX28_PAD_LCD_D07__LCD_D7
739 MX28_PAD_LCD_D08__LCD_D8
740 MX28_PAD_LCD_D09__LCD_D9
741 MX28_PAD_LCD_D10__LCD_D10
742 MX28_PAD_LCD_D11__LCD_D11
743 MX28_PAD_LCD_D12__LCD_D12
744 MX28_PAD_LCD_D13__LCD_D13
745 MX28_PAD_LCD_D14__LCD_D14
746 MX28_PAD_LCD_D15__LCD_D15
747 MX28_PAD_LCD_D16__LCD_D16
748 MX28_PAD_LCD_D17__LCD_D17
749 MX28_PAD_LCD_D18__LCD_D18
750 MX28_PAD_LCD_D19__LCD_D19
751 MX28_PAD_LCD_D20__LCD_D20
752 MX28_PAD_LCD_D21__LCD_D21
753 MX28_PAD_LCD_D22__LCD_D22
754 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]755 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]756 fsl,drive-strength = <MXS_DRIVE_4mA>;
757 fsl,voltage = <MXS_VOLTAGE_HIGH>;
758 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]759 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]760
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]761 lcdif_18bit_pins_a: lcdif-18bit@0 {
762 reg = <0>;
763 fsl,pinmux-ids = <
764 MX28_PAD_LCD_D00__LCD_D0
765 MX28_PAD_LCD_D01__LCD_D1
766 MX28_PAD_LCD_D02__LCD_D2
767 MX28_PAD_LCD_D03__LCD_D3
768 MX28_PAD_LCD_D04__LCD_D4
769 MX28_PAD_LCD_D05__LCD_D5
770 MX28_PAD_LCD_D06__LCD_D6
771 MX28_PAD_LCD_D07__LCD_D7
772 MX28_PAD_LCD_D08__LCD_D8
773 MX28_PAD_LCD_D09__LCD_D9
774 MX28_PAD_LCD_D10__LCD_D10
775 MX28_PAD_LCD_D11__LCD_D11
776 MX28_PAD_LCD_D12__LCD_D12
777 MX28_PAD_LCD_D13__LCD_D13
778 MX28_PAD_LCD_D14__LCD_D14
779 MX28_PAD_LCD_D15__LCD_D15
780 MX28_PAD_LCD_D16__LCD_D16
781 MX28_PAD_LCD_D17__LCD_D17
782 >;
783 fsl,drive-strength = <MXS_DRIVE_4mA>;
784 fsl,voltage = <MXS_VOLTAGE_HIGH>;
785 fsl,pull-up = <MXS_PULL_DISABLE>;
786 };
787
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]788 lcdif_16bit_pins_a: lcdif-16bit@0 {
789 reg = <0>;
790 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]791 MX28_PAD_LCD_D00__LCD_D0
792 MX28_PAD_LCD_D01__LCD_D1
793 MX28_PAD_LCD_D02__LCD_D2
794 MX28_PAD_LCD_D03__LCD_D3
795 MX28_PAD_LCD_D04__LCD_D4
796 MX28_PAD_LCD_D05__LCD_D5
797 MX28_PAD_LCD_D06__LCD_D6
798 MX28_PAD_LCD_D07__LCD_D7
799 MX28_PAD_LCD_D08__LCD_D8
800 MX28_PAD_LCD_D09__LCD_D9
801 MX28_PAD_LCD_D10__LCD_D10
802 MX28_PAD_LCD_D11__LCD_D11
803 MX28_PAD_LCD_D12__LCD_D12
804 MX28_PAD_LCD_D13__LCD_D13
805 MX28_PAD_LCD_D14__LCD_D14
806 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]807 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]808 fsl,drive-strength = <MXS_DRIVE_4mA>;
809 fsl,voltage = <MXS_VOLTAGE_HIGH>;
810 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]811 };
812
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]813 lcdif_sync_pins_a: lcdif-sync@0 {
814 reg = <0>;
815 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]816 MX28_PAD_LCD_RS__LCD_DOTCLK
817 MX28_PAD_LCD_CS__LCD_ENABLE
818 MX28_PAD_LCD_RD_E__LCD_VSYNC
819 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]820 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]821 fsl,drive-strength = <MXS_DRIVE_4mA>;
822 fsl,voltage = <MXS_VOLTAGE_HIGH>;
823 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]824 };
825
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]826 can0_pins_a: can0@0 {
827 reg = <0>;
828 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]829 MX28_PAD_GPMI_RDY2__CAN0_TX
830 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]831 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]832 fsl,drive-strength = <MXS_DRIVE_4mA>;
833 fsl,voltage = <MXS_VOLTAGE_HIGH>;
834 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]835 };
836
837 can1_pins_a: can1@0 {
838 reg = <0>;
839 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]840 MX28_PAD_GPMI_CE2N__CAN1_TX
841 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]842 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]843 fsl,drive-strength = <MXS_DRIVE_4mA>;
844 fsl,voltage = <MXS_VOLTAGE_HIGH>;
845 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]846 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]847
848 spi2_pins_a: spi2@0 {
849 reg = <0>;
850 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]851 MX28_PAD_SSP2_SCK__SSP2_SCK
852 MX28_PAD_SSP2_MOSI__SSP2_CMD
853 MX28_PAD_SSP2_MISO__SSP2_D0
854 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]855 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]856 fsl,drive-strength = <MXS_DRIVE_8mA>;
857 fsl,voltage = <MXS_VOLTAGE_HIGH>;
858 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]859 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]860
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]861 spi3_pins_a: spi3@0 {
862 reg = <0>;
863 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]864 MX28_PAD_AUART2_RX__SSP3_D4
865 MX28_PAD_AUART2_TX__SSP3_D5
866 MX28_PAD_SSP3_SCK__SSP3_SCK
867 MX28_PAD_SSP3_MOSI__SSP3_CMD
868 MX28_PAD_SSP3_MISO__SSP3_D0
869 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]870 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]871 fsl,drive-strength = <MXS_DRIVE_8mA>;
872 fsl,voltage = <MXS_VOLTAGE_HIGH>;
873 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]874 };
875
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]876 spi3_pins_b: spi3@1 {
877 reg = <1>;
878 fsl,pinmux-ids = <
879 MX28_PAD_SSP3_SCK__SSP3_SCK
880 MX28_PAD_SSP3_MOSI__SSP3_CMD
881 MX28_PAD_SSP3_MISO__SSP3_D0
882 MX28_PAD_SSP3_SS0__SSP3_D3
883 >;
884 fsl,drive-strength = <MXS_DRIVE_8mA>;
885 fsl,voltage = <MXS_VOLTAGE_HIGH>;
886 fsl,pull-up = <MXS_PULL_ENABLE>;
887 };
888
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]889 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]890 reg = <0>;
891 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]892 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]893 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]894 fsl,drive-strength = <MXS_DRIVE_12mA>;
895 fsl,voltage = <MXS_VOLTAGE_HIGH>;
896 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]897 };
898
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]899 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]900 reg = <1>;
901 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]902 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]903 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]904 fsl,drive-strength = <MXS_DRIVE_12mA>;
905 fsl,voltage = <MXS_VOLTAGE_HIGH>;
906 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]907 };
908
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]909 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]910 reg = <0>;
911 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]912 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]913 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]914 fsl,drive-strength = <MXS_DRIVE_12mA>;
915 fsl,voltage = <MXS_VOLTAGE_HIGH>;
916 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]917 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]918
919 usb0_id_pins_a: usb0id@0 {
920 reg = <0>;
921 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]922 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]923 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]924 fsl,drive-strength = <MXS_DRIVE_12mA>;
925 fsl,voltage = <MXS_VOLTAGE_HIGH>;
926 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]927 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]928
929 usb0_id_pins_b: usb0id1@0 {
930 reg = <0>;
931 fsl,pinmux-ids = <
932 MX28_PAD_PWM2__USB0_ID
933 >;
934 fsl,drive-strength = <MXS_DRIVE_12mA>;
935 fsl,voltage = <MXS_VOLTAGE_HIGH>;
936 fsl,pull-up = <MXS_PULL_ENABLE>;
937 };
938
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]939 };
940
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]941 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]942 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]943 reg = <0x8001c000 0x2000>;
944 interrupts = <89>;
945 status = "disabled";
946 };
947
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]948 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]949 reg = <0x80022000 0x2000>;
950 status = "disabled";
951 };
952
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]953 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]954 compatible = "fsl,imx28-dma-apbx";
955 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]956 interrupts = <78 79 66 0
957 80 81 68 69
958 70 71 72 73
959 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]960 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]961 "saif0", "saif1", "i2c0", "i2c1",
962 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
963 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
964 #dma-cells = <1>;
965 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]966 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]967 };
968
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]969 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]970 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]971 reg = <0x80028000 0x2000>;
972 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]973 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]974 };
975
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]976 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]977 reg = <0x8002a000 0x2000>;
978 interrupts = <39>;
979 status = "disabled";
980 };
981
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]982 ocotp: ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]983 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
984 #address-cells = <1>;
985 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]986 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]987 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]988 };
989
990 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]991 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]992 status = "disabled";
993 };
994
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]995 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]996 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]997 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]998 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]999 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1000 dmas = <&dma_apbh 13>;
1001 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1002 status = "disabled";
1003 };
1004
1005 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1006 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1007 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1008 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1009 clocks = <&clks 58>, <&clks 58>;
1010 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1011 status = "disabled";
1012 };
1013
1014 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1015 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1016 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1017 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1018 clocks = <&clks 59>, <&clks 59>;
1019 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1020 status = "disabled";
1021 };
1022
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1023 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1024 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1025 status = "disabled";
1026 };
1027
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1028 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1029 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1030 status = "disabled";
1031 };
1032
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1033 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1034 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1035 status = "disabled";
1036 };
1037
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1038 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1039 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1040 status = "disabled";
1041 };
1042
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1043 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1044 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1045 status = "disabled";
1046 };
1047
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1048 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1049 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1050 status = "disabled";
1051 };
1052
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1053 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1054 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1055 status = "disabled";
1056 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1057 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1058
1059 apbx@80040000 {
1060 compatible = "simple-bus";
1061 #address-cells = <1>;
1062 #size-cells = <1>;
1063 reg = <0x80040000 0x40000>;
1064 ranges;
1065
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1066 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]1067 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1068 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1069 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1070 };
1071
1072 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1073 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1074 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1075 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1076 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1077 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1078 dmas = <&dma_apbx 4>;
1079 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1080 status = "disabled";
1081 };
1082
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1083 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1084 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1085 status = "disabled";
1086 };
1087
1088 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1089 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1090 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1091 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1092 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1093 dmas = <&dma_apbx 5>;
1094 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1095 status = "disabled";
1096 };
1097
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1098 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1099 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1100 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1101 interrupts = <10 14 15 16 17 18 19
1102 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1103 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1104 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1105 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1106 };
1107
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1108 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1109 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1110 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1111 dmas = <&dma_apbx 2>;
1112 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1113 status = "disabled";
1114 };
1115
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1116 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1117 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1118 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1119 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1120 };
1121
1122 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1126 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1127 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1128 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1129 dmas = <&dma_apbx 6>;
1130 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1131 status = "disabled";
1132 };
1133
1134 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1138 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1139 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1140 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1141 dmas = <&dma_apbx 7>;
1142 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1143 status = "disabled";
1144 };
1145
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1146 pwm: pwm@80064000 {
1147 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1148 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1149 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1150 #pwm-cells = <2>;
1151 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1152 status = "disabled";
1153 };
1154
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1155 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1156 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1157 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1158 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1159 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1160 };
1161
1162 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1163 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1164 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1165 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1166 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1167 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1168 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1169 status = "disabled";
1170 };
1171
1172 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1173 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1174 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1175 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1176 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1177 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1178 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1179 status = "disabled";
1180 };
1181
1182 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1183 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1184 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1185 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1186 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1187 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1188 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1189 status = "disabled";
1190 };
1191
1192 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1193 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1194 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1195 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1196 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1197 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1198 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1199 status = "disabled";
1200 };
1201
1202 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1203 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1204 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1205 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1206 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1207 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1208 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1209 status = "disabled";
1210 };
1211
1212 duart: serial@80074000 {
1213 compatible = "arm,pl011", "arm,primecell";
1214 reg = <0x80074000 0x1000>;
1215 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1216 clocks = <&clks 45>, <&clks 26>;
1217 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1218 status = "disabled";
1219 };
1220
1221 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1222 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1223 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1224 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1225 status = "disabled";
1226 };
1227
1228 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1229 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1230 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1231 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1232 status = "disabled";
1233 };
1234 };
1235 };
1236
1237 ahb@80080000 {
1238 compatible = "simple-bus";
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 reg = <0x80080000 0x80000>;
1242 ranges;
1243
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1244 usb0: usb@80080000 {
1245 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1246 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1247 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1248 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1249 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1250 status = "disabled";
1251 };
1252
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1253 usb1: usb@80090000 {
1254 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1255 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1256 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1257 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1258 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1259 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1260 status = "disabled";
1261 };
1262
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1263 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1264 reg = <0x800c0000 0x10000>;
1265 status = "disabled";
1266 };
1267
1268 mac0: ethernet@800f0000 {
1269 compatible = "fsl,imx28-fec";
1270 reg = <0x800f0000 0x4000>;
1271 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1272 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1273 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1274 status = "disabled";
1275 };
1276
1277 mac1: ethernet@800f4000 {
1278 compatible = "fsl,imx28-fec";
1279 reg = <0x800f4000 0x4000>;
1280 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1281 clocks = <&clks 57>, <&clks 57>;
1282 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1283 status = "disabled";
1284 };
1285
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1286 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1287 reg = <0x800f8000 0x8000>;
1288 status = "disabled";
1289 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1290 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1291
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]1292 iio-hwmon {
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1293 compatible = "iio-hwmon";
1294 io-channels = <&lradc 8>;
1295 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1296};