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gerrit-public.fairphone.software / kernel / msm-4.19 / 7f415a61cf7accd5a013e05db55602f81ee65e47 / . / arch / arm / boot / dts / am43x-epos-evm.dts
blob: ce7a44daf839a7a8efcc5fc7094721d38a6c0e64 [file] [log] [blame]
Afzal Mohammed4730bcf2013-06-14 19:33:34 +0530[diff] [blame]1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM43x EPOS EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h>
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]16#include <dt-bindings/pwm/pwm.h>
Peter Ujfalusicbfc7e62015-07-02 17:06:22 +0300[diff] [blame]17#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
Afzal Mohammed4730bcf2013-06-14 19:33:34 +0530[diff] [blame]18
19/ {
20 model = "TI AM43x EPOS EVM";
Keerthy69101b22016-02-19 10:08:54 +0530[diff] [blame]21 compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]22
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]23 aliases {
24 display0 = &lcd0;
25 };
26
Lokesh Vutla24a1eb42017-01-18 09:33:24 +0530[diff] [blame]27 chosen {
28 stdout-path = &uart0;
29 };
30
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]31 vmmcsd_fixed: fixedregulator-sd {
32 compatible = "regulator-fixed";
33 regulator-name = "vmmcsd_fixed";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 enable-active-high;
37 };
38
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -0400[diff] [blame]39 vbat: fixedregulator0 {
Peter Ujfalusi7ec341d2015-07-02 17:06:20 +0300[diff] [blame]40 compatible = "regulator-fixed";
41 regulator-name = "vbat";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 regulator-boot-on;
45 };
46
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]47 lcd0: display {
48 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
49 label = "lcd";
50
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]51 panel-timing {
52 clock-frequency = <33000000>;
53 hactive = <800>;
54 vactive = <480>;
55 hfront-porch = <210>;
56 hback-porch = <16>;
57 hsync-len = <30>;
58 vback-porch = <10>;
59 vfront-porch = <22>;
60 vsync-len = <13>;
61 hsync-active = <0>;
62 vsync-active = <0>;
63 de-active = <1>;
64 pixelclk-active = <1>;
65 };
66
67 port {
68 lcd_in: endpoint {
69 remote-endpoint = <&dpi_out>;
70 };
71 };
72 };
73
Javier Martinez Canillas18ad99d2016-08-01 12:46:57 -0400[diff] [blame]74 matrix_keypad: matrix_keypad0 {
Tero Kristod7eaf3c2015-02-25 15:03:57 +0200[diff] [blame]75 compatible = "gpio-matrix-keypad";
76 debounce-delay-ms = <5>;
77 col-scan-delay-us = <2>;
Kabir Sahane0ba01cb2017-09-29 11:44:26 -0500[diff] [blame]78 pinctrl-names = "default", "sleep";
79 pinctrl-0 = <&matrix_keypad_default>;
80 pinctrl-1 = <&matrix_keypad_sleep>;
Tero Kristod7eaf3c2015-02-25 15:03:57 +0200[diff] [blame]81
82 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
83 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
84 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
85 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
86
87 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
88 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
89 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
90 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
91
92 linux,keymap = <0x00000201 /* P1 */
93 0x01000204 /* P4 */
94 0x02000207 /* P7 */
95 0x0300020a /* NUMERIC_STAR */
96 0x00010202 /* P2 */
97 0x01010205 /* P5 */
98 0x02010208 /* P8 */
99 0x03010200 /* P0 */
100 0x00020203 /* P3 */
101 0x01020206 /* P6 */
102 0x02020209 /* P9 */
103 0x0302020b /* NUMERIC_POUND */
104 0x00030067 /* UP */
105 0x0103006a /* RIGHT */
106 0x0203006c /* DOWN */
107 0x03030069>; /* LEFT */
108 };
109
110 backlight {
111 compatible = "pwm-backlight";
112 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
113 brightness-levels = <0 51 53 56 62 75 101 152 255>;
114 default-brightness-level = <8>;
115 };
Peter Ujfalusi22d7fb52015-07-02 17:06:23 +0300[diff] [blame]116
Javier Martinez Canillas4e8603e2016-04-01 16:20:21 -0400[diff] [blame]117 sound0: sound0 {
Peter Ujfalusi22d7fb52015-07-02 17:06:23 +0300[diff] [blame]118 compatible = "simple-audio-card";
119 simple-audio-card,name = "AM43-EPOS-EVM";
120 simple-audio-card,widgets =
121 "Microphone", "Microphone Jack",
122 "Headphone", "Headphone Jack",
123 "Speaker", "Speaker";
124 simple-audio-card,routing =
125 "MIC1LP", "Microphone Jack",
126 "MIC1RP", "Microphone Jack",
127 "MIC1LP", "MICBIAS",
128 "MIC1RP", "MICBIAS",
129 "Headphone Jack", "HPL",
130 "Headphone Jack", "HPR",
131 "Speaker", "SPL",
132 "Speaker", "SPR";
133 simple-audio-card,format = "dsp_b";
134 simple-audio-card,bitclock-master = <&sound0_master>;
135 simple-audio-card,frame-master = <&sound0_master>;
136 simple-audio-card,bitclock-inversion;
137
138 simple-audio-card,cpu {
139 sound-dai = <&mcasp1>;
140 system-clock-frequency = <12000000>;
141 };
142
143 sound0_master: simple-audio-card,codec {
144 sound-dai = <&tlv320aic3111>;
145 system-clock-frequency = <12000000>;
146 };
147 };
Tero Kristod7eaf3c2015-02-25 15:03:57 +0200[diff] [blame]148};
149
150&am43xx_pinmux {
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]151 cpsw_default: cpsw_default {
152 pinctrl-single,pins = <
153 /* Slave 1 */
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]154 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
155 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
156 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
157 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
158 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
159 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
160 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
161 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
162 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]163 >;
164 };
165
166 cpsw_sleep: cpsw_sleep {
167 pinctrl-single,pins = <
168 /* Slave 1 reset value */
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]169 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
170 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
171 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
172 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
173 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
174 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
175 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
176 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
177 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]178 >;
179 };
180
181 davinci_mdio_default: davinci_mdio_default {
182 pinctrl-single,pins = <
183 /* MDIO */
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]184 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
185 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]186 >;
187 };
188
189 davinci_mdio_sleep: davinci_mdio_sleep {
190 pinctrl-single,pins = <
191 /* MDIO reset value */
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]192 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
193 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]194 >;
195 };
196
197 i2c0_pins: pinmux_i2c0_pins {
198 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]199 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
200 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]201 >;
202 };
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]203
Andrew F. Davis74ae6662017-09-29 11:44:23 -0500[diff] [blame]204 nand_flash_x8_default: nand_flash_x8_default {
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]205 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]206 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
207 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
208 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
209 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
210 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
211 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
212 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
213 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
214 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
215 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
216 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
217 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
218 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
219 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
220 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
221 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]222 >;
223 };
Tony Lindgrenf777ba12014-03-02 14:22:03 -0800[diff] [blame]224
Andrew F. Davis74ae6662017-09-29 11:44:23 -0500[diff] [blame]225 nand_flash_x8_sleep: nand_flash_x8_sleep {
226 pinctrl-single,pins = <
227 AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
228 AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
229 AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
230 AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
231 AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
232 AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
233 AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
234 AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
235 AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
236 AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
237 AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
238 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
239 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
240 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
241 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
242 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
243 >;
244 };
245
Andrew F. Davis6aab42b2017-09-29 11:44:22 -0500[diff] [blame]246 ecap0_pins_default: backlight_pins_default {
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]247 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]248 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]249 >;
250 };
Sourav Poddar0aeaf1c2013-12-19 18:03:36 +0530[diff] [blame]251
Andrew F. Davis6aab42b2017-09-29 11:44:22 -0500[diff] [blame]252 ecap0_pins_sleep: backlight_pins_sleep {
253 pinctrl-single,pins = <
254 AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
255 >;
256 };
257
Sourav Poddar0aeaf1c2013-12-19 18:03:36 +0530[diff] [blame]258 i2c2_pins: pinmux_i2c2_pins {
259 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]260 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
261 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
Sourav Poddar0aeaf1c2013-12-19 18:03:36 +0530[diff] [blame]262 >;
263 };
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]264
Andrew F. Davis4178d4a2017-09-29 11:44:20 -0500[diff] [blame]265 spi0_pins_default: pinmux_spi0_pins_default {
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]266 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]267 AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
268 AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
269 AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
270 AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]271 >;
272 };
273
Andrew F. Davis4178d4a2017-09-29 11:44:20 -0500[diff] [blame]274 spi0_pins_sleep: pinmux_spi0_pins_sleep {
275 pinctrl-single,pins = <
276 AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
277 AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
278 AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
279 AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
280 >;
281 };
282
283 spi1_pins_default: pinmux_spi1_pins_default {
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]284 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]285 AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
286 AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
287 AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
288 AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]289 >;
290 };
Balaji T Kd2885db2014-03-03 20:20:20 +0530[diff] [blame]291
Andrew F. Davis4178d4a2017-09-29 11:44:20 -0500[diff] [blame]292 spi1_pins_sleep: pinmux_spi1_pins_sleep {
293 pinctrl-single,pins = <
294 AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
295 AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
296 AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
297 AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
298 >;
299 };
300
Andrew F. Davis21b61462017-09-29 11:44:25 -0500[diff] [blame]301 mmc1_pins_default: pinmux_mmc1_pins_default {
Balaji T Kd2885db2014-03-03 20:20:20 +0530[diff] [blame]302 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]303 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
Balaji T Kd2885db2014-03-03 20:20:20 +0530[diff] [blame]304 >;
305 };
Sourav Poddar2a1a5042014-04-28 19:12:30 +0530[diff] [blame]306
Andrew F. Davis21b61462017-09-29 11:44:25 -0500[diff] [blame]307 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
308 pinctrl-single,pins = <
309 AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7)
310 >;
311 };
312
Kabir Sahane0ba01cb2017-09-29 11:44:26 -0500[diff] [blame]313 matrix_keypad_default: matrix_keypad_default {
314 pinctrl-single,pins = <
315 AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */
316 AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */
317 AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */
318 AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */
319 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
320 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
321 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */
322 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */
323 >;
324 };
325
326 matrix_keypad_sleep: matrix_keypad_sleep {
327 pinctrl-single,pins = <
328 AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7)
329 AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7)
330 AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7)
331 AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7)
332 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7)
333 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7)
334 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7)
335 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7)
336 >;
337 };
338
Andrew F. Davisc5824132017-09-29 11:44:21 -0500[diff] [blame]339 qspi1_pins_default: qspi1_pins_default {
Sourav Poddar2a1a5042014-04-28 19:12:30 +0530[diff] [blame]340 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]341 AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
342 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
343 AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
344 AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
345 AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
346 AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
Sourav Poddar2a1a5042014-04-28 19:12:30 +0530[diff] [blame]347 >;
348 };
Roger Quadros6cfcb5b2014-04-30 15:43:24 +0300[diff] [blame]349
Andrew F. Davisc5824132017-09-29 11:44:21 -0500[diff] [blame]350 qspi1_pins_sleep: qspi1_pins_sleep {
351 pinctrl-single,pins = <
352 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
353 AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
354 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
355 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
356 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
357 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
358 >;
359 };
360
Andrew F. Davisac455072017-09-29 11:44:24 -0500[diff] [blame]361 pixcir_ts_pins_default: pixcir_ts_pins_default {
Roger Quadros6cfcb5b2014-04-30 15:43:24 +0300[diff] [blame]362 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]363 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
Roger Quadros6cfcb5b2014-04-30 15:43:24 +0300[diff] [blame]364 >;
365 };
Sourav Poddar741cac52014-05-08 11:30:07 +0530[diff] [blame]366
Andrew F. Davisac455072017-09-29 11:44:24 -0500[diff] [blame]367 pixcir_ts_pins_sleep: pixcir_ts_pins_sleep {
368 pinctrl-single,pins = <
369 AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
370 >;
371 };
372
Sourav Poddar741cac52014-05-08 11:30:07 +0530[diff] [blame]373 hdq_pins: pinmux_hdq_pins {
374 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]375 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
Sourav Poddar741cac52014-05-08 11:30:07 +0530[diff] [blame]376 >;
377 };
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]378
379 dss_pins: dss_pins {
380 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]381 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
382 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
383 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
384 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
385 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
386 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
387 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
388 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
389 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
390 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
391 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
392 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
393 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
394 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
395 AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
396 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
397 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
398 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
399 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
400 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
401 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
402 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
403 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
404 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
405 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
406 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
407 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
408 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]409 >;
410 };
411
Peter Ujfalusi56fd3dc2015-07-02 17:06:19 +0300[diff] [blame]412 display_mux_pins: display_mux_pins {
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]413 pinctrl-single,pins = <
414 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]415 AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]416 >;
417 };
Benoit Parrotd890edc2014-12-18 21:54:12 +0530[diff] [blame]418
419 vpfe1_pins_default: vpfe1_pins_default {
420 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]421 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
422 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
423 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
424 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
425 AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
426 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
427 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
428 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
429 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
430 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
431 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
432 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
433 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
Benoit Parrotd890edc2014-12-18 21:54:12 +0530[diff] [blame]434 >;
435 };
436
437 vpfe1_pins_sleep: vpfe1_pins_sleep {
438 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]439 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
440 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
441 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
442 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
443 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
444 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
445 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
446 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
447 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
448 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
449 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
450 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
451 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
Benoit Parrotd890edc2014-12-18 21:54:12 +0530[diff] [blame]452 >;
453 };
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]454
Andrew F. Davis7f415a62017-09-29 11:44:27 -0500[diff] [blame^]455 uart0_pins_default: uart0_pins_default {
456 pinctrl-single,pins = <
457 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
458 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
459 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
460 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
461 >;
462 };
463
464 uart0_pins_sleep: uart0_pins_sleep {
465 pinctrl-single,pins = <
466 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
467 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
468 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
469 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
470 >;
471 };
472
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]473 mcasp1_pins: mcasp1_pins {
474 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]475 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
476 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
477 AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
478 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]479 >;
480 };
481
482 mcasp1_sleep_pins: mcasp1_sleep_pins {
483 pinctrl-single,pins = <
Javier Martinez Canillas43ade6a2015-11-13 01:53:57 -0300[diff] [blame]484 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
485 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
486 AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
487 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]488 >;
489 };
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]490};
491
492&mmc1 {
493 status = "okay";
494 vmmc-supply = <&vmmcsd_fixed>;
495 bus-width = <4>;
Andrew F. Davis21b61462017-09-29 11:44:25 -0500[diff] [blame]496 pinctrl-names = "default", "sleep";
497 pinctrl-0 = <&mmc1_pins_default>;
498 pinctrl-1 = <&mmc1_pins_sleep>;
Mugunthan V N0731cbd2015-10-12 14:37:11 +0530[diff] [blame]499 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]500};
501
502&mac {
503 pinctrl-names = "default", "sleep";
504 pinctrl-0 = <&cpsw_default>;
505 pinctrl-1 = <&cpsw_sleep>;
506 status = "okay";
507};
508
509&davinci_mdio {
510 pinctrl-names = "default", "sleep";
511 pinctrl-0 = <&davinci_mdio_default>;
512 pinctrl-1 = <&davinci_mdio_sleep>;
513 status = "okay";
514};
515
516&cpsw_emac0 {
517 phy_id = <&davinci_mdio>, <16>;
518 phy-mode = "rmii";
519};
520
521&cpsw_emac1 {
522 phy_id = <&davinci_mdio>, <1>;
523 phy-mode = "rmii";
524};
525
George Cherianfe797552014-06-06 11:47:34 +0530[diff] [blame]526&phy_sel {
527 rmii-clock-ext;
528};
529
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]530&i2c0 {
531 status = "okay";
532 pinctrl-names = "default";
533 pinctrl-0 = <&i2c0_pins>;
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]534 clock-frequency = <400000>;
535
536 tps65218: tps65218@24 {
537 reg = <0x24>;
538 compatible = "ti,tps65218";
539 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]540 interrupt-controller;
541 #interrupt-cells = <2>;
542
543 dcdc1: regulator-dcdc1 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]544 regulator-name = "vdd_core";
545 regulator-min-microvolt = <912000>;
546 regulator-max-microvolt = <1144000>;
547 regulator-boot-on;
548 regulator-always-on;
549 };
550
551 dcdc2: regulator-dcdc2 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]552 regulator-name = "vdd_mpu";
553 regulator-min-microvolt = <912000>;
554 regulator-max-microvolt = <1378000>;
555 regulator-boot-on;
556 regulator-always-on;
557 };
558
559 dcdc3: regulator-dcdc3 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]560 regulator-name = "vdcdc3";
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]561 regulator-boot-on;
562 regulator-always-on;
563 };
564
Peter Ujfalusi7ec341d2015-07-02 17:06:20 +0300[diff] [blame]565 dcdc4: regulator-dcdc4 {
Peter Ujfalusi7ec341d2015-07-02 17:06:20 +0300[diff] [blame]566 regulator-name = "vdcdc4";
567 regulator-min-microvolt = <3300000>;
568 regulator-max-microvolt = <3300000>;
569 regulator-boot-on;
570 regulator-always-on;
571 };
572
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]573 dcdc5: regulator-dcdc5 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]574 regulator-name = "v1_0bat";
575 regulator-min-microvolt = <1000000>;
576 regulator-max-microvolt = <1000000>;
577 };
578
579 dcdc6: regulator-dcdc6 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]580 regulator-name = "v1_8bat";
581 regulator-min-microvolt = <1800000>;
582 regulator-max-microvolt = <1800000>;
583 };
584
585 ldo1: regulator-ldo1 {
Keerthy497d64a2014-07-09 11:06:30 +0530[diff] [blame]586 regulator-min-microvolt = <1800000>;
587 regulator-max-microvolt = <1800000>;
588 regulator-boot-on;
589 regulator-always-on;
590 };
591 };
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]592
593 at24@50 {
Javier Martinez Canillas05e7d622017-05-23 15:34:31 +0200[diff] [blame]594 compatible = "atmel,24c256";
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]595 pagesize = <64>;
596 reg = <0x50>;
597 };
598
599 pixcir_ts@5c {
Roger Quadros6cfcb5b2014-04-30 15:43:24 +0300[diff] [blame]600 compatible = "pixcir,pixcir_tangoc";
Andrew F. Davisac455072017-09-29 11:44:24 -0500[diff] [blame]601 pinctrl-names = "default", "sleep";
602 pinctrl-0 = <&pixcir_ts_pins_default>;
603 pinctrl-1 = <&pixcir_ts_pins_sleep>;
604
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]605 reg = <0x5c>;
606 interrupt-parent = <&gpio1>;
Grygorii Strashko95e7d032015-12-28 15:52:39 +0200[diff] [blame]607 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]608
609 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
610
Roger Quadros342666c2014-07-28 10:10:58 -0700[diff] [blame]611 touchscreen-size-x = <1024>;
612 touchscreen-size-y = <600>;
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]613 };
Peter Ujfalusicbfc7e62015-07-02 17:06:22 +0300[diff] [blame]614
615 tlv320aic3111: tlv320aic3111@18 {
Peter Ujfalusi22d7fb52015-07-02 17:06:23 +0300[diff] [blame]616 #sound-dai-cells = <0>;
Peter Ujfalusicbfc7e62015-07-02 17:06:22 +0300[diff] [blame]617 compatible = "ti,tlv320aic3111";
618 reg = <0x18>;
619 status = "okay";
620
621 ai31xx-micbias-vg = <MICBIAS_2_0V>;
622
623 /* Regulators */
624 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
625 SPRVDD-supply = <&vbat>; /* vbat */
626 SPLVDD-supply = <&vbat>; /* vbat */
627 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
628 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
629 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
630 };
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]631};
632
Sourav Poddar0aeaf1c2013-12-19 18:03:36 +0530[diff] [blame]633&i2c2 {
634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c2_pins>;
636 status = "okay";
637};
638
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]639&gpio0 {
640 status = "okay";
641};
642
643&gpio1 {
644 status = "okay";
645};
646
647&gpio2 {
Peter Ujfalusi56fd3dc2015-07-02 17:06:19 +0300[diff] [blame]648 pinctrl-names = "default";
649 pinctrl-0 = <&display_mux_pins>;
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]650 status = "okay";
Peter Ujfalusi56fd3dc2015-07-02 17:06:19 +0300[diff] [blame]651
652 p1 {
653 /*
654 * SelLCDorHDMI selects between display and audio paths:
655 * Low: HDMI display with audio via HDMI
656 * High: LCD display with analog audio via aic3111 codec
657 */
658 gpio-hog;
659 gpios = <1 GPIO_ACTIVE_HIGH>;
660 output-high;
661 line-name = "SelLCDorHDMI";
662 };
Mugunthan V Ne54686e2013-10-11 00:44:54 +0530[diff] [blame]663};
664
665&gpio3 {
666 status = "okay";
Afzal Mohammed4730bcf2013-06-14 19:33:34 +0530[diff] [blame]667};
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]668
669&elm {
670 status = "okay";
671};
672
673&gpmc {
Roger Quadros331bbb52014-09-02 16:57:07 +0300[diff] [blame]674 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
Andrew F. Davis74ae6662017-09-29 11:44:23 -0500[diff] [blame]675 pinctrl-names = "default", "sleep";
676 pinctrl-0 = <&nand_flash_x8_default>;
677 pinctrl-1 = <&nand_flash_x8_sleep>;
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200[diff] [blame]678 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]679 nand@0,0 {
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200[diff] [blame]680 compatible = "ti,omap2-nand";
Tony Lindgrene2c5eb72014-10-29 17:16:47 -0700[diff] [blame]681 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
Roger Quadrosbe3f39c2016-02-23 18:37:19 +0200[diff] [blame]682 interrupt-parent = <&gpmc>;
683 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
684 <1 IRQ_TYPE_NONE>; /* termcount */
Roger Quadros99a41012016-04-07 13:25:38 +0300[diff] [blame]685 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
Franklin S Cooper Jr78b02c32017-07-25 21:15:51 -0500[diff] [blame]686 ti,nand-xfer-type = "prefetch-dma";
Roger Quadrosdb01e6c2014-09-02 16:57:02 +0300[diff] [blame]687 ti,nand-ecc-opt = "bch16";
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]688 ti,elm-id = <&elm>;
689 nand-bus-width = <8>;
690 gpmc,device-width = <1>;
691 gpmc,sync-clk-ps = <0>;
692 gpmc,cs-on-ns = <0>;
693 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
694 gpmc,cs-wr-off-ns = <40>;
695 gpmc,adv-on-ns = <0>; /* cs-on-ns */
696 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
697 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
698 gpmc,we-on-ns = <0>; /* cs-on-ns */
699 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
700 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
701 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
702 gpmc,access-ns = <30>; /* tCEA + 4*/
703 gpmc,rd-cycle-ns = <40>;
704 gpmc,wr-cycle-ns = <40>;
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]705 gpmc,bus-turnaround-ns = <0>;
706 gpmc,cycle2cycle-delay-ns = <0>;
707 gpmc,clk-activation-ns = <0>;
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]708 gpmc,wr-access-ns = <40>;
709 gpmc,wr-data-mux-bus-ns = <0>;
710 /* MTD partition table */
711 /* All SPL-* partitions are sized to minimal length
712 * which can be independently programmable. For
713 * NAND flash this is equal to size of erase-block */
714 #address-cells = <1>;
715 #size-cells = <1>;
716 partition@0 {
717 label = "NAND.SPL";
718 reg = <0x00000000 0x00040000>;
719 };
720 partition@1 {
721 label = "NAND.SPL.backup1";
722 reg = <0x00040000 0x00040000>;
723 };
724 partition@2 {
725 label = "NAND.SPL.backup2";
726 reg = <0x00080000 0x00040000>;
727 };
728 partition@3 {
729 label = "NAND.SPL.backup3";
730 reg = <0x000C0000 0x00040000>;
731 };
732 partition@4 {
733 label = "NAND.u-boot-spl-os";
734 reg = <0x00100000 0x00080000>;
735 };
736 partition@5 {
737 label = "NAND.u-boot";
738 reg = <0x00180000 0x00100000>;
739 };
740 partition@6 {
741 label = "NAND.u-boot-env";
742 reg = <0x00280000 0x00040000>;
743 };
744 partition@7 {
745 label = "NAND.u-boot-env.backup1";
746 reg = <0x002C0000 0x00040000>;
747 };
748 partition@8 {
749 label = "NAND.kernel";
750 reg = <0x00300000 0x00700000>;
751 };
752 partition@9 {
753 label = "NAND.file-system";
Pekon Guptac4de4ec2014-05-19 14:45:48 +0530[diff] [blame]754 reg = <0x00a00000 0x1f600000>;
Pekon Guptaf68e3552014-02-05 18:58:34 +0530[diff] [blame]755 };
756 };
757};
Tony Lindgrenf777ba12014-03-02 14:22:03 -0800[diff] [blame]758
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]759&epwmss0 {
760 status = "okay";
761};
762
Vignesh R0f39f7b2014-11-21 15:44:22 +0530[diff] [blame]763&tscadc {
764 status = "okay";
765
766 adc {
767 ti,adc-channels = <0 1 2 3 4 5 6 7>;
768 };
769};
770
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]771&ecap0 {
772 status = "okay";
Andrew F. Davis6aab42b2017-09-29 11:44:22 -0500[diff] [blame]773 pinctrl-names = "default", "sleep";
774 pinctrl-0 = <&ecap0_pins_default>;
775 pinctrl-1 = <&ecap0_pins_sleep>;
Sourav Poddar2e3a9382013-12-19 18:03:34 +0530[diff] [blame]776};
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]777
778&spi0 {
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]779 status = "okay";
Andrew F. Davis4178d4a2017-09-29 11:44:20 -0500[diff] [blame]780 pinctrl-names = "default", "sleep";
781 pinctrl-0 = <&spi0_pins_default>;
782 pinctrl-1 = <&spi0_pins_sleep>;
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]783};
784
785&spi1 {
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]786 status = "okay";
Andrew F. Davis4178d4a2017-09-29 11:44:20 -0500[diff] [blame]787 pinctrl-names = "default", "sleep";
788 pinctrl-0 = <&spi1_pins_default>;
789 pinctrl-1 = <&spi1_pins_sleep>;
Sourav Poddar416f3d52013-12-19 18:03:37 +0530[diff] [blame]790};
George Cherian61d59242014-03-19 15:40:03 +0530[diff] [blame]791
792&usb2_phy1 {
793 status = "okay";
794};
795
796&usb1 {
797 dr_mode = "peripheral";
798 status = "okay";
799};
800
801&usb2_phy2 {
802 status = "okay";
803};
804
805&usb2 {
806 dr_mode = "host";
807 status = "okay";
808};
Sourav Poddar2a1a5042014-04-28 19:12:30 +0530[diff] [blame]809
810&qspi {
Roger Quadros331bbb52014-09-02 16:57:07 +0300[diff] [blame]811 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
Andrew F. Davisc5824132017-09-29 11:44:21 -0500[diff] [blame]812 pinctrl-names = "default", "sleep";
813 pinctrl-0 = <&qspi1_pins_default>;
814 pinctrl-1 = <&qspi1_pins_sleep>;
Sourav Poddar2a1a5042014-04-28 19:12:30 +0530[diff] [blame]815
816 spi-max-frequency = <48000000>;
817 m25p80@0 {
818 compatible = "mx66l51235l";
819 spi-max-frequency = <48000000>;
820 reg = <0>;
821 spi-cpol;
822 spi-cpha;
823 spi-tx-bus-width = <1>;
824 spi-rx-bus-width = <4>;
825 #address-cells = <1>;
826 #size-cells = <1>;
827
828 /* MTD partition table.
829 * The ROM checks the first 512KiB
830 * for a valid file to boot(XIP).
831 */
832 partition@0 {
833 label = "QSPI.U_BOOT";
834 reg = <0x00000000 0x000080000>;
835 };
836 partition@1 {
837 label = "QSPI.U_BOOT.backup";
838 reg = <0x00080000 0x00080000>;
839 };
840 partition@2 {
841 label = "QSPI.U-BOOT-SPL_OS";
842 reg = <0x00100000 0x00010000>;
843 };
844 partition@3 {
845 label = "QSPI.U_BOOT_ENV";
846 reg = <0x00110000 0x00010000>;
847 };
848 partition@4 {
849 label = "QSPI.U-BOOT-ENV.backup";
850 reg = <0x00120000 0x00010000>;
851 };
852 partition@5 {
853 label = "QSPI.KERNEL";
854 reg = <0x00130000 0x0800000>;
855 };
856 partition@6 {
857 label = "QSPI.FILESYSTEM";
858 reg = <0x00930000 0x36D0000>;
859 };
860 };
861};
Sourav Poddar741cac52014-05-08 11:30:07 +0530[diff] [blame]862
863&hdq {
864 status = "okay";
865 pinctrl-names = "default";
866 pinctrl-0 = <&hdq_pins>;
867};
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]868
869&dss {
870 status = "ok";
871
872 pinctrl-names = "default";
873 pinctrl-0 = <&dss_pins>;
874
875 port {
Javier Martinez Canillasbc8bffd02016-06-27 15:21:03 -0400[diff] [blame]876 dpi_out: endpoint {
Tomi Valkeinen999c3f12014-05-02 13:54:21 +0300[diff] [blame]877 remote-endpoint = <&lcd_in>;
878 data-lines = <24>;
879 };
880 };
881};
Benoit Parrotd890edc2014-12-18 21:54:12 +0530[diff] [blame]882
883&vpfe1 {
884 status = "okay";
885 pinctrl-names = "default", "sleep";
886 pinctrl-0 = <&vpfe1_pins_default>;
887 pinctrl-1 = <&vpfe1_pins_sleep>;
888
889 port {
890 vpfe1_ep: endpoint {
891 /* remote-endpoint = <&sensor>; add once we have it */
892 ti,am437x-vpfe-interface = <0>;
893 bus-width = <8>;
894 hsync-active = <0>;
895 vsync-active = <0>;
896 };
897 };
898};
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]899
Andrew F. Davis7f415a62017-09-29 11:44:27 -0500[diff] [blame^]900&uart0 {
901 status = "okay";
902 pinctrl-names = "default", "sleep";
903 pinctrl-0 = <&uart0_pins_default>;
904 pinctrl-1 = <&uart0_pins_sleep>;
905};
906
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]907&mcasp1 {
Peter Ujfalusi22d7fb52015-07-02 17:06:23 +0300[diff] [blame]908 #sound-dai-cells = <0>;
Peter Ujfalusi06e2bf62015-07-02 17:06:21 +0300[diff] [blame]909 pinctrl-names = "default", "sleep";
910 pinctrl-0 = <&mcasp1_pins>;
911 pinctrl-1 = <&mcasp1_sleep_pins>;
912
913 status = "okay";
914
915 op-mode = <0>; /* MCASP_IIS_MODE */
916 tdm-slots = <2>;
917 /* 4 serializer */
918 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
919 1 2 0 0
920 >;
921 tx-num-evt = <32>;
922 rx-num-evt = <32>;
923};
Lokesh Vutlacfe15802016-03-08 12:24:35 +0530[diff] [blame]924
925&synctimer_32kclk {
926 assigned-clocks = <&mux_synctimer32k_ck>;
927 assigned-clock-parents = <&clkdiv32k_ick>;
928};