Blame - drivers/scsi/qla2xxx/qla_dbg.c - kernel/msm-4.19

blob: df132fec6d86c98c29417c38f63eaf3a9df3e504 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	14	* \| Module Init and Probe \| 0x014f \| 0x4b,0xba,0xfa \|
Giridhar Malavali	754d124	2013-06-25 11:27:16 -0400	[diff] [blame]	15	* \| Mailbox commands \| 0x117a \| 0x111a-0x111b \|
Joe Carnuccio	e9f4f41	2013-03-25 02:21:36 -0400	[diff] [blame]	16	* \| \| \| 0x1155-0x1158 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	17	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	18	* \| \| \| 0x2011-0x2012, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	19	* \| \| \| 0x2016 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	20	* \| Queue Command and IO tracing \| 0x3058 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	21	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	22	* \| \| \| 0x303d-0x3041 \|
				23	* \| \| \| 0x302d,0x3033 \|
				24	* \| \| \| 0x3036,0x3038 \|
				25	* \| \| \| 0x303a \|
				26	* \| DPC Thread \| 0x4022 \| 0x4002,0x4013 \|
				27	* \| Async Events \| 0x5081 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	28	* \| \| \| 0x5047,0x5052 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	29	* \| \| \| 0x5040,0x5075 \|
Giridhar Malavali	5988aeb	2012-05-15 14:34:12 -0400	[diff] [blame]	30	* \| Timer Routines \| 0x6011 \| \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	31	* \| User Space Interactions \| 0x70dd \| 0x7018,0x702e, \|
Saurav Kashyap	78d56df	2013-01-30 03:34:42 -0500	[diff] [blame]	32	* \| \| \| 0x7020,0x7024, \|
Joe Carnuccio	733a95b	2012-02-09 11:15:55 -0800	[diff] [blame]	33	* \| \| \| 0x7039,0x7045, \|
				34	* \| \| \| 0x7073-0x7075, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	35	* \| \| \| 0x707b,0x708c, \|
Saurav Kashyap	a9b6f72	2012-08-22 14:21:01 -0400	[diff] [blame]	36	* \| \| \| 0x70a5,0x70a6, \|
				37	* \| \| \| 0x70a8,0x70ab, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	38	* \| \| \| 0x70ad-0x70ae, \|
Bart Van Assche	090fc2e	2013-06-25 11:27:22 -0400	[diff] [blame]	39	* \| \| \| 0x70d1-0x70da, \|
Bart Van Assche	a44c72f	2013-06-25 11:27:23 -0400	[diff] [blame]	40	* \| \| \| 0x7047,0x703b \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	41	* \| Task Management \| 0x803c \| 0x8025-0x8026 \|
				42	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	43	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	44	* \| Virtual Port \| 0xa007 \| \|
Saurav Kashyap	6c31555	2013-02-08 01:57:53 -0500	[diff] [blame]	45	* \| ISP82XX Specific \| 0xb086 \| 0xb002,0xb024 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	46	* \| MultiQ \| 0xc00c \| \|
				47	* \| Misc \| 0xd010 \| \|
Arun Easi	33c36c0	2013-01-30 03:34:41 -0500	[diff] [blame]	48	* \| Target Mode \| 0xe070 \| \|
Arun Easi	aa230bc	2013-01-30 03:34:39 -0500	[diff] [blame]	49	* \| Target Mode Management \| 0xf072 \| \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	50	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	51	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	52	*/
				53
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	54	#include "qla_def.h"
				55
				56	#include <linux/delay.h>
				57
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	58	static uint32_t ql_dbg_offset = 0x800;
				59
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	60	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	61	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	62	{
				63	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				64	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				65	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				66	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				67
				68	fw_dump->vendor = htonl(ha->pdev->vendor);
				69	fw_dump->device = htonl(ha->pdev->device);
				70	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				71	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				72	}
				73
				74	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	75	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	76	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	77	struct req_que *req = ha->req_q_map[0];
				78	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	79	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	80	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	81	sizeof(request_t));
				82
				83	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	84	ptr += req->length * sizeof(request_t);
				85	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	86	sizeof(response_t));
				87
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	88	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	89	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	90
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	91	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	92	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	93	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	94	{
				95	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	96	uint32_t cnt, stat, timer, dwords, idx;
				97	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	98	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	99	dma_addr_t dump_dma = ha->gid_list_dma;
				100	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	101
				102	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	103	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	104
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	105	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	106	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				107
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	108	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	109	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				110	cnt += dwords, addr += dwords) {
				111	if (cnt + dwords > ram_dwords)
				112	dwords = ram_dwords - cnt;
				113
				114	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				115	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				116
				117	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				118	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				119	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				120	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				121
				122	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				123	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	124	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				125
				126	for (timer = 6000000; timer; timer--) {
				127	/* Check for pending interrupts. */
				128	stat = RD_REG_DWORD(&reg->host_status);
				129	if (stat & HSRX_RISC_INT) {
				130	stat &= 0xff;
				131
				132	if (stat == 0x1 \|\| stat == 0x2 \|\|
				133	stat == 0x10 \|\| stat == 0x11) {
				134	set_bit(MBX_INTERRUPT,
				135	&ha->mbx_cmd_flags);
				136
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	137	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	138
				139	WRT_REG_DWORD(&reg->hccr,
				140	HCCRX_CLR_RISC_INT);
				141	RD_REG_DWORD(&reg->hccr);
				142	break;
				143	}
				144
				145	/* Clear this intr; it wasn't a mailbox intr */
				146	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				147	RD_REG_DWORD(&reg->hccr);
				148	}
				149	udelay(5);
				150	}
				151
				152	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	153	rval = mb0 & MBS_MASK;
				154	for (idx = 0; idx < dwords; idx++)
				155	ram[cnt + idx] = swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	156	} else {
				157	rval = QLA_FUNCTION_FAILED;
				158	}
				159	}
				160
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	161	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	162	return rval;
				163	}
				164
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	165	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	166	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	167	uint32_t cram_size, void **nxt)
				168	{
				169	int rval;
				170
				171	/* Code RAM. */
				172	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				173	if (rval != QLA_SUCCESS)
				174	return rval;
				175
				176	/* External Memory. */
				177	return qla24xx_dump_ram(ha, 0x100000, *nxt,
				178	ha->fw_memory_size - 0x100000 + 1, nxt);
				179	}
				180
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	181	static uint32_t *
				182	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				183	uint32_t count, uint32_t *buf)
				184	{
				185	uint32_t __iomem *dmp_reg;
				186
				187	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				188	dmp_reg = &reg->iobase_window;
				189	while (count--)
				190	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				191
				192	return buf;
				193	}
				194
				195	static inline int
				196	qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
				197	{
				198	int rval = QLA_SUCCESS;
				199	uint32_t cnt;
				200
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	201	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	aed1088	2009-06-03 09:55:26 -0700	[diff] [blame]	202	for (cnt = 30000;
				203	((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	204	rval == QLA_SUCCESS; cnt--) {
				205	if (cnt)
				206	udelay(100);
				207	else
				208	rval = QLA_FUNCTION_TIMEOUT;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	209	}
				210
				211	return rval;
				212	}
				213
				214	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	215	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	216	{
				217	int rval = QLA_SUCCESS;
				218	uint32_t cnt;
				219	uint16_t mb0, wd;
				220	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				221
				222	/* Reset RISC. */
				223	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				224	for (cnt = 0; cnt < 30000; cnt++) {
				225	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				226	break;
				227
				228	udelay(10);
				229	}
				230
				231	WRT_REG_DWORD(&reg->ctrl_status,
				232	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				233	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				234
				235	udelay(100);
				236	/* Wait for firmware to complete NVRAM accesses. */
				237	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				238	for (cnt = 10000 ; cnt && mb0; cnt--) {
				239	udelay(5);
				240	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				241	barrier();
				242	}
				243
				244	/* Wait for soft-reset to complete. */
				245	for (cnt = 0; cnt < 30000; cnt++) {
				246	if ((RD_REG_DWORD(&reg->ctrl_status) &
				247	CSRX_ISP_SOFT_RESET) == 0)
				248	break;
				249
				250	udelay(10);
				251	}
				252	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				253	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				254
				255	for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
				256	rval == QLA_SUCCESS; cnt--) {
				257	if (cnt)
				258	udelay(100);
				259	else
				260	rval = QLA_FUNCTION_TIMEOUT;
				261	}
				262
				263	return rval;
				264	}
				265
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	266	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	267	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	268	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	269	{
				270	int rval;
				271	uint32_t cnt, stat, timer, words, idx;
				272	uint16_t mb0;
				273	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				274	dma_addr_t dump_dma = ha->gid_list_dma;
				275	uint16_t dump = (uint16_t )ha->gid_list;
				276
				277	rval = QLA_SUCCESS;
				278	mb0 = 0;
				279
				280	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				281	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				282
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	283	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	284	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				285	cnt += words, addr += words) {
				286	if (cnt + words > ram_words)
				287	words = ram_words - cnt;
				288
				289	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				290	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				291
				292	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				293	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				294	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				295	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				296
				297	WRT_MAILBOX_REG(ha, reg, 4, words);
				298	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				299
				300	for (timer = 6000000; timer; timer--) {
				301	/* Check for pending interrupts. */
				302	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				303	if (stat & HSR_RISC_INT) {
				304	stat &= 0xff;
				305
				306	if (stat == 0x1 \|\| stat == 0x2) {
				307	set_bit(MBX_INTERRUPT,
				308	&ha->mbx_cmd_flags);
				309
				310	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				311
				312	/* Release mailbox registers. */
				313	WRT_REG_WORD(&reg->semaphore, 0);
				314	WRT_REG_WORD(&reg->hccr,
				315	HCCR_CLR_RISC_INT);
				316	RD_REG_WORD(&reg->hccr);
				317	break;
				318	} else if (stat == 0x10 \|\| stat == 0x11) {
				319	set_bit(MBX_INTERRUPT,
				320	&ha->mbx_cmd_flags);
				321
				322	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				323
				324	WRT_REG_WORD(&reg->hccr,
				325	HCCR_CLR_RISC_INT);
				326	RD_REG_WORD(&reg->hccr);
				327	break;
				328	}
				329
				330	/* clear this intr; it wasn't a mailbox intr */
				331	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				332	RD_REG_WORD(&reg->hccr);
				333	}
				334	udelay(5);
				335	}
				336
				337	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				338	rval = mb0 & MBS_MASK;
				339	for (idx = 0; idx < words; idx++)
				340	ram[cnt + idx] = swab16(dump[idx]);
				341	} else {
				342	rval = QLA_FUNCTION_FAILED;
				343	}
				344	}
				345
				346	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				347	return rval;
				348	}
				349
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	350	static inline void
				351	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				352	uint16_t *buf)
				353	{
				354	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				355
				356	while (count--)
				357	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				358	}
				359
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	360	static inline void *
				361	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				362	{
				363	if (!ha->eft)
				364	return ptr;
				365
				366	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				367	return ptr + ntohl(ha->fw_dump->eft_size);
				368	}
				369
				370	static inline void *
				371	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				372	{
				373	uint32_t cnt;
				374	uint32_t *iter_reg;
				375	struct qla2xxx_fce_chain *fcec = ptr;
				376
				377	if (!ha->fce)
				378	return ptr;
				379
				380	*last_chain = &fcec->type;
				381	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				382	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				383	fce_calc_size(ha->fce_bufs));
				384	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				385	fcec->addr_l = htonl(LSD(ha->fce_dma));
				386	fcec->addr_h = htonl(MSD(ha->fce_dma));
				387
				388	iter_reg = fcec->eregs;
				389	for (cnt = 0; cnt < 8; cnt++)
				390	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				391
				392	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				393
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	394	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	395	}
				396
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	397	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	398	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				399	uint32_t **last_chain)
				400	{
				401	struct qla2xxx_mqueue_chain *q;
				402	struct qla2xxx_mqueue_header *qh;
				403	uint32_t num_queues;
				404	int que;
				405	struct {
				406	int length;
				407	void *ring;
				408	} aq, *aqp;
				409
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	410	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	411	return ptr;
				412
				413	num_queues = 1;
				414	aqp = &aq;
				415	aqp->length = ha->tgt.atio_q_length;
				416	aqp->ring = ha->tgt.atio_ring;
				417
				418	for (que = 0; que < num_queues; que++) {
				419	/* aqp = ha->atio_q_map[que]; */
				420	q = ptr;
				421	*last_chain = &q->type;
				422	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				423	q->chain_size = htonl(
				424	sizeof(struct qla2xxx_mqueue_chain) +
				425	sizeof(struct qla2xxx_mqueue_header) +
				426	(aqp->length * sizeof(request_t)));
				427	ptr += sizeof(struct qla2xxx_mqueue_chain);
				428
				429	/* Add header. */
				430	qh = ptr;
				431	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				432	qh->number = htonl(que);
				433	qh->size = htonl(aqp->length * sizeof(request_t));
				434	ptr += sizeof(struct qla2xxx_mqueue_header);
				435
				436	/* Add data. */
				437	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				438
				439	ptr += aqp->length * sizeof(request_t);
				440	}
				441
				442	return ptr;
				443	}
				444
				445	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	446	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				447	{
				448	struct qla2xxx_mqueue_chain *q;
				449	struct qla2xxx_mqueue_header *qh;
				450	struct req_que *req;
				451	struct rsp_que *rsp;
				452	int que;
				453
				454	if (!ha->mqenable)
				455	return ptr;
				456
				457	/* Request queues */
				458	for (que = 1; que < ha->max_req_queues; que++) {
				459	req = ha->req_q_map[que];
				460	if (!req)
				461	break;
				462
				463	/* Add chain. */
				464	q = ptr;
				465	*last_chain = &q->type;
				466	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				467	q->chain_size = htonl(
				468	sizeof(struct qla2xxx_mqueue_chain) +
				469	sizeof(struct qla2xxx_mqueue_header) +
				470	(req->length * sizeof(request_t)));
				471	ptr += sizeof(struct qla2xxx_mqueue_chain);
				472
				473	/* Add header. */
				474	qh = ptr;
				475	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				476	qh->number = htonl(que);
				477	qh->size = htonl(req->length * sizeof(request_t));
				478	ptr += sizeof(struct qla2xxx_mqueue_header);
				479
				480	/* Add data. */
				481	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				482	ptr += req->length * sizeof(request_t);
				483	}
				484
				485	/* Response queues */
				486	for (que = 1; que < ha->max_rsp_queues; que++) {
				487	rsp = ha->rsp_q_map[que];
				488	if (!rsp)
				489	break;
				490
				491	/* Add chain. */
				492	q = ptr;
				493	*last_chain = &q->type;
				494	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				495	q->chain_size = htonl(
				496	sizeof(struct qla2xxx_mqueue_chain) +
				497	sizeof(struct qla2xxx_mqueue_header) +
				498	(rsp->length * sizeof(response_t)));
				499	ptr += sizeof(struct qla2xxx_mqueue_chain);
				500
				501	/* Add header. */
				502	qh = ptr;
				503	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				504	qh->number = htonl(que);
				505	qh->size = htonl(rsp->length * sizeof(response_t));
				506	ptr += sizeof(struct qla2xxx_mqueue_header);
				507
				508	/* Add data. */
				509	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				510	ptr += rsp->length * sizeof(response_t);
				511	}
				512
				513	return ptr;
				514	}
				515
				516	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	517	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				518	{
				519	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	520	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	521	struct qla2xxx_mq_chain *mq = ptr;
				522	struct device_reg_25xxmq __iomem *reg;
				523
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	524	if (!ha->mqenable \|\| IS_QLA83XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	525	return ptr;
				526
				527	mq = ptr;
				528	*last_chain = &mq->type;
				529	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				530	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				531
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	532	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				533	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	534	mq->count = htonl(que_cnt);
				535	for (cnt = 0; cnt < que_cnt; cnt++) {
Saurav Kashyap	fa49263	2012-11-21 02:40:29 -0500	[diff] [blame]	536	reg = (struct device_reg_25xxmq __iomem *)
				537	(ha->mqiobase + cnt * QLA_QUE_PAGE);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	538	que_idx = cnt * 4;
				539	mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
				540	mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
				541	mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
				542	mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
				543	}
				544
				545	return ptr + sizeof(struct qla2xxx_mq_chain);
				546	}
				547
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	548	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	549	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				550	{
				551	struct qla_hw_data *ha = vha->hw;
				552
				553	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	554	ql_log(ql_log_warn, vha, 0xd000,
				555	"Failed to dump firmware (%x).\n", rval);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	556	ha->fw_dumped = 0;
				557	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	558	ql_log(ql_log_info, vha, 0xd001,
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	559	"Firmware dump saved to temp buffer (%ld/%p).\n",
				560	vha->host_no, ha->fw_dump);
				561	ha->fw_dumped = 1;
				562	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				563	}
				564	}
				565
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	566	/**
				567	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				568	* @ha: HA context
				569	* @hardware_locked: Called with the hardware_lock
				570	*/
				571	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	572	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	573	{
				574	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	575	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	576	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	577	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	578	uint16_t __iomem *dmp_reg;
				579	unsigned long flags;
				580	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	581	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	582	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	583
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	584	flags = 0;
				585
				586	if (!hardware_locked)
				587	spin_lock_irqsave(&ha->hardware_lock, flags);
				588
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	589	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	590	ql_log(ql_log_warn, vha, 0xd002,
				591	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	592	goto qla2300_fw_dump_failed;
				593	}
				594
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	595	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	596	ql_log(ql_log_warn, vha, 0xd003,
				597	"Firmware has been previously dumped (%p) "
				598	"-- ignoring request.\n",
				599	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	600	goto qla2300_fw_dump_failed;
				601	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	602	fw = &ha->fw_dump->isp.isp23;
				603	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	604
				605	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	606	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	607
				608	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	609	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	610	if (IS_QLA2300(ha)) {
				611	for (cnt = 30000;
				612	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				613	rval == QLA_SUCCESS; cnt--) {
				614	if (cnt)
				615	udelay(100);
				616	else
				617	rval = QLA_FUNCTION_TIMEOUT;
				618	}
				619	} else {
				620	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				621	udelay(10);
				622	}
				623
				624	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	625	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	626	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	627	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	628
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	629	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	630	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	631	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	632
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	633	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	634	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	635	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	636
				637	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	638	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	639
				640	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	641	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	642
				643	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	644	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	645	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	646	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	647
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	648	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	649	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	650
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	651	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	652	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	653
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	654	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	655	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	656
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	657	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	658	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	659
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	660	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	661	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	662
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	663	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	664	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	665
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	666	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	667	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	668
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	669	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	670	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	671
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	672	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	673	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	674
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	675	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	676	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	677
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	678	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	679	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	680
				681	/* Reset RISC. */
				682	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				683	for (cnt = 0; cnt < 30000; cnt++) {
				684	if ((RD_REG_WORD(&reg->ctrl_status) &
				685	CSR_ISP_SOFT_RESET) == 0)
				686	break;
				687
				688	udelay(10);
				689	}
				690	}
				691
				692	if (!IS_QLA2300(ha)) {
				693	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				694	rval == QLA_SUCCESS; cnt--) {
				695	if (cnt)
				696	udelay(100);
				697	else
				698	rval = QLA_FUNCTION_TIMEOUT;
				699	}
				700	}
				701
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	702	/* Get RISC SRAM. */
				703	if (rval == QLA_SUCCESS)
				704	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				705	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	706
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	707	/* Get stack SRAM. */
				708	if (rval == QLA_SUCCESS)
				709	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				710	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	711
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	712	/* Get data SRAM. */
				713	if (rval == QLA_SUCCESS)
				714	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				715	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	716
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	717	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	718	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	719
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	720	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	721
				722	qla2300_fw_dump_failed:
				723	if (!hardware_locked)
				724	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				725	}
				726
				727	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	728	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				729	* @ha: HA context
				730	* @hardware_locked: Called with the hardware_lock
				731	*/
				732	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	733	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	734	{
				735	int rval;
				736	uint32_t cnt, timer;
				737	uint16_t risc_address;
				738	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	739	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	740	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	741	uint16_t __iomem *dmp_reg;
				742	unsigned long flags;
				743	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	744	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	745
				746	risc_address = 0;
				747	mb0 = mb2 = 0;
				748	flags = 0;
				749
				750	if (!hardware_locked)
				751	spin_lock_irqsave(&ha->hardware_lock, flags);
				752
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	753	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	754	ql_log(ql_log_warn, vha, 0xd004,
				755	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	756	goto qla2100_fw_dump_failed;
				757	}
				758
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	759	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	760	ql_log(ql_log_warn, vha, 0xd005,
				761	"Firmware has been previously dumped (%p) "
				762	"-- ignoring request.\n",
				763	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	764	goto qla2100_fw_dump_failed;
				765	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	766	fw = &ha->fw_dump->isp.isp21;
				767	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	768
				769	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	770	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	771
				772	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	773	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	774	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				775	rval == QLA_SUCCESS; cnt--) {
				776	if (cnt)
				777	udelay(100);
				778	else
				779	rval = QLA_FUNCTION_TIMEOUT;
				780	}
				781	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	782	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	783	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	784	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	785
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	786	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	787	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	788	if (cnt == 8)
				789	dmp_reg = &reg->u_end.isp2200.mailbox8;
				790
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	791	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	792	}
				793
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	794	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	795	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	796	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	797
				798	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	799	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	800	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	801	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	802
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	803	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	804	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	805
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	806	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	807	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	808
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	809	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	810	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	811
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	812	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	813	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	814
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	815	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	816	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	817
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	818	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	819	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	820
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	821	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	822	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	823
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	824	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	825	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	826
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	827	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	828	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	829
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	830	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	831	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	832
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	833	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	834	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	835
				836	/* Reset the ISP. */
				837	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				838	}
				839
				840	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				841	rval == QLA_SUCCESS; cnt--) {
				842	if (cnt)
				843	udelay(100);
				844	else
				845	rval = QLA_FUNCTION_TIMEOUT;
				846	}
				847
				848	/* Pause RISC. */
				849	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				850	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				851
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	852	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	853	for (cnt = 30000;
				854	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				855	rval == QLA_SUCCESS; cnt--) {
				856	if (cnt)
				857	udelay(100);
				858	else
				859	rval = QLA_FUNCTION_TIMEOUT;
				860	}
				861	if (rval == QLA_SUCCESS) {
				862	/* Set memory configuration and timing. */
				863	if (IS_QLA2100(ha))
				864	WRT_REG_WORD(&reg->mctr, 0xf1);
				865	else
				866	WRT_REG_WORD(&reg->mctr, 0xf2);
				867	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				868
				869	/* Release RISC. */
				870	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				871	}
				872	}
				873
				874	if (rval == QLA_SUCCESS) {
				875	/* Get RISC SRAM. */
				876	risc_address = 0x1000;
				877	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				878	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				879	}
				880	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				881	cnt++, risc_address++) {
				882	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				883	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				884
				885	for (timer = 6000000; timer != 0; timer--) {
				886	/* Check for pending interrupts. */
				887	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				888	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				889	set_bit(MBX_INTERRUPT,
				890	&ha->mbx_cmd_flags);
				891
				892	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				893	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				894
				895	WRT_REG_WORD(&reg->semaphore, 0);
				896	WRT_REG_WORD(&reg->hccr,
				897	HCCR_CLR_RISC_INT);
				898	RD_REG_WORD(&reg->hccr);
				899	break;
				900	}
				901	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				902	RD_REG_WORD(&reg->hccr);
				903	}
				904	udelay(5);
				905	}
				906
				907	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				908	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	909	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	910	} else {
				911	rval = QLA_FUNCTION_FAILED;
				912	}
				913	}
				914
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	915	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	916	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	917
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	918	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	919
				920	qla2100_fw_dump_failed:
				921	if (!hardware_locked)
				922	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				923	}
				924
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	925	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	926	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	927	{
				928	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	929	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	930	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	931	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	932	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				933	uint32_t __iomem *dmp_reg;
				934	uint32_t *iter_reg;
				935	uint16_t __iomem *mbx_reg;
				936	unsigned long flags;
				937	struct qla24xx_fw_dump *fw;
				938	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	939	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	940	void *nxt_chain;
				941	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	942	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	943
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	944	if (IS_QLA82XX(ha))
				945	return;
				946
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	947	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	948	flags = 0;
				949
				950	if (!hardware_locked)
				951	spin_lock_irqsave(&ha->hardware_lock, flags);
				952
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	953	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	954	ql_log(ql_log_warn, vha, 0xd006,
				955	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	956	goto qla24xx_fw_dump_failed;
				957	}
				958
				959	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	960	ql_log(ql_log_warn, vha, 0xd007,
				961	"Firmware has been previously dumped (%p) "
				962	"-- ignoring request.\n",
				963	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	964	goto qla24xx_fw_dump_failed;
				965	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	966	fw = &ha->fw_dump->isp.isp24;
				967	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	968
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	969	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	970
				971	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	972	rval = qla24xx_pause_risc(reg);
				973	if (rval != QLA_SUCCESS)
				974	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	975
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	976	/* Host interface registers. */
				977	dmp_reg = &reg->flash_addr;
				978	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				979	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	980
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	981	/* Disable interrupts. */
				982	WRT_REG_DWORD(&reg->ictrl, 0);
				983	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	984
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	985	/* Shadow registers. */
				986	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				987	RD_REG_DWORD(&reg->iobase_addr);
				988	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				989	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	990
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	991	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				992	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	993
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	994	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				995	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	996
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	997	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				998	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	999
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1000	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1001	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1002
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1003	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1004	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1005
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1006	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1007	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1008
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1009	/* Mailbox registers. */
				1010	mbx_reg = &reg->mailbox0;
				1011	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1012	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1013
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1014	/* Transfer sequence registers. */
				1015	iter_reg = fw->xseq_gp_reg;
				1016	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1017	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1018	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1019	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1020	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1021	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1022	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1023	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1024
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1025	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1026	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1027
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1028	/* Receive sequence registers. */
				1029	iter_reg = fw->rseq_gp_reg;
				1030	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1031	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1032	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1033	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1034	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1035	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1036	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1037	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1038
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1039	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1040	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1041	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1042
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1043	/* Command DMA registers. */
				1044	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1045
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1046	/* Queues. */
				1047	iter_reg = fw->req0_dma_reg;
				1048	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1049	dmp_reg = &reg->iobase_q;
				1050	for (cnt = 0; cnt < 7; cnt++)
				1051	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1052
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1053	iter_reg = fw->resp0_dma_reg;
				1054	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1055	dmp_reg = &reg->iobase_q;
				1056	for (cnt = 0; cnt < 7; cnt++)
				1057	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1058
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1059	iter_reg = fw->req1_dma_reg;
				1060	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1061	dmp_reg = &reg->iobase_q;
				1062	for (cnt = 0; cnt < 7; cnt++)
				1063	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1064
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1065	/* Transmit DMA registers. */
				1066	iter_reg = fw->xmt0_dma_reg;
				1067	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1068	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1069
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1070	iter_reg = fw->xmt1_dma_reg;
				1071	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1072	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1073
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1074	iter_reg = fw->xmt2_dma_reg;
				1075	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1076	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1077
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1078	iter_reg = fw->xmt3_dma_reg;
				1079	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1080	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1081
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1082	iter_reg = fw->xmt4_dma_reg;
				1083	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1084	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1085
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1086	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1087
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1088	/* Receive DMA registers. */
				1089	iter_reg = fw->rcvt0_data_dma_reg;
				1090	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1091	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1092
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1093	iter_reg = fw->rcvt1_data_dma_reg;
				1094	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1095	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1096
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1097	/* RISC registers. */
				1098	iter_reg = fw->risc_gp_reg;
				1099	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1100	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1101	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1102	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1103	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1104	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1105	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1106	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1107
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1108	/* Local memory controller registers. */
				1109	iter_reg = fw->lmc_reg;
				1110	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1111	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1112	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1113	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1114	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1115	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1116	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1117
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1118	/* Fibre Protocol Module registers. */
				1119	iter_reg = fw->fpm_hdw_reg;
				1120	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1121	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1122	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1123	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1124	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1125	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1126	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1127	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1128	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1129	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1130	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1131	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1132
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1133	/* Frame Buffer registers. */
				1134	iter_reg = fw->fb_hdw_reg;
				1135	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1136	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1137	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1138	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1139	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1140	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1141	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1142	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1144	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1145	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1146
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1147	rval = qla24xx_soft_reset(ha);
				1148	if (rval != QLA_SUCCESS)
				1149	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1150
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1151	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1152	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1153	if (rval != QLA_SUCCESS)
				1154	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1155
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1156	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1157
				1158	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1159
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1160	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1161	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1162	if (last_chain) {
				1163	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1164	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1165	}
				1166
				1167	/* Adjust valid length. */
				1168	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1169
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1170	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1171	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1172
				1173	qla24xx_fw_dump_failed:
				1174	if (!hardware_locked)
				1175	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1176	}
				1177
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1178	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1179	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1180	{
				1181	int rval;
				1182	uint32_t cnt;
				1183	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1184	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1185	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1186	uint32_t __iomem *dmp_reg;
				1187	uint32_t *iter_reg;
				1188	uint16_t __iomem *mbx_reg;
				1189	unsigned long flags;
				1190	struct qla25xx_fw_dump *fw;
				1191	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1192	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1193	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1194	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1195
				1196	risc_address = ext_mem_cnt = 0;
				1197	flags = 0;
				1198
				1199	if (!hardware_locked)
				1200	spin_lock_irqsave(&ha->hardware_lock, flags);
				1201
				1202	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1203	ql_log(ql_log_warn, vha, 0xd008,
				1204	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1205	goto qla25xx_fw_dump_failed;
				1206	}
				1207
				1208	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1209	ql_log(ql_log_warn, vha, 0xd009,
				1210	"Firmware has been previously dumped (%p) "
				1211	"-- ignoring request.\n",
				1212	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1213	goto qla25xx_fw_dump_failed;
				1214	}
				1215	fw = &ha->fw_dump->isp.isp25;
				1216	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1217	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1218
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1219	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1220
				1221	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1222	rval = qla24xx_pause_risc(reg);
				1223	if (rval != QLA_SUCCESS)
				1224	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1225
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1226	/* Host/Risc registers. */
				1227	iter_reg = fw->host_risc_reg;
				1228	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1229	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1230
				1231	/* PCIe registers. */
				1232	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1233	RD_REG_DWORD(&reg->iobase_addr);
				1234	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1235	dmp_reg = &reg->iobase_c4;
				1236	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1237	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1238	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1239	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1240
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1241	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1242	RD_REG_DWORD(&reg->iobase_window);
				1243
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1244	/* Host interface registers. */
				1245	dmp_reg = &reg->flash_addr;
				1246	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1247	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1248
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1249	/* Disable interrupts. */
				1250	WRT_REG_DWORD(&reg->ictrl, 0);
				1251	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1252
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1253	/* Shadow registers. */
				1254	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1255	RD_REG_DWORD(&reg->iobase_addr);
				1256	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1257	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1258
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1259	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1260	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1261
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1262	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1263	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1264
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1265	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1266	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1267
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1268	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1269	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1270
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1271	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1272	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1273
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1274	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1275	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1276
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1277	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1278	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1279
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1280	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1281	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1282
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1283	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1284	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1285
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1286	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1287	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1288
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1289	/* RISC I/O register. */
				1290	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1291	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1292
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1293	/* Mailbox registers. */
				1294	mbx_reg = &reg->mailbox0;
				1295	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1296	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1297
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1298	/* Transfer sequence registers. */
				1299	iter_reg = fw->xseq_gp_reg;
				1300	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1301	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1302	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1303	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1304	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1305	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1306	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1307	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1308
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1309	iter_reg = fw->xseq_0_reg;
				1310	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1311	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1312	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1313
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1314	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1315
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1316	/* Receive sequence registers. */
				1317	iter_reg = fw->rseq_gp_reg;
				1318	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1319	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1320	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1321	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1322	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1323	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1324	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1325	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1326
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1327	iter_reg = fw->rseq_0_reg;
				1328	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1329	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1330
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1331	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1332	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1333
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1334	/* Auxiliary sequence registers. */
				1335	iter_reg = fw->aseq_gp_reg;
				1336	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1337	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1338	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1339	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1340	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1341	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1342	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1343	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1344
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1345	iter_reg = fw->aseq_0_reg;
				1346	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1347	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1348
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1349	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1350	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1351
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1352	/* Command DMA registers. */
				1353	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1354
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1355	/* Queues. */
				1356	iter_reg = fw->req0_dma_reg;
				1357	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1358	dmp_reg = &reg->iobase_q;
				1359	for (cnt = 0; cnt < 7; cnt++)
				1360	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1361
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1362	iter_reg = fw->resp0_dma_reg;
				1363	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1364	dmp_reg = &reg->iobase_q;
				1365	for (cnt = 0; cnt < 7; cnt++)
				1366	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1367
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1368	iter_reg = fw->req1_dma_reg;
				1369	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1370	dmp_reg = &reg->iobase_q;
				1371	for (cnt = 0; cnt < 7; cnt++)
				1372	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1373
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1374	/* Transmit DMA registers. */
				1375	iter_reg = fw->xmt0_dma_reg;
				1376	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1377	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1378
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1379	iter_reg = fw->xmt1_dma_reg;
				1380	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1381	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1382
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1383	iter_reg = fw->xmt2_dma_reg;
				1384	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1385	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1386
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1387	iter_reg = fw->xmt3_dma_reg;
				1388	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1389	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1390
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1391	iter_reg = fw->xmt4_dma_reg;
				1392	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1393	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1394
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1395	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	/* Receive DMA registers. */
				1398	iter_reg = fw->rcvt0_data_dma_reg;
				1399	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1400	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1401
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1402	iter_reg = fw->rcvt1_data_dma_reg;
				1403	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1404	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1405
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1406	/* RISC registers. */
				1407	iter_reg = fw->risc_gp_reg;
				1408	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1409	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1410	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1411	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1412	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1413	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1414	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1415	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1416
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1417	/* Local memory controller registers. */
				1418	iter_reg = fw->lmc_reg;
				1419	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1421	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1422	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1423	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1424	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1425	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1426	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1427
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1428	/* Fibre Protocol Module registers. */
				1429	iter_reg = fw->fpm_hdw_reg;
				1430	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1431	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1432	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1439	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1440	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1441	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1442
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1443	/* Frame Buffer registers. */
				1444	iter_reg = fw->fb_hdw_reg;
				1445	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1446	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1447	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1448	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1449	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1450	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1451	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1455	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1456	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1457
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1458	/* Multi queue registers */
				1459	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1460	&last_chain);
				1461
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1462	rval = qla24xx_soft_reset(ha);
				1463	if (rval != QLA_SUCCESS)
				1464	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1465
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1466	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1467	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1468	if (rval != QLA_SUCCESS)
				1469	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1470
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1471	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1472
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame^]	1473	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1474
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1475	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1476	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1477	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1478	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1479	if (last_chain) {
				1480	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1481	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1482	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1483
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1484	/* Adjust valid length. */
				1485	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1486
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1487	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1488	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1489
				1490	qla25xx_fw_dump_failed:
				1491	if (!hardware_locked)
				1492	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1493	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1494
				1495	void
				1496	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1497	{
				1498	int rval;
				1499	uint32_t cnt;
				1500	uint32_t risc_address;
				1501	struct qla_hw_data *ha = vha->hw;
				1502	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1503	uint32_t __iomem *dmp_reg;
				1504	uint32_t *iter_reg;
				1505	uint16_t __iomem *mbx_reg;
				1506	unsigned long flags;
				1507	struct qla81xx_fw_dump *fw;
				1508	uint32_t ext_mem_cnt;
				1509	void nxt, nxt_chain;
				1510	uint32_t *last_chain = NULL;
				1511	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1512
				1513	risc_address = ext_mem_cnt = 0;
				1514	flags = 0;
				1515
				1516	if (!hardware_locked)
				1517	spin_lock_irqsave(&ha->hardware_lock, flags);
				1518
				1519	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1520	ql_log(ql_log_warn, vha, 0xd00a,
				1521	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1522	goto qla81xx_fw_dump_failed;
				1523	}
				1524
				1525	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1526	ql_log(ql_log_warn, vha, 0xd00b,
				1527	"Firmware has been previously dumped (%p) "
				1528	"-- ignoring request.\n",
				1529	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1530	goto qla81xx_fw_dump_failed;
				1531	}
				1532	fw = &ha->fw_dump->isp.isp81;
				1533	qla2xxx_prep_dump(ha, ha->fw_dump);
				1534
				1535	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1536
				1537	/* Pause RISC. */
				1538	rval = qla24xx_pause_risc(reg);
				1539	if (rval != QLA_SUCCESS)
				1540	goto qla81xx_fw_dump_failed_0;
				1541
				1542	/* Host/Risc registers. */
				1543	iter_reg = fw->host_risc_reg;
				1544	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1545	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1546
				1547	/* PCIe registers. */
				1548	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1549	RD_REG_DWORD(&reg->iobase_addr);
				1550	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1551	dmp_reg = &reg->iobase_c4;
				1552	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1553	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1554	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1555	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1556
				1557	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1558	RD_REG_DWORD(&reg->iobase_window);
				1559
				1560	/* Host interface registers. */
				1561	dmp_reg = &reg->flash_addr;
				1562	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1563	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1564
				1565	/* Disable interrupts. */
				1566	WRT_REG_DWORD(&reg->ictrl, 0);
				1567	RD_REG_DWORD(&reg->ictrl);
				1568
				1569	/* Shadow registers. */
				1570	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1571	RD_REG_DWORD(&reg->iobase_addr);
				1572	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1573	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1574
				1575	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1576	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1577
				1578	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1579	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1580
				1581	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1582	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1583
				1584	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1585	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1586
				1587	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1588	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1589
				1590	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1591	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1592
				1593	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1594	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1595
				1596	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1597	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1598
				1599	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1600	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1601
				1602	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1603	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1604
				1605	/* RISC I/O register. */
				1606	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1607	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1608
				1609	/* Mailbox registers. */
				1610	mbx_reg = &reg->mailbox0;
				1611	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1612	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1613
				1614	/* Transfer sequence registers. */
				1615	iter_reg = fw->xseq_gp_reg;
				1616	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1617	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1618	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1619	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1620	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1621	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1622	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1623	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1624
				1625	iter_reg = fw->xseq_0_reg;
				1626	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1627	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1628	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1629
				1630	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1631
				1632	/* Receive sequence registers. */
				1633	iter_reg = fw->rseq_gp_reg;
				1634	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1635	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1636	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1637	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1638	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1639	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1640	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1641	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1642
				1643	iter_reg = fw->rseq_0_reg;
				1644	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1645	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1646
				1647	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1648	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1649
				1650	/* Auxiliary sequence registers. */
				1651	iter_reg = fw->aseq_gp_reg;
				1652	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1653	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1654	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1655	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1656	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1657	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1658	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1659	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1660
				1661	iter_reg = fw->aseq_0_reg;
				1662	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1663	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1664
				1665	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1666	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1667
				1668	/* Command DMA registers. */
				1669	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1670
				1671	/* Queues. */
				1672	iter_reg = fw->req0_dma_reg;
				1673	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1674	dmp_reg = &reg->iobase_q;
				1675	for (cnt = 0; cnt < 7; cnt++)
				1676	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1677
				1678	iter_reg = fw->resp0_dma_reg;
				1679	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1680	dmp_reg = &reg->iobase_q;
				1681	for (cnt = 0; cnt < 7; cnt++)
				1682	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1683
				1684	iter_reg = fw->req1_dma_reg;
				1685	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1686	dmp_reg = &reg->iobase_q;
				1687	for (cnt = 0; cnt < 7; cnt++)
				1688	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1689
				1690	/* Transmit DMA registers. */
				1691	iter_reg = fw->xmt0_dma_reg;
				1692	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1693	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1694
				1695	iter_reg = fw->xmt1_dma_reg;
				1696	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1697	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1698
				1699	iter_reg = fw->xmt2_dma_reg;
				1700	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1701	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1702
				1703	iter_reg = fw->xmt3_dma_reg;
				1704	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1705	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1706
				1707	iter_reg = fw->xmt4_dma_reg;
				1708	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1709	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1710
				1711	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1712
				1713	/* Receive DMA registers. */
				1714	iter_reg = fw->rcvt0_data_dma_reg;
				1715	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1716	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1717
				1718	iter_reg = fw->rcvt1_data_dma_reg;
				1719	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1720	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1721
				1722	/* RISC registers. */
				1723	iter_reg = fw->risc_gp_reg;
				1724	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1725	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1726	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1727	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1728	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1729	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1730	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1731	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1732
				1733	/* Local memory controller registers. */
				1734	iter_reg = fw->lmc_reg;
				1735	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1737	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1738	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1739	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1740	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1741	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1742	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1743
				1744	/* Fibre Protocol Module registers. */
				1745	iter_reg = fw->fpm_hdw_reg;
				1746	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1747	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1748	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1749	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1750	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1757	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1758	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1759	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1760
				1761	/* Frame Buffer registers. */
				1762	iter_reg = fw->fb_hdw_reg;
				1763	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1764	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1765	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1767	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1768	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1772	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1773	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1774	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1775	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1776
				1777	/* Multi queue registers */
				1778	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1779	&last_chain);
				1780
				1781	rval = qla24xx_soft_reset(ha);
				1782	if (rval != QLA_SUCCESS)
				1783	goto qla81xx_fw_dump_failed_0;
				1784
				1785	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1786	&nxt);
				1787	if (rval != QLA_SUCCESS)
				1788	goto qla81xx_fw_dump_failed_0;
				1789
				1790	nxt = qla2xxx_copy_queues(ha, nxt);
				1791
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame^]	1792	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1793
				1794	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1795	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1796	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1797	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1798	if (last_chain) {
				1799	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1800	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1801	}
				1802
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1803	/* Adjust valid length. */
				1804	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1805
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1806	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1807	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1808
				1809	qla81xx_fw_dump_failed:
				1810	if (!hardware_locked)
				1811	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1812	}
				1813
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1814	void
				1815	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1816	{
				1817	int rval;
				1818	uint32_t cnt, reg_data;
				1819	uint32_t risc_address;
				1820	struct qla_hw_data *ha = vha->hw;
				1821	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1822	uint32_t __iomem *dmp_reg;
				1823	uint32_t *iter_reg;
				1824	uint16_t __iomem *mbx_reg;
				1825	unsigned long flags;
				1826	struct qla83xx_fw_dump *fw;
				1827	uint32_t ext_mem_cnt;
				1828	void nxt, nxt_chain;
				1829	uint32_t *last_chain = NULL;
				1830	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1831
				1832	risc_address = ext_mem_cnt = 0;
				1833	flags = 0;
				1834
				1835	if (!hardware_locked)
				1836	spin_lock_irqsave(&ha->hardware_lock, flags);
				1837
				1838	if (!ha->fw_dump) {
				1839	ql_log(ql_log_warn, vha, 0xd00c,
				1840	"No buffer available for dump!!!\n");
				1841	goto qla83xx_fw_dump_failed;
				1842	}
				1843
				1844	if (ha->fw_dumped) {
				1845	ql_log(ql_log_warn, vha, 0xd00d,
				1846	"Firmware has been previously dumped (%p) -- ignoring "
				1847	"request...\n", ha->fw_dump);
				1848	goto qla83xx_fw_dump_failed;
				1849	}
				1850	fw = &ha->fw_dump->isp.isp83;
				1851	qla2xxx_prep_dump(ha, ha->fw_dump);
				1852
				1853	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1854
				1855	/* Pause RISC. */
				1856	rval = qla24xx_pause_risc(reg);
				1857	if (rval != QLA_SUCCESS)
				1858	goto qla83xx_fw_dump_failed_0;
				1859
				1860	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1861	dmp_reg = &reg->iobase_window;
				1862	reg_data = RD_REG_DWORD(dmp_reg);
				1863	WRT_REG_DWORD(dmp_reg, 0);
				1864
				1865	dmp_reg = &reg->unused_4_1[0];
				1866	reg_data = RD_REG_DWORD(dmp_reg);
				1867	WRT_REG_DWORD(dmp_reg, 0);
				1868
				1869	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1870	dmp_reg = &reg->unused_4_1[2];
				1871	reg_data = RD_REG_DWORD(dmp_reg);
				1872	WRT_REG_DWORD(dmp_reg, 0);
				1873
				1874	/* select PCR and disable ecc checking and correction */
				1875	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1876	RD_REG_DWORD(&reg->iobase_addr);
				1877	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1878
				1879	/* Host/Risc registers. */
				1880	iter_reg = fw->host_risc_reg;
				1881	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1882	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1883	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				1884
				1885	/* PCIe registers. */
				1886	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1887	RD_REG_DWORD(&reg->iobase_addr);
				1888	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1889	dmp_reg = &reg->iobase_c4;
				1890	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1891	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1892	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1893	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1894
				1895	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1896	RD_REG_DWORD(&reg->iobase_window);
				1897
				1898	/* Host interface registers. */
				1899	dmp_reg = &reg->flash_addr;
				1900	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1901	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1902
				1903	/* Disable interrupts. */
				1904	WRT_REG_DWORD(&reg->ictrl, 0);
				1905	RD_REG_DWORD(&reg->ictrl);
				1906
				1907	/* Shadow registers. */
				1908	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1909	RD_REG_DWORD(&reg->iobase_addr);
				1910	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1911	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1912
				1913	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1914	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1915
				1916	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1917	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1918
				1919	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1920	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1921
				1922	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1923	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1924
				1925	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1926	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1927
				1928	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1929	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1930
				1931	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1932	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1933
				1934	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1935	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1936
				1937	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1938	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1939
				1940	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1941	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1942
				1943	/* RISC I/O register. */
				1944	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1945	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1946
				1947	/* Mailbox registers. */
				1948	mbx_reg = &reg->mailbox0;
				1949	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1950	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1951
				1952	/* Transfer sequence registers. */
				1953	iter_reg = fw->xseq_gp_reg;
				1954	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				1955	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				1956	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				1957	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				1958	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				1959	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				1960	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				1961	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				1962	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1963	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1964	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1965	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1966	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1967	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1968	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1969	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1970
				1971	iter_reg = fw->xseq_0_reg;
				1972	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1973	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1974	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1975
				1976	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1977
				1978	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				1979
				1980	/* Receive sequence registers. */
				1981	iter_reg = fw->rseq_gp_reg;
				1982	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				1983	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				1984	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				1985	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				1986	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				1987	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				1988	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				1989	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				1990	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1991	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1992	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1993	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1994	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1995	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1996	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1997	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1998
				1999	iter_reg = fw->rseq_0_reg;
				2000	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2001	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2002
				2003	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2004	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2005	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2006
				2007	/* Auxiliary sequence registers. */
				2008	iter_reg = fw->aseq_gp_reg;
				2009	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2010	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2011	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2012	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2013	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2014	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2015	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2016	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2017	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2018	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2019	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2020	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2021	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2022	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2023	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2024	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2025
				2026	iter_reg = fw->aseq_0_reg;
				2027	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2028	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2029
				2030	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2031	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2032	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2033
				2034	/* Command DMA registers. */
				2035	iter_reg = fw->cmd_dma_reg;
				2036	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2037	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2038	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2039	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2040
				2041	/* Queues. */
				2042	iter_reg = fw->req0_dma_reg;
				2043	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2044	dmp_reg = &reg->iobase_q;
				2045	for (cnt = 0; cnt < 7; cnt++)
				2046	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2047
				2048	iter_reg = fw->resp0_dma_reg;
				2049	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2050	dmp_reg = &reg->iobase_q;
				2051	for (cnt = 0; cnt < 7; cnt++)
				2052	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2053
				2054	iter_reg = fw->req1_dma_reg;
				2055	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2056	dmp_reg = &reg->iobase_q;
				2057	for (cnt = 0; cnt < 7; cnt++)
				2058	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2059
				2060	/* Transmit DMA registers. */
				2061	iter_reg = fw->xmt0_dma_reg;
				2062	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2063	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2064
				2065	iter_reg = fw->xmt1_dma_reg;
				2066	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2067	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2068
				2069	iter_reg = fw->xmt2_dma_reg;
				2070	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2071	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2072
				2073	iter_reg = fw->xmt3_dma_reg;
				2074	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2075	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2076
				2077	iter_reg = fw->xmt4_dma_reg;
				2078	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2079	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2080
				2081	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2082
				2083	/* Receive DMA registers. */
				2084	iter_reg = fw->rcvt0_data_dma_reg;
				2085	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2086	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2087
				2088	iter_reg = fw->rcvt1_data_dma_reg;
				2089	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2090	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2091
				2092	/* RISC registers. */
				2093	iter_reg = fw->risc_gp_reg;
				2094	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2095	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2096	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2097	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2098	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2099	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2100	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2101	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2102
				2103	/* Local memory controller registers. */
				2104	iter_reg = fw->lmc_reg;
				2105	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2107	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2111	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2112	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2113
				2114	/* Fibre Protocol Module registers. */
				2115	iter_reg = fw->fpm_hdw_reg;
				2116	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2117	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2118	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2120	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2121	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2122	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2123	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2124	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2125	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2126	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2127	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2128	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2130	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2131	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2132
				2133	/* RQ0 Array registers. */
				2134	iter_reg = fw->rq0_array_reg;
				2135	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2143	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2144	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2145	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2146	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2147	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2148	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2149	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2150	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2151
				2152	/* RQ1 Array registers. */
				2153	iter_reg = fw->rq1_array_reg;
				2154	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2160	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2161	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2162	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2163	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2164	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2165	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2166	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2167	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2168	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2169	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2170
				2171	/* RP0 Array registers. */
				2172	iter_reg = fw->rp0_array_reg;
				2173	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2174	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2175	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2176	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2177	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2178	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2179	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2180	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2181	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2182	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2183	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2184	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2185	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2186	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2187	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2188	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2189
				2190	/* RP1 Array registers. */
				2191	iter_reg = fw->rp1_array_reg;
				2192	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2193	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2194	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2195	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2196	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2197	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2198	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2199	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2200	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2201	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2202	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2203	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2204	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2205	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2206	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2207	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2208
				2209	iter_reg = fw->at0_array_reg;
				2210	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2211	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2212	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2213	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2214	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2216	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2217	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2218
				2219	/* I/O Queue Control registers. */
				2220	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2221
				2222	/* Frame Buffer registers. */
				2223	iter_reg = fw->fb_hdw_reg;
				2224	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2230	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2231	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2232	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2233	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2248	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2249	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2250	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2251
				2252	/* Multi queue registers */
				2253	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2254	&last_chain);
				2255
				2256	rval = qla24xx_soft_reset(ha);
				2257	if (rval != QLA_SUCCESS) {
				2258	ql_log(ql_log_warn, vha, 0xd00e,
				2259	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2260	rval = QLA_SUCCESS;
				2261
				2262	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2263
				2264	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2265	RD_REG_DWORD(&reg->hccr);
				2266
				2267	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2268	RD_REG_DWORD(&reg->hccr);
				2269
				2270	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2271	RD_REG_DWORD(&reg->hccr);
				2272
				2273	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2274	udelay(5);
				2275
				2276	if (!cnt) {
				2277	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2278	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2279	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2280	goto copy_queue;
				2281	} else
				2282	ql_log(ql_log_warn, vha, 0xd010,
				2283	"bigger hammer success?\n");
				2284	}
				2285
				2286	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2287	&nxt);
				2288	if (rval != QLA_SUCCESS)
				2289	goto qla83xx_fw_dump_failed_0;
				2290
				2291	copy_queue:
				2292	nxt = qla2xxx_copy_queues(ha, nxt);
				2293
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame^]	2294	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2295
				2296	/* Chain entries -- started with MQ. */
				2297	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2298	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2299	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2300	if (last_chain) {
				2301	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2302	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2303	}
				2304
				2305	/* Adjust valid length. */
				2306	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2307
				2308	qla83xx_fw_dump_failed_0:
				2309	qla2xxx_dump_post_process(base_vha, rval);
				2310
				2311	qla83xx_fw_dump_failed:
				2312	if (!hardware_locked)
				2313	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2314	}
				2315
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2316	/****************************************************************************/
				2317	/* Driver Debug Functions. */
				2318	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2319
				2320	static inline int
				2321	ql_mask_match(uint32_t level)
				2322	{
				2323	if (ql2xextended_error_logging == 1)
				2324	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2325	return (level & ql2xextended_error_logging) == level;
				2326	}
				2327
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2328	/*
				2329	* This function is for formatting and logging debug information.
				2330	* It is to be used when vha is available. It formats the message
				2331	* and logs it to the messages file.
				2332	* parameters:
				2333	* level: The level of the debug messages to be printed.
				2334	* If ql2xextended_error_logging value is correctly set,
				2335	* this message will appear in the messages file.
				2336	* vha: Pointer to the scsi_qla_host_t.
				2337	* id: This is a unique identifier for the level. It identifies the
				2338	* part of the code from where the message originated.
				2339	* msg: The message to be displayed.
				2340	*/
				2341	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2342	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2343	{
				2344	va_list va;
				2345	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2346
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2347	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2348	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2349
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2350	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2351
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2352	vaf.fmt = fmt;
				2353	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2354
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2355	if (vha != NULL) {
				2356	const struct pci_dev *pdev = vha->hw->pdev;
				2357	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2358	pr_warn("%s [%s]-%04x:%ld: %pV",
				2359	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2360	vha->host_no, &vaf);
				2361	} else {
				2362	pr_warn("%s [%s]-%04x: : %pV",
				2363	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2364	}
				2365
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2366	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2367
				2368	}
				2369
				2370	/*
				2371	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2372	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2373	* i.e., before host allocation. It formats the message and logs it
				2374	* to the messages file.
				2375	* parameters:
				2376	* level: The level of the debug messages to be printed.
				2377	* If ql2xextended_error_logging value is correctly set,
				2378	* this message will appear in the messages file.
				2379	* pdev: Pointer to the struct pci_dev.
				2380	* id: This is a unique id for the level. It identifies the part
				2381	* of the code from where the message originated.
				2382	* msg: The message to be displayed.
				2383	*/
				2384	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2385	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2386	const char *fmt, ...)
				2387	{
				2388	va_list va;
				2389	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2390
				2391	if (pdev == NULL)
				2392	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2393	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2394	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2395
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2396	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2397
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2398	vaf.fmt = fmt;
				2399	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2400
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2401	/* <module-name> <dev-name>:<msg-id> Message */
				2402	pr_warn("%s [%s]-%04x: : %pV",
				2403	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2404
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2405	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2406	}
				2407
				2408	/*
				2409	* This function is for formatting and logging log messages.
				2410	* It is to be used when vha is available. It formats the message
				2411	* and logs it to the messages file. All the messages will be logged
				2412	* irrespective of value of ql2xextended_error_logging.
				2413	* parameters:
				2414	* level: The level of the log messages to be printed in the
				2415	* messages file.
				2416	* vha: Pointer to the scsi_qla_host_t
				2417	* id: This is a unique id for the level. It identifies the
				2418	* part of the code from where the message originated.
				2419	* msg: The message to be displayed.
				2420	*/
				2421	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2422	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2423	{
				2424	va_list va;
				2425	struct va_format vaf;
				2426	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2427
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2428	if (level > ql_errlev)
				2429	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2430
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2431	if (vha != NULL) {
				2432	const struct pci_dev *pdev = vha->hw->pdev;
				2433	/* <module-name> <msg-id>:<host> Message */
				2434	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2435	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2436	} else {
				2437	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2438	QL_MSGHDR, "0000:00:00.0", id);
				2439	}
				2440	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2441
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2442	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2443
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2444	vaf.fmt = fmt;
				2445	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2446
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2447	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2448	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2449	pr_crit("%s%pV", pbuf, &vaf);
				2450	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2451	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2452	pr_err("%s%pV", pbuf, &vaf);
				2453	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2454	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2455	pr_warn("%s%pV", pbuf, &vaf);
				2456	break;
				2457	default:
				2458	pr_info("%s%pV", pbuf, &vaf);
				2459	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2460	}
				2461
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2462	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2463	}
				2464
				2465	/*
				2466	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2467	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2468	* i.e., before host allocation. It formats the message and logs
				2469	* it to the messages file. All the messages are logged irrespective
				2470	* of the value of ql2xextended_error_logging.
				2471	* parameters:
				2472	* level: The level of the log messages to be printed in the
				2473	* messages file.
				2474	* pdev: Pointer to the struct pci_dev.
				2475	* id: This is a unique id for the level. It identifies the
				2476	* part of the code from where the message originated.
				2477	* msg: The message to be displayed.
				2478	*/
				2479	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2480	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2481	const char *fmt, ...)
				2482	{
				2483	va_list va;
				2484	struct va_format vaf;
				2485	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2486
				2487	if (pdev == NULL)
				2488	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2489	if (level > ql_errlev)
				2490	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2491
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2492	/* <module-name> <dev-name>:<msg-id> Message */
				2493	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2494	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2495	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2496
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2497	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2498
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2499	vaf.fmt = fmt;
				2500	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2501
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2502	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2503	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2504	pr_crit("%s%pV", pbuf, &vaf);
				2505	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2506	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2507	pr_err("%s%pV", pbuf, &vaf);
				2508	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2509	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2510	pr_warn("%s%pV", pbuf, &vaf);
				2511	break;
				2512	default:
				2513	pr_info("%s%pV", pbuf, &vaf);
				2514	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2515	}
				2516
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2517	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2518	}
				2519
				2520	void
				2521	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2522	{
				2523	int i;
				2524	struct qla_hw_data *ha = vha->hw;
				2525	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2526	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2527	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2528	uint16_t __iomem *mbx_reg;
				2529
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2530	if (!ql_mask_match(level))
				2531	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2532
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2533	if (IS_QLA82XX(ha))
				2534	mbx_reg = &reg82->mailbox_in[0];
				2535	else if (IS_FWI2_CAPABLE(ha))
				2536	mbx_reg = &reg24->mailbox0;
				2537	else
				2538	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2539
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2540	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2541	for (i = 0; i < 6; i++)
				2542	ql_dbg(level, vha, id,
				2543	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2544	}
				2545
				2546
				2547	void
				2548	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2549	uint8_t *b, uint32_t size)
				2550	{
				2551	uint32_t cnt;
				2552	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2553
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2554	if (!ql_mask_match(level))
				2555	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2556
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2557	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2558	"9 Ah Bh Ch Dh Eh Fh\n");
				2559	ql_dbg(level, vha, id, "----------------------------------"
				2560	"----------------------------\n");
				2561
				2562	ql_dbg(level, vha, id, " ");
				2563	for (cnt = 0; cnt < size;) {
				2564	c = *b++;
				2565	printk("%02x", (uint32_t) c);
				2566	cnt++;
				2567	if (!(cnt % 16))
				2568	printk("\n");
				2569	else
				2570	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2571	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2572	if (cnt % 16)
				2573	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2574	}