Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
| 4 | * Permission to use, copy, modify, distribute, and sell this software and its |
| 5 | * documentation for any purpose is hereby granted without fee, provided that |
| 6 | * the above copyright notice appear in all copies and that both that copyright |
| 7 | * notice and this permission notice appear in supporting documentation, and |
| 8 | * that the name of the copyright holders not be used in advertising or |
| 9 | * publicity pertaining to distribution of the software without specific, |
| 10 | * written prior permission. The copyright holders make no representations |
| 11 | * about the suitability of this software for any purpose. It is provided "as |
| 12 | * is" without express or implied warranty. |
| 13 | * |
| 14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
| 15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
| 16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
| 17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
| 18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
| 20 | * OF THIS SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/delay.h> |
Thierry Reding | aef03d3 | 2013-11-08 13:28:34 +0100 | [diff] [blame] | 25 | #include <linux/host1x.h> |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 26 | #include <linux/io.h> |
| 27 | #include <linux/of_platform.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/slab.h> |
| 30 | |
Thierry Reding | aef03d3 | 2013-11-08 13:28:34 +0100 | [diff] [blame] | 31 | #include "dev.h" |
| 32 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 33 | #define MIPI_CAL_CTRL 0x00 |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 34 | #define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26) |
| 35 | #define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24) |
| 36 | #define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4) |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 37 | #define MIPI_CAL_CTRL_START (1 << 0) |
| 38 | |
| 39 | #define MIPI_CAL_AUTOCAL_CTRL 0x01 |
| 40 | |
| 41 | #define MIPI_CAL_STATUS 0x02 |
| 42 | #define MIPI_CAL_STATUS_DONE (1 << 16) |
| 43 | #define MIPI_CAL_STATUS_ACTIVE (1 << 0) |
| 44 | |
| 45 | #define MIPI_CAL_CONFIG_CSIA 0x05 |
| 46 | #define MIPI_CAL_CONFIG_CSIB 0x06 |
| 47 | #define MIPI_CAL_CONFIG_CSIC 0x07 |
| 48 | #define MIPI_CAL_CONFIG_CSID 0x08 |
| 49 | #define MIPI_CAL_CONFIG_CSIE 0x09 |
| 50 | #define MIPI_CAL_CONFIG_DSIA 0x0e |
| 51 | #define MIPI_CAL_CONFIG_DSIB 0x0f |
| 52 | #define MIPI_CAL_CONFIG_DSIC 0x10 |
| 53 | #define MIPI_CAL_CONFIG_DSID 0x11 |
| 54 | |
Thierry Reding | 8ed5c06 | 2015-04-08 17:06:08 +0200 | [diff] [blame] | 55 | #define MIPI_CAL_CONFIG_DSIA_CLK 0x19 |
| 56 | #define MIPI_CAL_CONFIG_DSIB_CLK 0x1a |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 57 | #define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b |
| 58 | #define MIPI_CAL_CONFIG_CSICD_CLK 0x1c |
| 59 | #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d |
| 60 | |
| 61 | /* for data and clock lanes */ |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 62 | #define MIPI_CAL_CONFIG_SELECT (1 << 21) |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 63 | |
| 64 | /* for data lanes */ |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 65 | #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16) |
| 66 | #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8) |
| 67 | #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0) |
| 68 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 69 | /* for clock lanes */ |
| 70 | #define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8) |
| 71 | #define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0) |
| 72 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 73 | #define MIPI_CAL_BIAS_PAD_CFG0 0x16 |
| 74 | #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1) |
| 75 | #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) |
| 76 | |
| 77 | #define MIPI_CAL_BIAS_PAD_CFG1 0x17 |
Sean Paul | b298e98 | 2014-09-10 10:52:05 -0400 | [diff] [blame] | 78 | #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 79 | #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8) |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 80 | |
| 81 | #define MIPI_CAL_BIAS_PAD_CFG2 0x18 |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 82 | #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16) |
| 83 | #define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4) |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 84 | #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) |
| 85 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 86 | struct tegra_mipi_pad { |
| 87 | unsigned long data; |
| 88 | unsigned long clk; |
| 89 | }; |
| 90 | |
| 91 | struct tegra_mipi_soc { |
| 92 | bool has_clk_lane; |
| 93 | const struct tegra_mipi_pad *pads; |
| 94 | unsigned int num_pads; |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 95 | |
| 96 | bool clock_enable_override; |
| 97 | bool needs_vclamp_ref; |
| 98 | |
| 99 | /* bias pad configuration settings */ |
| 100 | u8 pad_drive_down_ref; |
| 101 | u8 pad_drive_up_ref; |
| 102 | |
| 103 | u8 pad_vclamp_level; |
| 104 | u8 pad_vauxp_level; |
| 105 | |
| 106 | /* calibration settings for data lanes */ |
| 107 | u8 hspdos; |
| 108 | u8 hspuos; |
| 109 | u8 termos; |
| 110 | |
| 111 | /* calibration settings for clock lanes */ |
| 112 | u8 hsclkpdos; |
| 113 | u8 hsclkpuos; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | struct tegra_mipi { |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 117 | const struct tegra_mipi_soc *soc; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 118 | void __iomem *regs; |
| 119 | struct mutex lock; |
| 120 | struct clk *clk; |
| 121 | }; |
| 122 | |
| 123 | struct tegra_mipi_device { |
| 124 | struct platform_device *pdev; |
| 125 | struct tegra_mipi *mipi; |
| 126 | struct device *device; |
| 127 | unsigned long pads; |
| 128 | }; |
| 129 | |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 130 | static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, |
| 131 | unsigned long offset) |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 132 | { |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 133 | return readl(mipi->regs + (offset << 2)); |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 134 | } |
| 135 | |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 136 | static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, |
| 137 | unsigned long offset) |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 138 | { |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 139 | writel(value, mipi->regs + (offset << 2)); |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | struct tegra_mipi_device *tegra_mipi_request(struct device *device) |
| 143 | { |
| 144 | struct device_node *np = device->of_node; |
| 145 | struct tegra_mipi_device *dev; |
| 146 | struct of_phandle_args args; |
| 147 | int err; |
| 148 | |
| 149 | err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate", |
| 150 | "#nvidia,mipi-calibrate-cells", 0, |
| 151 | &args); |
| 152 | if (err < 0) |
| 153 | return ERR_PTR(err); |
| 154 | |
| 155 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
| 156 | if (!dev) { |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 157 | err = -ENOMEM; |
| 158 | goto out; |
| 159 | } |
| 160 | |
| 161 | dev->pdev = of_find_device_by_node(args.np); |
| 162 | if (!dev->pdev) { |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 163 | err = -ENODEV; |
| 164 | goto free; |
| 165 | } |
| 166 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 167 | dev->mipi = platform_get_drvdata(dev->pdev); |
| 168 | if (!dev->mipi) { |
| 169 | err = -EPROBE_DEFER; |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 170 | goto put; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 171 | } |
| 172 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 173 | of_node_put(args.np); |
| 174 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 175 | dev->pads = args.args[0]; |
| 176 | dev->device = device; |
| 177 | |
| 178 | return dev; |
| 179 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 180 | put: |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 181 | platform_device_put(dev->pdev); |
| 182 | free: |
| 183 | kfree(dev); |
| 184 | out: |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 185 | of_node_put(args.np); |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 186 | return ERR_PTR(err); |
| 187 | } |
| 188 | EXPORT_SYMBOL(tegra_mipi_request); |
| 189 | |
| 190 | void tegra_mipi_free(struct tegra_mipi_device *device) |
| 191 | { |
| 192 | platform_device_put(device->pdev); |
| 193 | kfree(device); |
| 194 | } |
| 195 | EXPORT_SYMBOL(tegra_mipi_free); |
| 196 | |
| 197 | static int tegra_mipi_wait(struct tegra_mipi *mipi) |
| 198 | { |
| 199 | unsigned long timeout = jiffies + msecs_to_jiffies(250); |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 200 | u32 value; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 201 | |
| 202 | while (time_before(jiffies, timeout)) { |
| 203 | value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); |
| 204 | if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && |
| 205 | (value & MIPI_CAL_STATUS_DONE) != 0) |
| 206 | return 0; |
| 207 | |
| 208 | usleep_range(10, 50); |
| 209 | } |
| 210 | |
| 211 | return -ETIMEDOUT; |
| 212 | } |
| 213 | |
| 214 | int tegra_mipi_calibrate(struct tegra_mipi_device *device) |
| 215 | { |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 216 | const struct tegra_mipi_soc *soc = device->mipi->soc; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 217 | unsigned int i; |
Thierry Reding | 57b17ae | 2014-10-02 14:33:31 +0200 | [diff] [blame] | 218 | u32 value; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 219 | int err; |
| 220 | |
| 221 | err = clk_enable(device->mipi->clk); |
| 222 | if (err < 0) |
| 223 | return err; |
| 224 | |
| 225 | mutex_lock(&device->mipi->lock); |
| 226 | |
| 227 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0); |
| 228 | value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP; |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 229 | |
| 230 | if (soc->needs_vclamp_ref) |
| 231 | value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; |
| 232 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 233 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0); |
| 234 | |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 235 | value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) | |
| 236 | MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref); |
| 237 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1); |
Sean Paul | b298e98 | 2014-09-10 10:52:05 -0400 | [diff] [blame] | 238 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 239 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); |
| 240 | value &= ~MIPI_CAL_BIAS_PAD_PDVREG; |
| 241 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); |
| 242 | |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 243 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); |
| 244 | value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7); |
| 245 | value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7); |
| 246 | value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level); |
| 247 | value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level); |
| 248 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); |
| 249 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 250 | for (i = 0; i < soc->num_pads; i++) { |
| 251 | u32 clk = 0, data = 0; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 252 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 253 | if (device->pads & BIT(i)) { |
| 254 | data = MIPI_CAL_CONFIG_SELECT | |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 255 | MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) | |
| 256 | MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) | |
| 257 | MIPI_CAL_CONFIG_TERMOS(soc->termos); |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 258 | clk = MIPI_CAL_CONFIG_SELECT | |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 259 | MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) | |
| 260 | MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos); |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | tegra_mipi_writel(device->mipi, data, soc->pads[i].data); |
| 264 | |
| 265 | if (soc->has_clk_lane) |
| 266 | tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk); |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 267 | } |
| 268 | |
Sean Paul | 26f7a92 | 2014-09-10 10:52:03 -0400 | [diff] [blame] | 269 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 270 | value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf); |
| 271 | value &= ~MIPI_CAL_CTRL_PRESCALE(0x3); |
| 272 | value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa); |
| 273 | value |= MIPI_CAL_CTRL_PRESCALE(0x2); |
| 274 | |
| 275 | if (!soc->clock_enable_override) |
| 276 | value &= ~MIPI_CAL_CTRL_CLKEN_OVR; |
| 277 | else |
| 278 | value |= MIPI_CAL_CTRL_CLKEN_OVR; |
| 279 | |
| 280 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); |
| 281 | |
Thierry Reding | 2ed264b | 2015-04-08 17:17:44 +0200 | [diff] [blame] | 282 | /* clear any pending status bits */ |
| 283 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS); |
| 284 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS); |
| 285 | |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 286 | value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
Sean Paul | 26f7a92 | 2014-09-10 10:52:03 -0400 | [diff] [blame] | 287 | value |= MIPI_CAL_CTRL_START; |
| 288 | tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 289 | |
| 290 | err = tegra_mipi_wait(device->mipi); |
| 291 | |
| 292 | mutex_unlock(&device->mipi->lock); |
| 293 | clk_disable(device->mipi->clk); |
| 294 | |
| 295 | return err; |
| 296 | } |
| 297 | EXPORT_SYMBOL(tegra_mipi_calibrate); |
| 298 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 299 | static const struct tegra_mipi_pad tegra114_mipi_pads[] = { |
| 300 | { .data = MIPI_CAL_CONFIG_CSIA }, |
| 301 | { .data = MIPI_CAL_CONFIG_CSIB }, |
| 302 | { .data = MIPI_CAL_CONFIG_CSIC }, |
| 303 | { .data = MIPI_CAL_CONFIG_CSID }, |
| 304 | { .data = MIPI_CAL_CONFIG_CSIE }, |
| 305 | { .data = MIPI_CAL_CONFIG_DSIA }, |
| 306 | { .data = MIPI_CAL_CONFIG_DSIB }, |
| 307 | { .data = MIPI_CAL_CONFIG_DSIC }, |
| 308 | { .data = MIPI_CAL_CONFIG_DSID }, |
| 309 | }; |
| 310 | |
| 311 | static const struct tegra_mipi_soc tegra114_mipi_soc = { |
| 312 | .has_clk_lane = false, |
| 313 | .pads = tegra114_mipi_pads, |
| 314 | .num_pads = ARRAY_SIZE(tegra114_mipi_pads), |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 315 | .clock_enable_override = true, |
| 316 | .needs_vclamp_ref = true, |
| 317 | .pad_drive_down_ref = 0x2, |
| 318 | .pad_drive_up_ref = 0x0, |
| 319 | .pad_vclamp_level = 0x0, |
| 320 | .pad_vauxp_level = 0x0, |
| 321 | .hspdos = 0x0, |
| 322 | .hspuos = 0x4, |
| 323 | .termos = 0x5, |
| 324 | .hsclkpdos = 0x0, |
| 325 | .hsclkpuos = 0x4, |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 326 | }; |
| 327 | |
| 328 | static const struct tegra_mipi_pad tegra124_mipi_pads[] = { |
| 329 | { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, |
| 330 | { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, |
| 331 | { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, |
| 332 | { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, |
Thierry Reding | 8ed5c06 | 2015-04-08 17:06:08 +0200 | [diff] [blame] | 333 | { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK }, |
| 334 | { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK }, |
| 335 | { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK }, |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | static const struct tegra_mipi_soc tegra124_mipi_soc = { |
| 339 | .has_clk_lane = true, |
| 340 | .pads = tegra124_mipi_pads, |
| 341 | .num_pads = ARRAY_SIZE(tegra124_mipi_pads), |
Thierry Reding | 83a3c22 | 2015-04-08 17:03:49 +0200 | [diff] [blame] | 342 | .clock_enable_override = true, |
| 343 | .needs_vclamp_ref = true, |
| 344 | .pad_drive_down_ref = 0x2, |
| 345 | .pad_drive_up_ref = 0x0, |
| 346 | .pad_vclamp_level = 0x0, |
| 347 | .pad_vauxp_level = 0x0, |
| 348 | .hspdos = 0x0, |
| 349 | .hspuos = 0x0, |
| 350 | .termos = 0x0, |
| 351 | .hsclkpdos = 0x1, |
| 352 | .hsclkpuos = 0x2, |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 353 | }; |
| 354 | |
Thierry Reding | 7fd3eca | 2015-04-08 17:20:32 +0200 | [diff] [blame^] | 355 | static const struct tegra_mipi_soc tegra132_mipi_soc = { |
| 356 | .has_clk_lane = true, |
| 357 | .pads = tegra124_mipi_pads, |
| 358 | .num_pads = ARRAY_SIZE(tegra124_mipi_pads), |
| 359 | .clock_enable_override = false, |
| 360 | .needs_vclamp_ref = false, |
| 361 | .pad_drive_down_ref = 0x0, |
| 362 | .pad_drive_up_ref = 0x3, |
| 363 | .pad_vclamp_level = 0x0, |
| 364 | .pad_vauxp_level = 0x0, |
| 365 | .hspdos = 0x0, |
| 366 | .hspuos = 0x0, |
| 367 | .termos = 0x0, |
| 368 | .hsclkpdos = 0x3, |
| 369 | .hsclkpuos = 0x2, |
| 370 | }; |
| 371 | |
Thierry Reding | c22fb79 | 2015-04-08 17:19:19 +0200 | [diff] [blame] | 372 | static const struct of_device_id tegra_mipi_of_match[] = { |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 373 | { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc }, |
| 374 | { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc }, |
Thierry Reding | 7fd3eca | 2015-04-08 17:20:32 +0200 | [diff] [blame^] | 375 | { .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc }, |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 376 | { }, |
| 377 | }; |
| 378 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 379 | static int tegra_mipi_probe(struct platform_device *pdev) |
| 380 | { |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 381 | const struct of_device_id *match; |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 382 | struct tegra_mipi *mipi; |
| 383 | struct resource *res; |
| 384 | int err; |
| 385 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 386 | match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node); |
| 387 | if (!match) |
| 388 | return -ENODEV; |
| 389 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 390 | mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL); |
| 391 | if (!mipi) |
| 392 | return -ENOMEM; |
| 393 | |
Sean Paul | 08a15cc | 2014-09-10 10:52:04 -0400 | [diff] [blame] | 394 | mipi->soc = match->data; |
| 395 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 396 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 397 | mipi->regs = devm_ioremap_resource(&pdev->dev, res); |
| 398 | if (IS_ERR(mipi->regs)) |
| 399 | return PTR_ERR(mipi->regs); |
| 400 | |
| 401 | mutex_init(&mipi->lock); |
| 402 | |
| 403 | mipi->clk = devm_clk_get(&pdev->dev, NULL); |
| 404 | if (IS_ERR(mipi->clk)) { |
| 405 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 406 | return PTR_ERR(mipi->clk); |
| 407 | } |
| 408 | |
| 409 | err = clk_prepare(mipi->clk); |
| 410 | if (err < 0) |
| 411 | return err; |
| 412 | |
| 413 | platform_set_drvdata(pdev, mipi); |
| 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | static int tegra_mipi_remove(struct platform_device *pdev) |
| 419 | { |
| 420 | struct tegra_mipi *mipi = platform_get_drvdata(pdev); |
| 421 | |
| 422 | clk_unprepare(mipi->clk); |
| 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |
Thierry Reding | 4de6a2d | 2013-09-02 09:48:53 +0200 | [diff] [blame] | 427 | struct platform_driver tegra_mipi_driver = { |
| 428 | .driver = { |
| 429 | .name = "tegra-mipi", |
| 430 | .of_match_table = tegra_mipi_of_match, |
| 431 | }, |
| 432 | .probe = tegra_mipi_probe, |
| 433 | .remove = tegra_mipi_remove, |
| 434 | }; |