arch/arm/boot/dts/am43x-epos-evm.dts

/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* AM43x EPOS EVM */

/dts-v1/;

#include "am4372.dtsi"
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "TI AM43x EPOS EVM";
	compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";

	aliases {
		display0 = &lcd0;
	};

	vmmcsd_fixed: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
	};

	lcd0: display {
		compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
		label = "lcd";

		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins>;

		/*
		 * SelLCDorHDMI, LOW to select HDMI. This is not really the
		 * panel's enable GPIO, but we don't have HDMI driver support nor
		 * support to switch between two displays, so using this gpio as
		 * panel's enable should be safe.
		 */
		enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;

		panel-timing {
			clock-frequency = <33000000>;
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <210>;
			hback-porch = <16>;
			hsync-len = <30>;
			vback-porch = <10>;
			vfront-porch = <22>;
			vsync-len = <13>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <1>;
		};

		port {
			lcd_in: endpoint {
				remote-endpoint = <&dpi_out>;
			};
		};
	};

	am43xx_pinmux: pinmux@44e10800 {
		cpsw_default: cpsw_default {
			pinctrl-single,pins = <
				/* Slave 1 */
				0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs */
				0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
				0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
				0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxdv.rmii1_rxdv */
				0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
				0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
				0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
				0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
				0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
			>;
		};

		cpsw_sleep: cpsw_sleep {
			pinctrl-single,pins = <
				/* Slave 1 reset value */
				0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};

		davinci_mdio_default: davinci_mdio_default {
			pinctrl-single,pins = <
				/* MDIO */
				0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
				0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
			>;
		};

		davinci_mdio_sleep: davinci_mdio_sleep {
			pinctrl-single,pins = <
				/* MDIO reset value */
				0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};

		i2c0_pins: pinmux_i2c0_pins {
			pinctrl-single,pins = <
				0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			>;
		};

		nand_flash_x8: nand_flash_x8 {
			pinctrl-single,pins = <
				0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.SELQSPIorNAND/GPIO */
				0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
				0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
				0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
				0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
				0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
				0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
				0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
				0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
				0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
				0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
				0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
				0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
				0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
				0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
				0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
			>;
		};

		ecap0_pins: backlight_pins {
			pinctrl-single,pins = <
				0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
			>;
		};

		i2c2_pins: pinmux_i2c2_pins {
			pinctrl-single,pins = <
				0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
				0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
			>;
		};

		spi0_pins: pinmux_spi0_pins {
			pinctrl-single,pins = <
				0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
				0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
				0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
				0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
			>;
		};

		spi1_pins: pinmux_spi1_pins {
			pinctrl-single,pins = <
				0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
				0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
				0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
				0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
			>;
		};

		mmc1_pins: pinmux_mmc1_pins {
			pinctrl-single,pins = <
				0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
			>;
		};

		qspi1_default: qspi1_default {
			pinctrl-single,pins = <
				0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
				0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
				0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
				0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
				0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
				0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
			>;
		};

		pixcir_ts_pins: pixcir_ts_pins {
			pinctrl-single,pins = <
				0x44 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a1.gpio1_17 */
			>;
		};

		hdq_pins: pinmux_hdq_pins {
			pinctrl-single,pins = <
				0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
			>;
		};

		dss_pins: dss_pins {
			pinctrl-single,pins = <
				0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
				0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
				0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
				0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
				0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
				0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
				0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
				0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
				0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
				0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
			>;
		};

		lcd_pins: lcd_pins {
			pinctrl-single,pins = <
				/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
				0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
			>;
		};
	};

	matrix_keypad: matrix_keypad@0 {
			compatible = "gpio-matrix-keypad";
			debounce-delay-ms = <5>;
			col-scan-delay-us = <2>;

			row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH		/* Bank0, pin12 */
				     &gpio0 13 GPIO_ACTIVE_HIGH		/* Bank0, pin13 */
				     &gpio0 14 GPIO_ACTIVE_HIGH		/* Bank0, pin14 */
				     &gpio0 15 GPIO_ACTIVE_HIGH>;	/* Bank0, pin15 */

			col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH		/* Bank3, pin9 */
				     &gpio3 10 GPIO_ACTIVE_HIGH		/* Bank3, pin10 */
				     &gpio2 18 GPIO_ACTIVE_HIGH		/* Bank2, pin18 */
				     &gpio2 19 GPIO_ACTIVE_HIGH>;	/* Bank2, pin19 */

			linux,keymap = <0x00000201	/* P1 */
				0x01000204	/* P4 */
				0x02000207	/* P7 */
				0x0300020a	/* NUMERIC_STAR */
				0x00010202	/* P2 */
				0x01010205	/* P5 */
				0x02010208	/* P8 */
				0x03010200	/* P0 */
				0x00020203	/* P3 */
				0x01020206	/* P6 */
				0x02020209	/* P9 */
				0x0302020b	/* NUMERIC_POUND */
				0x00030067	/* UP */
				0x0103006a	/* RIGHT */
				0x0203006c	/* DOWN */
				0x03030069>;	/* LEFT */
		};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
		brightness-levels = <0 51 53 56 62 75 101 152 255>;
		default-brightness-level = <8>;
	};
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <16>;
	phy-mode = "rmii";
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rmii";
};

&phy_sel {
	rmii-clock-ext;
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <400000>;

	tps65218: tps65218@24 {
		reg = <0x24>;
		compatible = "ti,tps65218";
		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
		interrupt-parent = <&gic>;
		interrupt-controller;
		#interrupt-cells = <2>;

		dcdc1: regulator-dcdc1 {
			compatible = "ti,tps65218-dcdc1";
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912000>;
			regulator-max-microvolt = <1144000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc2: regulator-dcdc2 {
			compatible = "ti,tps65218-dcdc2";
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912000>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc3: regulator-dcdc3 {
			compatible = "ti,tps65218-dcdc3";
			regulator-name = "vdcdc3";
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <1500000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc5: regulator-dcdc5 {
			compatible = "ti,tps65218-dcdc5";
			regulator-name = "v1_0bat";
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
		};

		dcdc6: regulator-dcdc6 {
			compatible = "ti,tps65218-dcdc6";
			regulator-name = "v1_8bat";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		ldo1: regulator-ldo1 {
			compatible = "ti,tps65218-ldo1";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
			regulator-always-on;
		};
	};

	at24@50 {
		compatible = "at24,24c256";
		pagesize = <64>;
		reg = <0x50>;
	};

	pixcir_ts@5c {
		compatible = "pixcir,pixcir_tangoc";
		pinctrl-names = "default";
		pinctrl-0 = <&pixcir_ts_pins>;
		reg = <0x5c>;
		interrupt-parent = <&gpio1>;
		interrupts = <17 0>;

		attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;

		touchscreen-size-x = <1024>;
		touchscreen-size-y = <600>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";	/* Disable QSPI when enabling GPMC (NAND) */
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
	nand@0,0 {
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		ti,nand-ecc-opt = "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
		gpmc,cs-wr-off-ns = <40>;
		gpmc,adv-on-ns = <0>;  /* cs-on-ns */
		gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
		gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
		gpmc,we-on-ns = <0>;   /* cs-on-ns */
		gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
		gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
		gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
		gpmc,access-ns = <30>; /* tCEA + 4*/
		gpmc,rd-cycle-ns = <40>;
		gpmc,wr-cycle-ns = <40>;
		gpmc,wait-pin = <0>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000C0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00100000 0x00080000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x00180000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x00280000 0x00040000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x002C0000 0x00040000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00300000 0x00700000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x1f600000>;
		};
	};
};

&epwmss0 {
	status = "okay";
};

&tscadc {
	status = "okay";

	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&ecap0 {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&ecap0_pins>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";
};

&usb2_phy1 {
	status = "okay";
};

&usb1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usb2_phy2 {
	status = "okay";
};

&usb2 {
	dr_mode = "host";
	status = "okay";
};

&qspi {
	status = "disabled";	/* Disable GPMC (NAND) when enabling QSPI */
	pinctrl-names = "default";
	pinctrl-0 = <&qspi1_default>;

	spi-max-frequency = <48000000>;
	m25p80@0 {
		compatible = "mx66l51235l";
		spi-max-frequency = <48000000>;
		reg = <0>;
		spi-cpol;
		spi-cpha;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first 512KiB
		 * for a valid file to boot(XIP).
		 */
		partition@0 {
			label = "QSPI.U_BOOT";
			reg = <0x00000000 0x000080000>;
		};
		partition@1 {
			label = "QSPI.U_BOOT.backup";
			reg = <0x00080000 0x00080000>;
		};
		partition@2 {
			label = "QSPI.U-BOOT-SPL_OS";
			reg = <0x00100000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.U_BOOT_ENV";
			reg = <0x00110000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.U-BOOT-ENV.backup";
			reg = <0x00120000 0x00010000>;
		};
		partition@5 {
			label = "QSPI.KERNEL";
			reg = <0x00130000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.FILESYSTEM";
			reg = <0x00930000 0x36D0000>;
		};
	};
};

&hdq {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&hdq_pins>;
};

&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
		dpi_out: endpoint@0 {
			remote-endpoint = <&lcd_in>;
			data-lines = <24>;
		};
	};
};