blob: 7e8d630138f51c1be6ff3d5678c644232eac9f82 [file] [log] [blame]
Maxime Ripard8aed3b32013-03-10 16:09:06 +01001/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <1>;
33 };
34
35 cpu@2 {
36 compatible = "arm,cortex-a7";
37 device_type = "cpu";
38 reg = <2>;
39 };
40
41 cpu@3 {
42 compatible = "arm,cortex-a7";
43 device_type = "cpu";
44 reg = <3>;
45 };
46 };
47
48 memory {
49 reg = <0x40000000 0x80000000>;
50 };
51
52 clocks {
53 #address-cells = <1>;
Maxime Ripard98096562013-07-23 23:54:19 +020054 #size-cells = <1>;
55 ranges;
Maxime Ripard8aed3b32013-03-10 16:09:06 +010056
Maxime Ripard98096562013-07-23 23:54:19 +020057 osc24M: osc24M {
Maxime Ripard8aed3b32013-03-10 16:09:06 +010058 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
Maxime Ripard98096562013-07-23 23:54:19 +020062
63 osc32k: osc32k {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 pll1: pll1@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
88 cpu: cpu@01c20050 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
92
93 /*
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
97 * Allwinner.
98 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
100 };
101
102 axi: axi@01c20050 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>;
107 };
108
109 ahb1_mux: ahb1_mux@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
114 };
115
116 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
121 };
122
123 ahb1_gates: ahb1_gates@01c20060 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
127 clocks = <&ahb1>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
142 };
143
144 apb1: apb1@01c20054 {
145 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>;
149 };
150
151 apb1_gates: apb1_gates@01c20060 {
152 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
155 clocks = <&apb1>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
158 "apb1_daudio1";
159 };
160
161 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166 };
167
168 apb2: apb2@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
173 };
174
175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
Maxime Ripard439d9f52013-09-24 16:30:05 +0300178 reg = <0x01c2006c 0x4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
184 };
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100185 };
186
187 soc@01c00000 {
188 compatible = "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges;
192
Maxime Ripard140e1722013-03-12 22:16:05 +0100193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
Maxime Ripard98096562013-07-23 23:54:19 +0200197 clocks = <&apb1_gates 5>;
Maxime Ripard140e1722013-03-12 22:16:05 +0100198 gpio-controller;
199 interrupt-controller;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #gpio-cells = <3>;
Maxime Ripardab4238c2013-06-22 23:56:40 +0200203
204 uart0_pins_a: uart0@0 {
205 allwinner,pins = "PH20", "PH21";
206 allwinner,function = "uart0";
207 allwinner,drive = <0>;
208 allwinner,pull = <0>;
209 };
Maxime Ripard140e1722013-03-12 22:16:05 +0100210 };
211
Maxime Ripard24a661e92013-09-24 11:10:41 +0300212 ahb1_rst: reset@01c202c0 {
213 #reset-cells = <1>;
214 compatible = "allwinner,sun6i-a31-ahb1-reset";
215 reg = <0x01c202c0 0xc>;
216 };
217
218 apb1_rst: reset@01c202d0 {
219 #reset-cells = <1>;
220 compatible = "allwinner,sun6i-a31-clock-reset";
221 reg = <0x01c202d0 0x4>;
222 };
223
224 apb2_rst: reset@01c202d8 {
225 #reset-cells = <1>;
226 compatible = "allwinner,sun6i-a31-clock-reset";
227 reg = <0x01c202d8 0x4>;
228 };
229
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100230 timer@01c20c00 {
231 compatible = "allwinner,sun4i-timer";
232 reg = <0x01c20c00 0xa0>;
233 interrupts = <0 18 1>,
234 <0 19 1>,
235 <0 20 1>,
236 <0 21 1>,
237 <0 22 1>;
Maxime Ripard98096562013-07-23 23:54:19 +0200238 clocks = <&osc24M>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100239 };
240
241 wdt1: watchdog@01c20ca0 {
242 compatible = "allwinner,sun6i-wdt";
243 reg = <0x01c20ca0 0x20>;
244 };
245
246 uart0: serial@01c28000 {
247 compatible = "snps,dw-apb-uart";
248 reg = <0x01c28000 0x400>;
249 interrupts = <0 0 1>;
250 reg-shift = <2>;
251 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200252 clocks = <&apb2_gates 16>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300253 resets = <&apb2_rst 16>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100254 status = "disabled";
255 };
256
257 uart1: serial@01c28400 {
258 compatible = "snps,dw-apb-uart";
259 reg = <0x01c28400 0x400>;
260 interrupts = <0 1 1>;
261 reg-shift = <2>;
262 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200263 clocks = <&apb2_gates 17>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300264 resets = <&apb2_rst 17>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100265 status = "disabled";
266 };
267
268 uart2: serial@01c28800 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x01c28800 0x400>;
271 interrupts = <0 2 1>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200274 clocks = <&apb2_gates 18>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300275 resets = <&apb2_rst 18>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100276 status = "disabled";
277 };
278
279 uart3: serial@01c28c00 {
280 compatible = "snps,dw-apb-uart";
281 reg = <0x01c28c00 0x400>;
282 interrupts = <0 3 1>;
283 reg-shift = <2>;
284 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200285 clocks = <&apb2_gates 19>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300286 resets = <&apb2_rst 19>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100287 status = "disabled";
288 };
289
290 uart4: serial@01c29000 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x01c29000 0x400>;
293 interrupts = <0 4 1>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200296 clocks = <&apb2_gates 20>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300297 resets = <&apb2_rst 20>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100298 status = "disabled";
299 };
300
301 uart5: serial@01c29400 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x01c29400 0x400>;
304 interrupts = <0 5 1>;
305 reg-shift = <2>;
306 reg-io-width = <4>;
Maxime Ripard98096562013-07-23 23:54:19 +0200307 clocks = <&apb2_gates 21>;
Maxime Ripard24a661e92013-09-24 11:10:41 +0300308 resets = <&apb2_rst 21>;
Maxime Ripard8aed3b32013-03-10 16:09:06 +0100309 status = "disabled";
310 };
311
312 gic: interrupt-controller@01c81000 {
313 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
314 reg = <0x01c81000 0x1000>,
315 <0x01c82000 0x1000>,
316 <0x01c84000 0x2000>,
317 <0x01c86000 0x2000>;
318 interrupt-controller;
319 #interrupt-cells = <3>;
320 interrupts = <1 9 0xf04>;
321 };
322 };
323};