| Maxime Ripard | 8aed3b3 | 2013-03-10 16:09:06 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
| 14 | /include/ "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | interrupt-parent = <&gic>; |
| 18 | |
| 19 | cpus { |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
| 22 | |
| 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a7"; |
| 25 | device_type = "cpu"; |
| 26 | reg = <0>; |
| 27 | }; |
| 28 | |
| 29 | cpu@1 { |
| 30 | compatible = "arm,cortex-a7"; |
| 31 | device_type = "cpu"; |
| 32 | reg = <1>; |
| 33 | }; |
| 34 | |
| 35 | cpu@2 { |
| 36 | compatible = "arm,cortex-a7"; |
| 37 | device_type = "cpu"; |
| 38 | reg = <2>; |
| 39 | }; |
| 40 | |
| 41 | cpu@3 { |
| 42 | compatible = "arm,cortex-a7"; |
| 43 | device_type = "cpu"; |
| 44 | reg = <3>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | memory { |
| 49 | reg = <0x40000000 0x80000000>; |
| 50 | }; |
| 51 | |
| 52 | clocks { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | |
| 56 | osc: oscillator { |
| 57 | #clock-cells = <0>; |
| 58 | compatible = "fixed-clock"; |
| 59 | clock-frequency = <24000000>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc@01c00000 { |
| 64 | compatible = "simple-bus"; |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <1>; |
| 67 | ranges; |
| 68 | |
| 69 | timer@01c20c00 { |
| 70 | compatible = "allwinner,sun4i-timer"; |
| 71 | reg = <0x01c20c00 0xa0>; |
| 72 | interrupts = <0 18 1>, |
| 73 | <0 19 1>, |
| 74 | <0 20 1>, |
| 75 | <0 21 1>, |
| 76 | <0 22 1>; |
| 77 | clocks = <&osc>; |
| 78 | }; |
| 79 | |
| 80 | wdt1: watchdog@01c20ca0 { |
| 81 | compatible = "allwinner,sun6i-wdt"; |
| 82 | reg = <0x01c20ca0 0x20>; |
| 83 | }; |
| 84 | |
| 85 | uart0: serial@01c28000 { |
| 86 | compatible = "snps,dw-apb-uart"; |
| 87 | reg = <0x01c28000 0x400>; |
| 88 | interrupts = <0 0 1>; |
| 89 | reg-shift = <2>; |
| 90 | reg-io-width = <4>; |
| 91 | clocks = <&osc>; |
| 92 | status = "disabled"; |
| 93 | }; |
| 94 | |
| 95 | uart1: serial@01c28400 { |
| 96 | compatible = "snps,dw-apb-uart"; |
| 97 | reg = <0x01c28400 0x400>; |
| 98 | interrupts = <0 1 1>; |
| 99 | reg-shift = <2>; |
| 100 | reg-io-width = <4>; |
| 101 | clocks = <&osc>; |
| 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | uart2: serial@01c28800 { |
| 106 | compatible = "snps,dw-apb-uart"; |
| 107 | reg = <0x01c28800 0x400>; |
| 108 | interrupts = <0 2 1>; |
| 109 | reg-shift = <2>; |
| 110 | reg-io-width = <4>; |
| 111 | clocks = <&osc>; |
| 112 | status = "disabled"; |
| 113 | }; |
| 114 | |
| 115 | uart3: serial@01c28c00 { |
| 116 | compatible = "snps,dw-apb-uart"; |
| 117 | reg = <0x01c28c00 0x400>; |
| 118 | interrupts = <0 3 1>; |
| 119 | reg-shift = <2>; |
| 120 | reg-io-width = <4>; |
| 121 | clocks = <&osc>; |
| 122 | status = "disabled"; |
| 123 | }; |
| 124 | |
| 125 | uart4: serial@01c29000 { |
| 126 | compatible = "snps,dw-apb-uart"; |
| 127 | reg = <0x01c29000 0x400>; |
| 128 | interrupts = <0 4 1>; |
| 129 | reg-shift = <2>; |
| 130 | reg-io-width = <4>; |
| 131 | clocks = <&osc>; |
| 132 | status = "disabled"; |
| 133 | }; |
| 134 | |
| 135 | uart5: serial@01c29400 { |
| 136 | compatible = "snps,dw-apb-uart"; |
| 137 | reg = <0x01c29400 0x400>; |
| 138 | interrupts = <0 5 1>; |
| 139 | reg-shift = <2>; |
| 140 | reg-io-width = <4>; |
| 141 | clocks = <&osc>; |
| 142 | status = "disabled"; |
| 143 | }; |
| 144 | |
| 145 | gic: interrupt-controller@01c81000 { |
| 146 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 147 | reg = <0x01c81000 0x1000>, |
| 148 | <0x01c82000 0x1000>, |
| 149 | <0x01c84000 0x2000>, |
| 150 | <0x01c86000 0x2000>; |
| 151 | interrupt-controller; |
| 152 | #interrupt-cells = <3>; |
| 153 | interrupts = <1 9 0xf04>; |
| 154 | }; |
| 155 | }; |
| 156 | }; |