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Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
Thomas Petazzoni92ece1c2012-11-09 16:29:17 +010023 compatible = "marvell,armada-370-xp";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020024
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
Gregory CLEMENT82a68262013-04-12 16:29:08 +020031
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020032 soc {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "simple-bus";
36 interrupt-parent = <&mpic>;
Gregory CLEMENT82a68262013-04-12 16:29:08 +020037 ranges = <0 0xd0000000 0x100000>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020038
Gregory CLEMENT82a68262013-04-12 16:29:08 +020039 mpic: interrupt-controller@20000 {
40 compatible = "marvell,mpic";
41 #interrupt-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
Thomas Petazzonib18ea4d2013-04-12 16:29:07 +020044 };
45
Gregory CLEMENT82a68262013-04-12 16:29:08 +020046 coherency-fabric@20200 {
47 compatible = "marvell,coherency-fabric";
48 reg = <0x20200 0xb0>,
49 <0x21810 0x1c>;
Thomas Petazzonib18ea4d2013-04-12 16:29:07 +020050 };
51
Gregory CLEMENT82a68262013-04-12 16:29:08 +020052 serial@12000 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010053 compatible = "snps,dw-apb-uart";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020054 reg = <0x12000 0x100>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020055 reg-shift = <2>;
56 interrupts = <41>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010057 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020058 status = "disabled";
59 };
Gregory CLEMENT82a68262013-04-12 16:29:08 +020060 serial@12100 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010061 compatible = "snps,dw-apb-uart";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020062 reg = <0x12100 0x100>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020063 reg-shift = <2>;
64 interrupts = <42>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010065 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020066 status = "disabled";
67 };
68
Gregory CLEMENT82a68262013-04-12 16:29:08 +020069 timer@20300 {
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020070 compatible = "marvell,armada-370-xp-timer";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020071 reg = <0x20300 0x30>,
72 <0x21040 0x30>;
Gregory CLEMENTe1dd4642013-01-25 18:32:44 +010073 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010074 clocks = <&coreclk 2>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020075 };
Thomas Petazzoni5b40bae2012-09-11 14:27:30 +020076
Gregory CLEMENT82a68262013-04-12 16:29:08 +020077 sata@a0000 {
Gregory CLEMENTa6a6de12012-10-26 14:30:47 +020078 compatible = "marvell,orion-sata";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020079 reg = <0xa0000 0x2400>;
Gregory CLEMENTa6a6de12012-10-26 14:30:47 +020080 interrupts = <55>;
81 clocks = <&gateclk 15>, <&gateclk 30>;
82 clock-names = "0", "1";
83 status = "disabled";
84 };
85
Thomas Petazzoni323c1012012-09-04 15:06:43 +020086 mdio {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "marvell,orion-mdio";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020090 reg = <0x72004 0x4>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +020091 };
92
Gregory CLEMENT82a68262013-04-12 16:29:08 +020093 ethernet@70000 {
Thomas Petazzoni323c1012012-09-04 15:06:43 +020094 compatible = "marvell,armada-370-neta";
Gregory CLEMENT82a68262013-04-12 16:29:08 +020095 reg = <0x70000 0x2500>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +020096 interrupts = <8>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +010097 clocks = <&gateclk 4>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +020098 status = "disabled";
99 };
100
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200101 ethernet@74000 {
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200102 compatible = "marvell,armada-370-neta";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200103 reg = <0x74000 0x2500>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200104 interrupts = <10>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100105 clocks = <&gateclk 3>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200106 status = "disabled";
107 };
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900108
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200109 i2c0: i2c@11000 {
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900110 compatible = "marvell,mv64xxx-i2c";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200111 reg = <0x11000 0x20>;
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900112 #address-cells = <1>;
113 #size-cells = <0>;
114 interrupts = <31>;
115 timeout-ms = <1000>;
116 clocks = <&coreclk 0>;
117 status = "disabled";
118 };
119
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200120 i2c1: i2c@11100 {
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900121 compatible = "marvell,mv64xxx-i2c";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200122 reg = <0x11100 0x20>;
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900123 #address-cells = <1>;
124 #size-cells = <0>;
125 interrupts = <32>;
126 timeout-ms = <1000>;
127 clocks = <&coreclk 0>;
128 status = "disabled";
129 };
Gregory CLEMENT0db98542012-12-12 10:06:24 +0100130
131 rtc@10300 {
132 compatible = "marvell,orion-rtc";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200133 reg = <0x10300 0x20>;
Gregory CLEMENT0db98542012-12-12 10:06:24 +0100134 interrupts = <50>;
135 };
Thomas Petazzoni42bb5312012-12-21 15:49:04 +0100136
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200137 mvsdio@d4000 {
Thomas Petazzoni42bb5312012-12-21 15:49:04 +0100138 compatible = "marvell,orion-sdio";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200139 reg = <0xd4000 0x200>;
Thomas Petazzoni42bb5312012-12-21 15:49:04 +0100140 interrupts = <54>;
141 clocks = <&gateclk 17>;
142 status = "disabled";
143 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300144
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200145 usb@50000 {
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300146 compatible = "marvell,orion-ehci";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200147 reg = <0x50000 0x500>;
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300148 interrupts = <45>;
149 status = "disabled";
150 };
151
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200152 usb@51000 {
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300153 compatible = "marvell,orion-ehci";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200154 reg = <0x51000 0x500>;
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300155 interrupts = <46>;
156 status = "disabled";
157 };
158
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200159 spi0: spi@10600 {
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300160 compatible = "marvell,orion-spi";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200161 reg = <0x10600 0x28>;
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300162 #address-cells = <1>;
163 #size-cells = <0>;
164 cell-index = <0>;
165 interrupts = <30>;
166 clocks = <&coreclk 0>;
167 status = "disabled";
168 };
169
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200170 spi1: spi@10680 {
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300171 compatible = "marvell,orion-spi";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200172 reg = <0x10680 0x28>;
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300173 #address-cells = <1>;
174 #size-cells = <0>;
175 cell-index = <1>;
176 interrupts = <92>;
177 clocks = <&coreclk 0>;
178 status = "disabled";
179 };
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300180
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200181 devbus-bootcs@10400 {
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300182 compatible = "marvell,mvebu-devbus";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200183 reg = <0x10400 0x8>;
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300184 #address-cells = <1>;
185 #size-cells = <1>;
186 clocks = <&coreclk 0>;
187 status = "disabled";
188 };
189
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200190 devbus-cs0@10408 {
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300191 compatible = "marvell,mvebu-devbus";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200192 reg = <0x10408 0x8>;
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300193 #address-cells = <1>;
194 #size-cells = <1>;
195 clocks = <&coreclk 0>;
196 status = "disabled";
197 };
198
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200199 devbus-cs1@10410 {
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300200 compatible = "marvell,mvebu-devbus";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200201 reg = <0x10410 0x8>;
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300202 #address-cells = <1>;
203 #size-cells = <1>;
204 clocks = <&coreclk 0>;
205 status = "disabled";
206 };
207
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200208 devbus-cs2@10418 {
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300209 compatible = "marvell,mvebu-devbus";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200210 reg = <0x10418 0x8>;
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300211 #address-cells = <1>;
212 #size-cells = <1>;
213 clocks = <&coreclk 0>;
214 status = "disabled";
215 };
216
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200217 devbus-cs3@10420 {
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300218 compatible = "marvell,mvebu-devbus";
Gregory CLEMENT82a68262013-04-12 16:29:08 +0200219 reg = <0x10420 0x8>;
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300220 #address-cells = <1>;
221 #size-cells = <1>;
222 clocks = <&coreclk 0>;
223 status = "disabled";
224 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200225 };
226};
227