blob: c0cdf66f8964f7a800390ee0dd8c6899b5c0baad [file] [log] [blame]
Christian Daudt8ac49e02012-11-19 09:46:10 -08001/*
2 * Copyright (C) 2012 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Matt Porter5401cc42013-06-06 01:41:35 -040014#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
Matt Porter74375652013-06-06 01:41:34 -040017#include "skeleton.dtsi"
Christian Daudt8ac49e02012-11-19 09:46:10 -080018
19/ {
20 model = "BCM11351 SoC";
21 compatible = "bcm,bcm11351";
22 interrupt-parent = <&gic>;
23
24 chosen {
25 bootargs = "console=ttyS0,115200n8";
26 };
27
28 gic: interrupt-controller@3ff00100 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 #address-cells = <0>;
32 interrupt-controller;
33 reg = <0x3ff01000 0x1000>,
34 <0x3ff00100 0x100>;
35 };
36
Christian Daudt7f6c62e2013-03-13 15:05:37 -070037 smc@0x3404c000 {
38 compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
Matt Porterd22dc5e2013-06-11 14:45:58 -040039 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
Christian Daudt7f6c62e2013-03-13 15:05:37 -070040 };
41
Christian Daudt8ac49e02012-11-19 09:46:10 -080042 uart@3e000000 {
43 compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
44 status = "disabled";
45 reg = <0x3e000000 0x1000>;
46 clock-frequency = <13000000>;
Matt Porter5401cc42013-06-06 01:41:35 -040047 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
Christian Daudt8ac49e02012-11-19 09:46:10 -080048 reg-shift = <2>;
49 reg-io-width = <4>;
50 };
51
52 L2: l2-cache {
Christian Daudt3b656fe2013-05-09 22:21:01 +010053 compatible = "bcm,bcm11351-a2-pl310-cache";
54 reg = <0x3ff20000 0x1000>;
55 cache-unified;
56 cache-level = <2>;
Christian Daudt8ac49e02012-11-19 09:46:10 -080057 };
Christian Daudt5f03dc22013-03-13 14:27:28 -070058
59 timer@35006000 {
60 compatible = "bcm,kona-timer";
61 reg = <0x35006000 0x1000>;
Matt Porter5401cc42013-06-06 01:41:35 -040062 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Christian Daudt5f03dc22013-03-13 14:27:28 -070063 clock-frequency = <32768>;
64 };
65
Christian Daudt2dbfe742013-05-10 00:10:07 -070066 sdio0: sdio@0x3f180000 {
67 compatible = "bcm,kona-sdhci";
68 reg = <0x3f180000 0x10000>;
69 interrupts = <0x0 77 0x4>;
70 status = "disabled";
71 };
72
73 sdio1: sdio@0x3f190000 {
74 compatible = "bcm,kona-sdhci";
75 reg = <0x3f190000 0x10000>;
76 interrupts = <0x0 76 0x4>;
77 status = "disabled";
78 };
79
80 sdio2: sdio@0x3f1a0000 {
81 compatible = "bcm,kona-sdhci";
82 reg = <0x3f1a0000 0x10000>;
83 interrupts = <0x0 74 0x4>;
84 status = "disabled";
85 };
86
87 sdio3: sdio@0x3f1b0000 {
88 compatible = "bcm,kona-sdhci";
89 reg = <0x3f1b0000 0x10000>;
90 interrupts = <0x0 73 0x4>;
91 status = "disabled";
92 };
93
Christian Daudt8ac49e02012-11-19 09:46:10 -080094};