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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _ASM_IA64_SYSTEM_H
2#define _ASM_IA64_SYSTEM_H
3
4/*
5 * System defines. Note that this is included both from .c and .S
6 * files, so it does only defines, not any C code. This is based
7 * on information published in the Processor Abstraction Layer
8 * and the System Abstraction Layer manual.
9 *
10 * Copyright (C) 1998-2003 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
13 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
14 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#include <asm/kregs.h>
17#include <asm/page.h>
18#include <asm/pal.h>
19#include <asm/percpu.h>
20
Peter Chubb0a41e252005-08-16 19:54:00 -070021#define GATE_ADDR RGN_BASE(RGN_GATE)
22
Linus Torvalds1da177e2005-04-16 15:20:36 -070023/*
24 * 0xa000000000000000+2*PERCPU_PAGE_SIZE
25 * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
26 */
Peter Chubb0a41e252005-08-16 19:54:00 -070027#define KERNEL_START (GATE_ADDR+0x100000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
29
30#ifndef __ASSEMBLY__
31
32#include <linux/kernel.h>
33#include <linux/types.h>
34
35struct pci_vector_struct {
36 __u16 segment; /* PCI Segment number */
37 __u16 bus; /* PCI Bus number */
38 __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
39 __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
40 __u32 irq; /* IRQ assigned */
41};
42
43extern struct ia64_boot_param {
44 __u64 command_line; /* physical address of command line arguments */
45 __u64 efi_systab; /* physical address of EFI system table */
46 __u64 efi_memmap; /* physical address of EFI memory map */
47 __u64 efi_memmap_size; /* size of EFI memory map */
48 __u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
49 __u32 efi_memdesc_version; /* memory descriptor version */
50 struct {
51 __u16 num_cols; /* number of columns on console output device */
52 __u16 num_rows; /* number of rows on console output device */
53 __u16 orig_x; /* cursor's x position */
54 __u16 orig_y; /* cursor's y position */
55 } console_info;
56 __u64 fpswa; /* physical address of the fpswa interface */
57 __u64 initrd_start;
58 __u64 initrd_size;
59} *ia64_boot_param;
60
61/*
62 * Macros to force memory ordering. In these descriptions, "previous"
63 * and "subsequent" refer to program order; "visible" means that all
64 * architecturally visible effects of a memory access have occurred
65 * (at a minimum, this means the memory has been read or written).
66 *
67 * wmb(): Guarantees that all preceding stores to memory-
68 * like regions are visible before any subsequent
69 * stores and that all following stores will be
70 * visible only after all previous stores.
71 * rmb(): Like wmb(), but for reads.
72 * mb(): wmb()/rmb() combo, i.e., all previous memory
73 * accesses are visible before all subsequent
74 * accesses and vice versa. This is also known as
75 * a "fence."
76 *
77 * Note: "mb()" and its variants cannot be used as a fence to order
78 * accesses to memory mapped I/O registers. For that, mf.a needs to
79 * be used. However, we don't want to always use mf.a because (a)
80 * it's (presumably) much slower than mf and (b) mf.a is supported for
81 * sequential memory pages only.
82 */
83#define mb() ia64_mf()
84#define rmb() mb()
85#define wmb() mb()
86#define read_barrier_depends() do { } while(0)
87
88#ifdef CONFIG_SMP
89# define smp_mb() mb()
90# define smp_rmb() rmb()
91# define smp_wmb() wmb()
92# define smp_read_barrier_depends() read_barrier_depends()
93#else
94# define smp_mb() barrier()
95# define smp_rmb() barrier()
96# define smp_wmb() barrier()
97# define smp_read_barrier_depends() do { } while(0)
98#endif
99
100/*
101 * XXX check on these---I suspect what Linus really wants here is
102 * acquire vs release semantics but we can't discuss this stuff with
103 * Linus just yet. Grrr...
104 */
105#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
106#define set_wmb(var, value) do { (var) = (value); mb(); } while (0)
107
108#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
109
110/*
111 * The group barrier in front of the rsm & ssm are necessary to ensure
112 * that none of the previous instructions in the same group are
113 * affected by the rsm/ssm.
114 */
115/* For spinlocks etc */
116
117/*
118 * - clearing psr.i is implicitly serialized (visible by next insn)
119 * - setting psr.i requires data serialization
120 * - we need a stop-bit before reading PSR because we sometimes
121 * write a floating-point register right before reading the PSR
122 * and that writes to PSR.mfl
123 */
124#define __local_irq_save(x) \
125do { \
126 ia64_stop(); \
127 (x) = ia64_getreg(_IA64_REG_PSR); \
128 ia64_stop(); \
129 ia64_rsm(IA64_PSR_I); \
130} while (0)
131
132#define __local_irq_disable() \
133do { \
134 ia64_stop(); \
135 ia64_rsm(IA64_PSR_I); \
136} while (0)
137
138#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
139
140#ifdef CONFIG_IA64_DEBUG_IRQ
141
142 extern unsigned long last_cli_ip;
143
144# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
145
146# define local_irq_save(x) \
147do { \
148 unsigned long psr; \
149 \
150 __local_irq_save(psr); \
151 if (psr & IA64_PSR_I) \
152 __save_ip(); \
153 (x) = psr; \
154} while (0)
155
156# define local_irq_disable() do { unsigned long x; local_irq_save(x); } while (0)
157
158# define local_irq_restore(x) \
159do { \
160 unsigned long old_psr, psr = (x); \
161 \
162 local_save_flags(old_psr); \
163 __local_irq_restore(psr); \
164 if ((old_psr & IA64_PSR_I) && !(psr & IA64_PSR_I)) \
165 __save_ip(); \
166} while (0)
167
168#else /* !CONFIG_IA64_DEBUG_IRQ */
169# define local_irq_save(x) __local_irq_save(x)
170# define local_irq_disable() __local_irq_disable()
171# define local_irq_restore(x) __local_irq_restore(x)
172#endif /* !CONFIG_IA64_DEBUG_IRQ */
173
174#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
175#define local_save_flags(flags) ({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); })
176
177#define irqs_disabled() \
178({ \
179 unsigned long __ia64_id_flags; \
180 local_save_flags(__ia64_id_flags); \
181 (__ia64_id_flags & IA64_PSR_I) == 0; \
182})
183
184#ifdef __KERNEL__
185
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186#ifdef CONFIG_IA32_SUPPORT
187# define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
188#else
189# define IS_IA32_PROCESS(regs) 0
190struct task_struct;
191static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
192static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
193#endif
194
195/*
196 * Context switch from one thread to another. If the two threads have
197 * different address spaces, schedule() has already taken care of
198 * switching to the new address space by calling switch_mm().
199 *
200 * Disabling access to the fph partition and the debug-register
201 * context switch MUST be done before calling ia64_switch_to() since a
202 * newly created thread returns directly to
203 * ia64_ret_from_syscall_clear_r8.
204 */
205extern struct task_struct *ia64_switch_to (void *next_task);
206
207struct task_struct;
208
209extern void ia64_save_extra (struct task_struct *task);
210extern void ia64_load_extra (struct task_struct *task);
211
212#ifdef CONFIG_PERFMON
213 DECLARE_PER_CPU(unsigned long, pfm_syst_info);
214# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
215#else
216# define PERFMON_IS_SYSWIDE() (0)
217#endif
218
219#define IA64_HAS_EXTRA_STATE(t) \
220 ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
Al Viro64505782006-01-12 01:06:06 -0800221 || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222
223#define __switch_to(prev,next,last) do { \
224 if (IA64_HAS_EXTRA_STATE(prev)) \
225 ia64_save_extra(prev); \
226 if (IA64_HAS_EXTRA_STATE(next)) \
227 ia64_load_extra(next); \
Al Viro64505782006-01-12 01:06:06 -0800228 ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 (last) = ia64_switch_to((next)); \
230} while (0)
231
232#ifdef CONFIG_SMP
233/*
234 * In the SMP case, we save the fph state when context-switching away from a thread that
235 * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
236 * pick up the state from task->thread.fph, avoiding the complication of having to fetch
237 * the latest fph state from another CPU. In other words: eager save, lazy restore.
238 */
239# define switch_to(prev,next,last) do { \
Al Viro64505782006-01-12 01:06:06 -0800240 if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
241 ia64_psr(task_pt_regs(prev))->mfh = 0; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
243 __ia64_save_fpu((prev)->thread.fph); \
244 } \
245 __switch_to(prev, next, last); \
Brent Casavante08e6c52006-01-26 15:55:52 -0800246 /* "next" in old context is "current" in new context */ \
247 if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
248 (task_cpu(current) != \
249 task_thread_info(current)->last_cpu))) { \
250 platform_migrate(current); \
251 task_thread_info(current)->last_cpu = task_cpu(current); \
252 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253} while (0)
254#else
255# define switch_to(prev,next,last) __switch_to(prev, next, last)
256#endif
257
Nick Piggin4866cde2005-06-25 14:57:23 -0700258#define __ARCH_WANT_UNLOCKED_CTXSW
Chen, Kenneth W383f2832005-09-09 13:02:02 -0700259#define ARCH_HAS_PREFETCH_SWITCH_STACK
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
261
262void cpu_idle_wait(void);
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -0800263void sched_cacheflush(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265#define arch_align_stack(x) (x)
266
Adrian Bunkcdb04522006-03-24 03:15:57 -0800267void default_idle(void);
268
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269#endif /* __KERNEL__ */
270
271#endif /* __ASSEMBLY__ */
272
273#endif /* _ASM_IA64_SYSTEM_H */