Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/boot/nspire.dtsi |
| 3 | * |
| 4 | * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2, as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | /include/ "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | interrupt-parent = <&intc>; |
| 16 | |
| 17 | cpus { |
| 18 | cpu@0 { |
| 19 | compatible = "arm,arm926ejs"; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | bootrom: bootrom@00000000 { |
| 24 | reg = <0x00000000 0x80000>; |
| 25 | }; |
| 26 | |
| 27 | sram: sram@A4000000 { |
| 28 | device = "memory"; |
| 29 | reg = <0xA4000000 0x20000>; |
| 30 | }; |
| 31 | |
| 32 | timer_clk: timer_clk { |
| 33 | #clock-cells = <0>; |
| 34 | compatible = "fixed-clock"; |
| 35 | clock-frequency = <32768>; |
| 36 | }; |
| 37 | |
| 38 | base_clk: base_clk { |
| 39 | #clock-cells = <0>; |
| 40 | reg = <0x900B0024 0x4>; |
| 41 | }; |
| 42 | |
| 43 | ahb_clk: ahb_clk { |
| 44 | #clock-cells = <0>; |
| 45 | reg = <0x900B0024 0x4>; |
| 46 | clocks = <&base_clk>; |
| 47 | }; |
| 48 | |
| 49 | apb_pclk: apb_pclk { |
| 50 | #clock-cells = <0>; |
| 51 | compatible = "fixed-factor-clock"; |
| 52 | clock-div = <2>; |
| 53 | clock-mult = <1>; |
| 54 | clocks = <&ahb_clk>; |
| 55 | }; |
| 56 | |
Daniel Tang | 66c9270 | 2015-02-09 19:41:57 +1100 | [diff] [blame] | 57 | usb_phy: usb_phy { |
| 58 | compatible = "usb-nop-xceiv"; |
| 59 | }; |
| 60 | |
| 61 | vbus_reg: vbus_reg { |
| 62 | compatible = "regulator-fixed"; |
| 63 | |
| 64 | regulator-name = "USB VBUS output"; |
| 65 | regulator-type = "voltage"; |
| 66 | |
| 67 | regulator-min-microvolt = <5000000>; |
| 68 | regulator-max-microvolt = <5000000>; |
| 69 | }; |
| 70 | |
Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 71 | ahb { |
| 72 | compatible = "simple-bus"; |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <1>; |
| 75 | ranges; |
| 76 | |
| 77 | spi: spi@A9000000 { |
| 78 | reg = <0xA9000000 0x1000>; |
| 79 | }; |
| 80 | |
| 81 | usb0: usb@B0000000 { |
Daniel Tang | 66c9270 | 2015-02-09 19:41:57 +1100 | [diff] [blame] | 82 | compatible = "lsi,zevio-usb"; |
Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 83 | reg = <0xB0000000 0x1000>; |
| 84 | interrupts = <8>; |
Daniel Tang | 66c9270 | 2015-02-09 19:41:57 +1100 | [diff] [blame] | 85 | |
| 86 | usb-phy = <&usb_phy>; |
| 87 | vbus-supply = <&vbus_reg>; |
Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | usb1: usb@B4000000 { |
| 91 | reg = <0xB4000000 0x1000>; |
| 92 | interrupts = <9>; |
| 93 | status = "disabled"; |
| 94 | }; |
| 95 | |
| 96 | lcd: lcd@C0000000 { |
| 97 | compatible = "arm,pl111", "arm,primecell"; |
| 98 | reg = <0xC0000000 0x1000>; |
| 99 | interrupts = <21>; |
| 100 | |
| 101 | clocks = <&apb_pclk>; |
| 102 | clock-names = "apb_pclk"; |
| 103 | }; |
| 104 | |
| 105 | adc: adc@C4000000 { |
| 106 | reg = <0xC4000000 0x1000>; |
| 107 | interrupts = <11>; |
| 108 | }; |
| 109 | |
| 110 | tdes: crypto@C8010000 { |
| 111 | reg = <0xC8010000 0x1000>; |
| 112 | }; |
| 113 | |
| 114 | sha256: crypto@CC000000 { |
| 115 | reg = <0xCC000000 0x1000>; |
| 116 | }; |
| 117 | |
| 118 | apb@90000000 { |
| 119 | compatible = "simple-bus"; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <1>; |
| 122 | clock-ranges; |
| 123 | ranges; |
| 124 | |
| 125 | gpio: gpio@90000000 { |
Daniel Tang | 66c9270 | 2015-02-09 19:41:57 +1100 | [diff] [blame] | 126 | compatible = "lsi,zevio-gpio"; |
Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 127 | reg = <0x90000000 0x1000>; |
| 128 | interrupts = <7>; |
Daniel Tang | 66c9270 | 2015-02-09 19:41:57 +1100 | [diff] [blame] | 129 | gpio-controller; |
| 130 | #gpio-cells = <2>; |
Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | fast_timer: timer@90010000 { |
| 134 | reg = <0x90010000 0x1000>; |
| 135 | interrupts = <17>; |
| 136 | }; |
| 137 | |
| 138 | uart: serial@90020000 { |
| 139 | reg = <0x90020000 0x1000>; |
| 140 | interrupts = <1>; |
| 141 | }; |
| 142 | |
| 143 | timer0: timer@900C0000 { |
| 144 | reg = <0x900C0000 0x1000>; |
| 145 | |
| 146 | clocks = <&timer_clk>; |
| 147 | }; |
| 148 | |
| 149 | timer1: timer@900D0000 { |
| 150 | reg = <0x900D0000 0x1000>; |
| 151 | interrupts = <19>; |
| 152 | |
| 153 | clocks = <&timer_clk>; |
| 154 | }; |
| 155 | |
| 156 | watchdog: watchdog@90060000 { |
| 157 | compatible = "arm,amba-primecell"; |
| 158 | reg = <0x90060000 0x1000>; |
| 159 | interrupts = <3>; |
| 160 | }; |
| 161 | |
| 162 | rtc: rtc@90090000 { |
| 163 | reg = <0x90090000 0x1000>; |
| 164 | interrupts = <4>; |
| 165 | }; |
| 166 | |
| 167 | misc: misc@900A0000 { |
| 168 | reg = <0x900A0000 0x1000>; |
| 169 | }; |
| 170 | |
| 171 | pwr: pwr@900B0000 { |
| 172 | reg = <0x900B0000 0x1000>; |
| 173 | interrupts = <15>; |
| 174 | }; |
| 175 | |
| 176 | keypad: input@900E0000 { |
| 177 | compatible = "ti,nspire-keypad"; |
| 178 | reg = <0x900E0000 0x1000>; |
| 179 | interrupts = <16>; |
| 180 | |
| 181 | scan-interval = <1000>; |
| 182 | row-delay = <200>; |
| 183 | |
| 184 | clocks = <&apb_pclk>; |
| 185 | }; |
| 186 | |
| 187 | contrast: contrast@900F0000 { |
| 188 | reg = <0x900F0000 0x1000>; |
| 189 | }; |
| 190 | |
| 191 | led: led@90110000 { |
| 192 | reg = <0x90110000 0x1000>; |
| 193 | }; |
| 194 | }; |
| 195 | }; |
| 196 | }; |