Icenowy Zheng | 838adb5 | 2017-01-26 23:48:51 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Allwinner H5 SoC pinctrl driver. |
| 3 | * |
| 4 | * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
| 5 | * |
| 6 | * Based on pinctrl-sun8i-h3.c, which is: |
| 7 | * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> |
| 8 | * |
| 9 | * Based on pinctrl-sun8i-a23.c, which is: |
| 10 | * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> |
| 11 | * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> |
| 12 | * |
| 13 | * This file is licensed under the terms of the GNU General Public |
| 14 | * License version 2. This program is licensed "as is" without any |
| 15 | * warranty of any kind, whether express or implied. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/pinctrl/pinctrl.h> |
| 23 | |
| 24 | #include "pinctrl-sunxi.h" |
| 25 | |
| 26 | static const struct sunxi_desc_pin sun50i_h5_pins[] = { |
| 27 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), |
| 28 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 29 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 30 | SUNXI_FUNCTION(0x2, "uart2"), /* TX */ |
| 31 | SUNXI_FUNCTION(0x3, "jtag"), /* MS */ |
| 32 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ |
| 33 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), |
| 34 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 35 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 36 | SUNXI_FUNCTION(0x2, "uart2"), /* RX */ |
| 37 | SUNXI_FUNCTION(0x3, "jtag"), /* CK */ |
| 38 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ |
| 39 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), |
| 40 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 41 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 42 | SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ |
| 43 | SUNXI_FUNCTION(0x3, "jtag"), /* DO */ |
| 44 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ |
| 45 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), |
| 46 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 47 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 48 | SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ |
| 49 | SUNXI_FUNCTION(0x3, "jtag"), /* DI */ |
| 50 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ |
| 51 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), |
| 52 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 53 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 54 | SUNXI_FUNCTION(0x2, "uart0"), /* TX */ |
| 55 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ |
| 56 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), |
| 57 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 58 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 59 | SUNXI_FUNCTION(0x2, "uart0"), /* RX */ |
| 60 | SUNXI_FUNCTION(0x3, "pwm0"), |
| 61 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ |
| 62 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), |
| 63 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 64 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 65 | SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ |
| 66 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ |
| 67 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), |
| 68 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 69 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 70 | SUNXI_FUNCTION(0x2, "sim"), /* CLK */ |
| 71 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ |
| 72 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), |
| 73 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 74 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 75 | SUNXI_FUNCTION(0x2, "sim"), /* DATA */ |
| 76 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ |
| 77 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), |
| 78 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 79 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 80 | SUNXI_FUNCTION(0x2, "sim"), /* RST */ |
| 81 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ |
| 82 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), |
| 83 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 84 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 85 | SUNXI_FUNCTION(0x2, "sim"), /* DET */ |
| 86 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ |
| 87 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), |
| 88 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 89 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 90 | SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ |
| 91 | SUNXI_FUNCTION(0x3, "di"), /* TX */ |
| 92 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ |
| 93 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), |
| 94 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 95 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 96 | SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ |
| 97 | SUNXI_FUNCTION(0x3, "di"), /* RX */ |
| 98 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ |
| 99 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), |
| 100 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 101 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 102 | SUNXI_FUNCTION(0x2, "spi1"), /* CS */ |
| 103 | SUNXI_FUNCTION(0x3, "uart3"), /* TX */ |
| 104 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ |
| 105 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), |
| 106 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 107 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 108 | SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ |
| 109 | SUNXI_FUNCTION(0x3, "uart3"), /* RX */ |
| 110 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ |
| 111 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), |
| 112 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 113 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 114 | SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ |
| 115 | SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ |
| 116 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ |
| 117 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), |
| 118 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 119 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 120 | SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ |
| 121 | SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ |
| 122 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ |
| 123 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), |
| 124 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 125 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 126 | SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ |
| 127 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ |
| 128 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), |
| 129 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 130 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 131 | SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ |
| 132 | SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ |
| 133 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ |
| 134 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), |
| 135 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 136 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 137 | SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ |
| 138 | SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ |
| 139 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ |
| 140 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), |
| 141 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 142 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 143 | SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ |
| 144 | SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ |
| 145 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ |
| 146 | SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), |
| 147 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 148 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 149 | SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ |
| 150 | SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ |
| 151 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ |
| 152 | /* Hole */ |
| 153 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), |
| 154 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 155 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 156 | SUNXI_FUNCTION(0x2, "nand0"), /* WE */ |
| 157 | SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ |
| 158 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), |
| 159 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 160 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 161 | SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ |
| 162 | SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ |
| 163 | SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ |
| 164 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), |
| 165 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 166 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 167 | SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ |
| 168 | SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ |
| 169 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), |
| 170 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 171 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 172 | SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ |
| 173 | SUNXI_FUNCTION(0x3, "spi0")), /* CS */ |
| 174 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), |
| 175 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 176 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 177 | SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ |
| 178 | SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ |
| 179 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), |
| 180 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 181 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 182 | SUNXI_FUNCTION(0x2, "nand0"), /* RE */ |
| 183 | SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ |
| 184 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), |
| 185 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 186 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 187 | SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ |
| 188 | SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ |
| 189 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), |
| 190 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 191 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 192 | SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ |
| 193 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), |
| 194 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 195 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 196 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ |
| 197 | SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ |
| 198 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), |
| 199 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 200 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 201 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ |
| 202 | SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ |
| 203 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), |
| 204 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 205 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 206 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ |
| 207 | SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ |
| 208 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), |
| 209 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 210 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 211 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ |
| 212 | SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ |
| 213 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), |
| 214 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 215 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 216 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ |
| 217 | SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ |
| 218 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), |
| 219 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 220 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 221 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ |
| 222 | SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ |
| 223 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
| 224 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 225 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 226 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ |
| 227 | SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ |
| 228 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
| 229 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 230 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 231 | SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ |
| 232 | SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ |
| 233 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
| 234 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 235 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 236 | SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ |
| 237 | SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ |
| 238 | /* Hole */ |
| 239 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), |
| 240 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 241 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 242 | SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ |
| 243 | SUNXI_FUNCTION(0x3, "di"), /* TX */ |
| 244 | SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ |
| 245 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), |
| 246 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 247 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 248 | SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ |
| 249 | SUNXI_FUNCTION(0x3, "di"), /* RX */ |
| 250 | SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ |
| 251 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
| 252 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 253 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 254 | SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ |
| 255 | SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ |
| 256 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), |
| 257 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 258 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 259 | SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ |
| 260 | SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ |
| 261 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), |
| 262 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 263 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 264 | SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ |
| 265 | SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ |
| 266 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), |
| 267 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 268 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 269 | SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ |
| 270 | SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ |
| 271 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), |
| 272 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 273 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 274 | SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ |
| 275 | SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ |
| 276 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), |
| 277 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 278 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 279 | SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ |
| 280 | SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ |
| 281 | SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ |
| 282 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), |
| 283 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 284 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 285 | SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ |
| 286 | SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ |
| 287 | SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ |
| 288 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), |
| 289 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 290 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 291 | SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ |
| 292 | SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ |
| 293 | SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ |
| 294 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), |
| 295 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 296 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 297 | SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ |
| 298 | SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ |
| 299 | SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ |
| 300 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), |
| 301 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 302 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 303 | SUNXI_FUNCTION(0x2, "emac"), /* CRS */ |
| 304 | SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ |
| 305 | SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ |
| 306 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), |
| 307 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 308 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 309 | SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ |
| 310 | SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ |
| 311 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), |
| 312 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 313 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 314 | SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ |
| 315 | SUNXI_FUNCTION(0x4, "sim")), /* CLK */ |
| 316 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), |
| 317 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 318 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 319 | SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ |
| 320 | SUNXI_FUNCTION(0x4, "sim")), /* DATA */ |
| 321 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), |
| 322 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 323 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 324 | SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ |
| 325 | SUNXI_FUNCTION(0x4, "sim")), /* RST */ |
| 326 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), |
| 327 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 328 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 329 | SUNXI_FUNCTION(0x2, "emac"), /* MDC */ |
| 330 | SUNXI_FUNCTION(0x4, "sim")), /* DET */ |
| 331 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), |
| 332 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 333 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 334 | SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ |
| 335 | /* Hole */ |
| 336 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), |
| 337 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 338 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 339 | SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ |
| 340 | SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ |
| 341 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), |
| 342 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 343 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 344 | SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ |
| 345 | SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ |
| 346 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), |
| 347 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 348 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 349 | SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ |
| 350 | SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ |
| 351 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), |
| 352 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 353 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 354 | SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ |
| 355 | SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ |
| 356 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), |
| 357 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 358 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 359 | SUNXI_FUNCTION(0x2, "csi"), /* D0 */ |
| 360 | SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ |
| 361 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), |
| 362 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 363 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 364 | SUNXI_FUNCTION(0x2, "csi"), /* D1 */ |
| 365 | SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ |
| 366 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), |
| 367 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 368 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 369 | SUNXI_FUNCTION(0x2, "csi"), /* D2 */ |
| 370 | SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ |
| 371 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), |
| 372 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 373 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 374 | SUNXI_FUNCTION(0x2, "csi"), /* D3 */ |
| 375 | SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ |
| 376 | SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ |
| 377 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), |
| 378 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 379 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 380 | SUNXI_FUNCTION(0x2, "csi"), /* D4 */ |
| 381 | SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ |
| 382 | SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ |
| 383 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), |
| 384 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 385 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 386 | SUNXI_FUNCTION(0x2, "csi"), /* D5 */ |
| 387 | SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ |
| 388 | SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ |
| 389 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), |
| 390 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 391 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 392 | SUNXI_FUNCTION(0x2, "csi"), /* D6 */ |
| 393 | SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ |
| 394 | SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ |
| 395 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), |
| 396 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 397 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 398 | SUNXI_FUNCTION(0x2, "csi"), /* D7 */ |
| 399 | SUNXI_FUNCTION(0x3, "ts"), /* D7 */ |
| 400 | SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ |
| 401 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), |
| 402 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 403 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 404 | SUNXI_FUNCTION(0x2, "csi"), /* SCK */ |
| 405 | SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ |
| 406 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), |
| 407 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 408 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 409 | SUNXI_FUNCTION(0x2, "csi"), /* SDA */ |
| 410 | SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ |
| 411 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), |
| 412 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 413 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 414 | SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ |
| 415 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), |
| 416 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 417 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 418 | SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ |
| 419 | /* Hole */ |
| 420 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), |
| 421 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 422 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 423 | SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ |
| 424 | SUNXI_FUNCTION(0x3, "jtag"), /* MS */ |
| 425 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ |
| 426 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), |
| 427 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 428 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 429 | SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ |
| 430 | SUNXI_FUNCTION(0x3, "jtag"), /* DI */ |
| 431 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ |
| 432 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), |
| 433 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 434 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 435 | SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ |
| 436 | SUNXI_FUNCTION(0x3, "uart0"), /* TX */ |
| 437 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ |
| 438 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), |
| 439 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 440 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 441 | SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ |
| 442 | SUNXI_FUNCTION(0x3, "jtag"), /* DO */ |
| 443 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ |
| 444 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), |
| 445 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 446 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 447 | SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ |
| 448 | SUNXI_FUNCTION(0x3, "uart0"), /* RX */ |
| 449 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ |
| 450 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), |
| 451 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 452 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 453 | SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ |
| 454 | SUNXI_FUNCTION(0x3, "jtag"), /* CK */ |
| 455 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ |
| 456 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), |
| 457 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 458 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 459 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ |
| 460 | /* Hole */ |
| 461 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), |
| 462 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 463 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 464 | SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ |
| 465 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ |
| 466 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), |
| 467 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 468 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 469 | SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ |
| 470 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ |
| 471 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), |
| 472 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 473 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 474 | SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ |
| 475 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ |
| 476 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), |
| 477 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 478 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 479 | SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ |
| 480 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ |
| 481 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), |
| 482 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 483 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 484 | SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ |
| 485 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ |
| 486 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), |
| 487 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 488 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 489 | SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ |
| 490 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ |
| 491 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), |
| 492 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 493 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 494 | SUNXI_FUNCTION(0x2, "uart1"), /* TX */ |
| 495 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ |
| 496 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), |
| 497 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 498 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 499 | SUNXI_FUNCTION(0x2, "uart1"), /* RX */ |
| 500 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ |
| 501 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), |
| 502 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 503 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 504 | SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ |
| 505 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ |
| 506 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), |
| 507 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 508 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 509 | SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ |
| 510 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ |
| 511 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), |
| 512 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 513 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 514 | SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ |
| 515 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ |
| 516 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), |
| 517 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 518 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 519 | SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ |
| 520 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ |
| 521 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), |
| 522 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 523 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 524 | SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ |
| 525 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ |
| 526 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), |
| 527 | SUNXI_FUNCTION(0x0, "gpio_in"), |
| 528 | SUNXI_FUNCTION(0x1, "gpio_out"), |
| 529 | SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ |
| 530 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ |
| 531 | }; |
| 532 | |
| 533 | static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { |
| 534 | .pins = sun50i_h5_pins, |
| 535 | .npins = ARRAY_SIZE(sun50i_h5_pins), |
| 536 | .irq_banks = 2, |
| 537 | .irq_read_needs_mux = true |
| 538 | }; |
| 539 | |
| 540 | static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) |
| 541 | { |
| 542 | return sunxi_pinctrl_init(pdev, |
| 543 | &sun50i_h5_pinctrl_data); |
| 544 | } |
| 545 | |
| 546 | static const struct of_device_id sun50i_h5_pinctrl_match[] = { |
| 547 | { .compatible = "allwinner,sun50i-h5-pinctrl", }, |
| 548 | {} |
| 549 | }; |
| 550 | |
| 551 | static struct platform_driver sun50i_h5_pinctrl_driver = { |
| 552 | .probe = sun50i_h5_pinctrl_probe, |
| 553 | .driver = { |
| 554 | .name = "sun50i-h5-pinctrl", |
| 555 | .of_match_table = sun50i_h5_pinctrl_match, |
| 556 | }, |
| 557 | }; |
| 558 | builtin_platform_driver(sun50i_h5_pinctrl_driver); |