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Paul Walmsleyad67ef62008-08-19 11:08:40 +03001/*
2 * OMAP2/3 powerdomain control
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
22#include <mach/cpu.h>
23
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
31/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON))
34
35#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_RET))
37
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
39
40
41/*
42 * Number of memory banks that are power-controllable. On OMAP3430, the
43 * maximum is 4.
44 */
45#define PWRDM_MAX_MEM_BANKS 4
46
Paul Walmsley8420bb12008-08-19 11:08:44 +030047/*
48 * Maximum number of clockdomains that can be associated with a powerdomain.
49 * CORE powerdomain is probably the worst case.
50 */
51#define PWRDM_MAX_CLKDMS 3
52
Paul Walmsleyad67ef62008-08-19 11:08:40 +030053/* XXX A completely arbitrary number. What is reasonable here? */
54#define PWRDM_TRANSITION_BAILOUT 100000
55
Paul Walmsley8420bb12008-08-19 11:08:44 +030056struct clockdomain;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030057struct powerdomain;
58
59/* Encodes dependencies between powerdomains - statically defined */
60struct pwrdm_dep {
61
62 /* Powerdomain name */
63 const char *pwrdm_name;
64
65 /* Powerdomain pointer - resolved by the powerdomain code */
66 struct powerdomain *pwrdm;
67
68 /* Flags to mark OMAP chip restrictions, etc. */
69 const struct omap_chip_id omap_chip;
70
71};
72
73struct powerdomain {
74
75 /* Powerdomain name */
76 const char *name;
77
78 /* the address offset from CM_BASE/PRM_BASE */
79 const s16 prcm_offs;
80
81 /* Used to represent the OMAP chip types containing this pwrdm */
82 const struct omap_chip_id omap_chip;
83
84 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
85 const u8 dep_bit;
86
87 /* Powerdomains that can be told to wake this powerdomain up */
88 struct pwrdm_dep *wkdep_srcs;
89
90 /* Powerdomains that can be told to keep this pwrdm from inactivity */
91 struct pwrdm_dep *sleepdep_srcs;
92
93 /* Possible powerdomain power states */
94 const u8 pwrsts;
95
96 /* Possible logic power states when pwrdm in RETENTION */
97 const u8 pwrsts_logic_ret;
98
99 /* Number of software-controllable memory banks in this powerdomain */
100 const u8 banks;
101
102 /* Possible memory bank pwrstates when pwrdm in RETENTION */
103 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
104
105 /* Possible memory bank pwrstates when pwrdm is ON */
106 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
107
Paul Walmsley8420bb12008-08-19 11:08:44 +0300108 /* Clockdomains in this powerdomain */
109 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
110
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300111 struct list_head node;
112
113};
114
115
116void pwrdm_init(struct powerdomain **pwrdm_list);
117
118int pwrdm_register(struct powerdomain *pwrdm);
119int pwrdm_unregister(struct powerdomain *pwrdm);
120struct powerdomain *pwrdm_lookup(const char *name);
121
122int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
123
Paul Walmsley8420bb12008-08-19 11:08:44 +0300124int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
125int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
126int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
127 int (*fn)(struct powerdomain *pwrdm,
128 struct clockdomain *clkdm));
129
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300130int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
131int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
132int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
133int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
134int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
135int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
136
137int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
138
139int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
140int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
141int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
142int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
143
144int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
145int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
146int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
147
148int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
149int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
150int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
151int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
152
153int pwrdm_wait_transition(struct powerdomain *pwrdm);
154
155#endif