Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014-2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "intel_drv.h" |
| 25 | |
| 26 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
| 27 | u32 deemph_reg_value, u32 margin_reg_value, |
| 28 | bool uniq_trans_scale) |
| 29 | { |
| 30 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 31 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 32 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
| 33 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 34 | enum pipe pipe = intel_crtc->pipe; |
| 35 | u32 val; |
| 36 | int i; |
| 37 | |
| 38 | mutex_lock(&dev_priv->sb_lock); |
| 39 | |
| 40 | /* Clear calc init */ |
| 41 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 42 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 43 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 44 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 45 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 46 | |
| 47 | if (intel_crtc->config->lane_count > 2) { |
| 48 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 49 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 50 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 51 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 52 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 53 | } |
| 54 | |
| 55 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
| 56 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 57 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 58 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
| 59 | |
| 60 | if (intel_crtc->config->lane_count > 2) { |
| 61 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
| 62 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 63 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 64 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
| 65 | } |
| 66 | |
| 67 | /* Program swing deemph */ |
| 68 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 69 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
| 70 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
| 71 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
| 72 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
| 73 | } |
| 74 | |
| 75 | /* Program swing margin */ |
| 76 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 77 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
| 78 | |
| 79 | val &= ~DPIO_SWING_MARGIN000_MASK; |
| 80 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
| 81 | |
| 82 | /* |
| 83 | * Supposedly this value shouldn't matter when unique transition |
| 84 | * scale is disabled, but in fact it does matter. Let's just |
| 85 | * always program the same value and hope it's OK. |
| 86 | */ |
| 87 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 88 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
| 89 | |
| 90 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * The document said it needs to set bit 27 for ch0 and bit 26 |
| 95 | * for ch1. Might be a typo in the doc. |
| 96 | * For now, for this unique transition scale selection, set bit |
| 97 | * 27 for ch0 and ch1. |
| 98 | */ |
| 99 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 100 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
| 101 | if (uniq_trans_scale) |
| 102 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 103 | else |
| 104 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 105 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
| 106 | } |
| 107 | |
| 108 | /* Start swing calculation */ |
| 109 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 110 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 111 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 112 | |
| 113 | if (intel_crtc->config->lane_count > 2) { |
| 114 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 115 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 116 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 117 | } |
| 118 | |
| 119 | mutex_unlock(&dev_priv->sb_lock); |
| 120 | |
| 121 | } |
| 122 | |
Ander Conselvan de Oliveira | 844b2f9 | 2016-04-27 15:44:18 +0300 | [diff] [blame^] | 123 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
| 124 | bool reset) |
| 125 | { |
| 126 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 127 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
| 128 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 129 | enum pipe pipe = crtc->pipe; |
| 130 | uint32_t val; |
| 131 | |
| 132 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
| 133 | if (reset) |
| 134 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 135 | else |
| 136 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 137 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
| 138 | |
| 139 | if (crtc->config->lane_count > 2) { |
| 140 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
| 141 | if (reset) |
| 142 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 143 | else |
| 144 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 145 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
| 146 | } |
| 147 | |
| 148 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
| 149 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 150 | if (reset) |
| 151 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 152 | else |
| 153 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 154 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
| 155 | |
| 156 | if (crtc->config->lane_count > 2) { |
| 157 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
| 158 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 159 | if (reset) |
| 160 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 161 | else |
| 162 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 163 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
| 164 | } |
| 165 | } |