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gerrit-public.fairphone.software / kernel / msm-4.19 / 859deea949c382d9ccb6397fe33df3703ecef45d / . / include / asm-powerpc / cputable.h
blob: a9a40149a7c0daf66cca975035b4d5863bbc10bc [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb0212006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]26#define PPC_FEATURE_PA6T 0x00000800
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]27
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]28#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001
30
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]31#ifdef __KERNEL__
32#ifndef __ASSEMBLY__
33
34/* This structure can grow, it's real size is used by head.S code
35 * via the mkdefs mechanism.
36 */
37struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]39typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]40typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]41
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]42enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]43 PPC_OPROFILE_INVALID = 0,
44 PPC_OPROFILE_RS64 = 1,
45 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_G4 = 3,
47 PPC_OPROFILE_BOOKE = 4,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]48};
49
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]50struct cpu_spec {
51 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
52 unsigned int pvr_mask;
53 unsigned int pvr_value;
54
55 char *cpu_name;
56 unsigned long cpu_features; /* Kernel features */
57 unsigned int cpu_user_features; /* Userland features */
58
59 /* cache line sizes */
60 unsigned int icache_bsize;
61 unsigned int dcache_bsize;
62
63 /* number of performance monitor counters */
64 unsigned int num_pmcs;
65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]77 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]78
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]88};
89
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]90extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]92extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
93
94extern struct cpu_spec *identify_cpu(unsigned long offset);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]95extern void do_feature_fixups(unsigned long value, void *fixup_start,
96 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]97
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]98#endif /* __ASSEMBLY__ */
99
100/* CPU kernel features */
101
102/* Retain the 32b definitions all use bottom half of word */
103#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
104#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
105#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
106#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
107#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
108#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
109#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
110#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
111#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
112#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
113#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
114#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
115#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
116#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
117#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
118#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
119#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
120#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
121#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
122#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]123#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]124#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
125#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]126
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]127/*
128 * Add the 64-bit processor unique features in the top half of the word;
129 * on 32-bit, make the names available but defined to be 0.
130 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]131#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]132#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]133#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]134#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]135#endif
136
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]137#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
138#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
139#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
140#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
141#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
142#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
143#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
144#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
145#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
146#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
147#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
148#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
149#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame^]150#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]151
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]152#ifndef __ASSEMBLY__
153
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]154#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
155 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]156 CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]157
158/* iSeries doesn't support large pages */
159#ifdef CONFIG_PPC_ISERIES
160#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
161#else
162#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
163#endif /* CONFIG_PPC_ISERIES */
164
165/* We only set the altivec features if the kernel was compiled with altivec
166 * support
167 */
168#ifdef CONFIG_ALTIVEC
169#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
170#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
171#else
172#define CPU_FTR_ALTIVEC_COMP 0
173#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
174#endif
175
176/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]177 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
178 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]179 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]180#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
181 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]182#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
183#else
184#define CPU_FTR_COMMON 0
185#endif
186
187/* The powersave features NAP & DOZE seems to confuse BDI when
188 debugging. So if a BDI is used, disable theses
189 */
190#ifndef CONFIG_BDI_SWITCH
191#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
192#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
193#else
194#define CPU_FTR_MAYBE_CAN_DOZE 0
195#define CPU_FTR_MAYBE_CAN_NAP 0
196#endif
197
198#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
199 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
200 !defined(CONFIG_BOOKE))
201
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]202#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
203#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
204 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]205 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]206#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]207 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
208 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]209#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]211 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]212#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]214 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]216#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]218 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
219 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]220#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
221 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
222 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]223 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]224#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
225 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
226 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]227 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]228#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
229 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
230 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]231 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]232#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
233 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
234 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]235 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]236#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
237 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
238 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]239 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]240#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
241 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
242 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]244#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
245 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
246 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]247 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]248#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
249 CPU_FTR_USE_TB | \
250 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
251 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
252 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]253 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]254#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255 CPU_FTR_USE_TB | \
256 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
257 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]258 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]259#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
260 CPU_FTR_USE_TB | \
261 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
262 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]263 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]264#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
265 CPU_FTR_USE_TB | \
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
267 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]269 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]270#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
271 CPU_FTR_USE_TB | \
272 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
273 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
274 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]275 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]276#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
277 CPU_FTR_USE_TB | \
278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
279 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
280 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]281 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]282#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
283 CPU_FTR_USE_TB | \
284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
285 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
286 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]287 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]288#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
289 CPU_FTR_USE_TB | \
290 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
291 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
292 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]294#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
296#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
297 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
298#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
299 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
300 CPU_FTR_COMMON)
301#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
302 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]303#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
304#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
305 CPU_FTR_NODSISRALIGN)
306#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
307 CPU_FTR_NODSISRALIGN)
308#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
309#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
310 CPU_FTR_NODSISRALIGN)
311#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
312 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
313#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]314#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]315#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]316 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]317#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
318 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
319 CPU_FTR_MMCRA | CPU_FTR_CTRL)
320#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]321 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
322 CPU_FTR_MMCRA)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]323#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]324 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]325 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
326#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]327 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]328 CPU_FTR_MMCRA | CPU_FTR_SMT | \
329 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]330 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]331#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]332 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]333 CPU_FTR_MMCRA | CPU_FTR_SMT | \
334 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]335 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]336#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]337 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]338 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame^]339 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]340#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
342 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
343 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]344#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]346#endif
347
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]348#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]349#define CPU_FTRS_POSSIBLE \
350 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]351 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]352 CPU_FTRS_CELL | CPU_FTRS_PA6T)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]353#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]354enum {
355 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]356#if CLASSIC_PPC
357 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
358 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
359 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
360 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
361 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
362 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
363 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
364 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
365#else
366 CPU_FTRS_GENERIC_32 |
367#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]368#ifdef CONFIG_8xx
369 CPU_FTRS_8XX |
370#endif
371#ifdef CONFIG_40x
372 CPU_FTRS_40X |
373#endif
374#ifdef CONFIG_44x
375 CPU_FTRS_44X |
376#endif
377#ifdef CONFIG_E200
378 CPU_FTRS_E200 |
379#endif
380#ifdef CONFIG_E500
381 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
382#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]383 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]384};
385#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]386
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]387#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]388#define CPU_FTRS_ALWAYS \
389 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]390 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]391 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]392#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]393enum {
394 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]395#if CLASSIC_PPC
396 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
397 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
398 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
399 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
400 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
401 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
402 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
403 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
404#else
405 CPU_FTRS_GENERIC_32 &
406#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]407#ifdef CONFIG_8xx
408 CPU_FTRS_8XX &
409#endif
410#ifdef CONFIG_40x
411 CPU_FTRS_40X &
412#endif
413#ifdef CONFIG_44x
414 CPU_FTRS_44X &
415#endif
416#ifdef CONFIG_E200
417 CPU_FTRS_E200 &
418#endif
419#ifdef CONFIG_E500
420 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
421#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]422 CPU_FTRS_POSSIBLE,
423};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]424#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]425
426static inline int cpu_has_feature(unsigned long feature)
427{
428 return (CPU_FTRS_ALWAYS & feature) ||
429 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]430 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]431 & feature);
432}
433
434#endif /* !__ASSEMBLY__ */
435
436#ifdef __ASSEMBLY__
437
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]438#define BEGIN_FTR_SECTION_NESTED(label) label:
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]439#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]440#define END_FTR_SECTION_NESTED(msk, val, label) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]441 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]442#define END_FTR_SECTION(msk, val) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]443 END_FTR_SECTION_NESTED(msk, val, 97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]444
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]445#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
446#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
447#endif /* __ASSEMBLY__ */
448
449#endif /* __KERNEL__ */
450#endif /* __ASM_POWERPC_CPUTABLE_H */