blob: 84aea549de5df1689d507ab0cf1525d491fda5fe [file] [log] [blame]
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
Brad Volkin44e895a2014-05-10 14:10:43 -07004#include <linux/hashtable.h>
Chris Wilson06fbca72015-04-07 16:20:36 +01005#include "i915_gem_batch_pool.h"
Chris Wilsondcff85c2016-08-05 10:14:11 +01006#include "i915_gem_request.h"
Brad Volkin44e895a2014-05-10 14:10:43 -07007
8#define I915_CMD_HASH_ORDER 9
9
Oscar Mateo47122742014-07-24 17:04:28 +010010/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
11 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
12 * to give some inclination as to some of the magic values used in the various
13 * workarounds!
14 */
15#define CACHELINE_BYTES 64
Arun Siluvery17ee9502015-06-19 19:07:01 +010016#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
Oscar Mateo47122742014-07-24 17:04:28 +010017
Ville Syrjälä633cf8f2012-12-03 18:43:32 +020018/*
19 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
20 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
21 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
22 *
23 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
24 * cacheline, the Head Pointer must not be greater than the Tail
25 * Pointer."
26 */
27#define I915_RING_FREE_SPACE 64
28
Chris Wilson57e88532016-08-15 10:48:57 +010029struct intel_hw_status_page {
30 struct i915_vma *vma;
31 u32 *page_addr;
32 u32 ggtt_offset;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080033};
34
Dave Gordonbbdc070a2016-07-20 18:16:05 +010035#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
36#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080037
Dave Gordonbbdc070a2016-07-20 18:16:05 +010038#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
39#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080040
Dave Gordonbbdc070a2016-07-20 18:16:05 +010041#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
42#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080043
Dave Gordonbbdc070a2016-07-20 18:16:05 +010044#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
45#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080046
Dave Gordonbbdc070a2016-07-20 18:16:05 +010047#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
48#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
Daniel Vetter870e86d2010-08-02 16:29:44 +020049
Dave Gordonbbdc070a2016-07-20 18:16:05 +010050#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
51#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +053052
Ben Widawsky3e789982014-06-30 09:53:37 -070053/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
54 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
55 */
Chris Wilson8c126722016-04-07 07:29:14 +010056#define gen8_semaphore_seqno_size sizeof(uint64_t)
57#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
58 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
Ben Widawsky3e789982014-06-30 09:53:37 -070059#define GEN8_SIGNAL_OFFSET(__ring, to) \
Chris Wilson51d545d2016-08-15 10:49:02 +010060 (dev_priv->semaphore->node.start + \
Chris Wilson8c126722016-04-07 07:29:14 +010061 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
Ben Widawsky3e789982014-06-30 09:53:37 -070062#define GEN8_WAIT_OFFSET(__ring, from) \
Chris Wilson51d545d2016-08-15 10:49:02 +010063 (dev_priv->semaphore->node.start + \
Chris Wilson8c126722016-04-07 07:29:14 +010064 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
Ben Widawsky3e789982014-06-30 09:53:37 -070065
Chris Wilson7e37f882016-08-02 22:50:21 +010066enum intel_engine_hangcheck_action {
Mika Kuoppalada661462013-09-06 16:03:28 +030067 HANGCHECK_IDLE = 0,
Jani Nikulaf2f4d822013-08-11 12:44:01 +030068 HANGCHECK_WAIT,
69 HANGCHECK_ACTIVE,
70 HANGCHECK_KICK,
71 HANGCHECK_HUNG,
72};
Mika Kuoppalaad8beae2013-06-12 12:35:32 +030073
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +020074#define HANGCHECK_SCORE_RING_HUNG 31
75
Chris Wilson7e37f882016-08-02 22:50:21 +010076struct intel_engine_hangcheck {
Chris Wilson50877442014-03-21 12:41:53 +000077 u64 acthd;
Mika Kuoppala92cab732013-05-24 17:16:07 +030078 u32 seqno;
Mika Kuoppala05407ff2013-05-30 09:04:29 +030079 int score;
Chris Wilson7e37f882016-08-02 22:50:21 +010080 enum intel_engine_hangcheck_action action;
Chris Wilson4be17382014-06-06 10:22:29 +010081 int deadlock;
Mika Kuoppala61642ff2015-12-01 17:56:12 +020082 u32 instdone[I915_NUM_INSTDONE_REG];
Mika Kuoppala92cab732013-05-24 17:16:07 +030083};
84
Chris Wilson7e37f882016-08-02 22:50:21 +010085struct intel_ring {
Tvrtko Ursulin0eb973d2016-01-15 15:10:28 +000086 struct i915_vma *vma;
Chris Wilson57e88532016-08-15 10:48:57 +010087 void *vaddr;
Oscar Mateo8ee14972014-05-22 14:13:34 +010088
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +000089 struct intel_engine_cs *engine;
Chris Wilson608c1a52015-09-03 13:01:40 +010090 struct list_head link;
Daniel Vetter0c7dd532014-08-11 16:17:44 +020091
Chris Wilson675d9ad2016-08-04 07:52:36 +010092 struct list_head request_list;
93
Oscar Mateo8ee14972014-05-22 14:13:34 +010094 u32 head;
95 u32 tail;
96 int space;
97 int size;
98 int effective_size;
99
100 /** We track the position of the requests in the ring buffer, and
101 * when each is retired we increment last_retired_head as the GPU
102 * must have finished processing the request and so we know we
103 * can advance the ringbuffer up to that position.
104 *
105 * last_retired_head is set to -1 after the value is consumed so
106 * we can detect new retirements.
107 */
108 u32 last_retired_head;
109};
110
Chris Wilsone2efd132016-05-24 14:53:34 +0100111struct i915_gem_context;
Jordan Justen361b0272016-03-06 23:30:27 -0800112struct drm_i915_reg_table;
Nick Hoath21076372015-01-15 13:10:38 +0000113
Arun Siluvery17ee9502015-06-19 19:07:01 +0100114/*
115 * we use a single page to load ctx workarounds so all of these
116 * values are referred in terms of dwords
117 *
118 * struct i915_wa_ctx_bb:
119 * offset: specifies batch starting position, also helpful in case
120 * if we want to have multiple batches at different offsets based on
121 * some criteria. It is not a requirement at the moment but provides
122 * an option for future use.
123 * size: size of the batch in DWORDS
124 */
Chris Wilson48bb74e2016-08-15 10:49:04 +0100125struct i915_ctx_workarounds {
Arun Siluvery17ee9502015-06-19 19:07:01 +0100126 struct i915_wa_ctx_bb {
127 u32 offset;
128 u32 size;
129 } indirect_ctx, per_ctx;
Chris Wilson48bb74e2016-08-15 10:49:04 +0100130 struct i915_vma *vma;
Arun Siluvery17ee9502015-06-19 19:07:01 +0100131};
132
Chris Wilsonc81d4612016-07-01 17:23:25 +0100133struct drm_i915_gem_request;
134
Chris Wilsonc0336662016-05-06 15:40:21 +0100135struct intel_engine_cs {
136 struct drm_i915_private *i915;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800137 const char *name;
Tvrtko Ursulin117897f2016-03-16 11:00:40 +0000138 enum intel_engine_id {
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000139 RCS = 0,
Daniel Vetter96154f22011-12-14 13:57:00 +0100140 BCS,
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000141 VCS,
142 VCS2, /* Keep instances of the same type engine together. */
143 VECS
Chris Wilson92204342010-09-18 11:02:01 +0100144 } id;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000145#define I915_NUM_ENGINES 5
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000146#define _VCS(n) (VCS + (n))
Chris Wilson426960b2016-01-15 16:51:46 +0000147 unsigned int exec_id;
Tvrtko Ursulin5ec2cf72016-08-16 17:04:20 +0100148 enum intel_engine_hw_id {
149 RCS_HW = 0,
150 VCS_HW,
151 BCS_HW,
152 VECS_HW,
153 VCS2_HW
154 } hw_id;
155 enum intel_engine_hw_id guc_id; /* XXX same as hw_id? */
Chris Wilson04769652016-07-20 09:21:11 +0100156 u64 fence_context;
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200157 u32 mmio_base;
Dave Gordonc2c7f242016-07-13 16:03:35 +0100158 unsigned int irq_shift;
Chris Wilson7e37f882016-08-02 22:50:21 +0100159 struct intel_ring *buffer;
Chris Wilson608c1a52015-09-03 13:01:40 +0100160 struct list_head buffers;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800161
Chris Wilson688e6c72016-07-01 17:23:15 +0100162 /* Rather than have every client wait upon all user interrupts,
163 * with the herd waking after every interrupt and each doing the
164 * heavyweight seqno dance, we delegate the task (of being the
165 * bottom-half of the user interrupt) to the first client. After
166 * every interrupt, we wake up one client, who does the heavyweight
167 * coherent seqno read and either goes back to sleep (if incomplete),
168 * or wakes up all the completed clients in parallel, before then
169 * transferring the bottom-half status to the next client in the queue.
170 *
171 * Compared to walking the entire list of waiters in a single dedicated
172 * bottom-half, we reduce the latency of the first waiter by avoiding
173 * a context switch, but incur additional coherent seqno reads when
174 * following the chain of request breadcrumbs. Since it is most likely
175 * that we have a single client waiting on each seqno, then reducing
176 * the overhead of waking that client is much preferred.
177 */
178 struct intel_breadcrumbs {
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100179 struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */
Chris Wilsonaca34b62016-07-06 12:39:02 +0100180 bool irq_posted;
181
Chris Wilson688e6c72016-07-01 17:23:15 +0100182 spinlock_t lock; /* protects the lists of requests */
183 struct rb_root waiters; /* sorted by retirement, priority */
Chris Wilsonc81d4612016-07-01 17:23:25 +0100184 struct rb_root signals; /* sorted by retirement */
Chris Wilson688e6c72016-07-01 17:23:15 +0100185 struct intel_wait *first_wait; /* oldest waiter by retirement */
Chris Wilsonc81d4612016-07-01 17:23:25 +0100186 struct task_struct *signaler; /* used for fence signalling */
Chris Wilsonb3850852016-07-01 17:23:26 +0100187 struct drm_i915_gem_request *first_signal;
Chris Wilson688e6c72016-07-01 17:23:15 +0100188 struct timer_list fake_irq; /* used after a missed interrupt */
Chris Wilson83348ba2016-08-09 17:47:51 +0100189 struct timer_list hangcheck; /* detect missed interrupts */
190
191 unsigned long timeout;
Chris Wilsonaca34b62016-07-06 12:39:02 +0100192
193 bool irq_enabled : 1;
194 bool rpm_wakelock : 1;
Chris Wilson688e6c72016-07-01 17:23:15 +0100195 } breadcrumbs;
196
Chris Wilson06fbca72015-04-07 16:20:36 +0100197 /*
198 * A pool of objects to use as shadow copies of client batch buffers
199 * when the command parser is enabled. Prevents the client from
200 * modifying the batch contents after software parsing.
201 */
202 struct i915_gem_batch_pool batch_pool;
203
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800204 struct intel_hw_status_page status_page;
Arun Siluvery17ee9502015-06-19 19:07:01 +0100205 struct i915_ctx_workarounds wa_ctx;
Chris Wilson56c0f1a2016-08-15 10:48:58 +0100206 struct i915_vma *scratch;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800207
Chris Wilson61ff75a2016-07-01 17:23:28 +0100208 u32 irq_keep_mask; /* always keep these interrupts */
209 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
Dave Gordon38a0f2d2016-07-20 18:16:06 +0100210 void (*irq_enable)(struct intel_engine_cs *engine);
211 void (*irq_disable)(struct intel_engine_cs *engine);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800212
Dave Gordon38a0f2d2016-07-20 18:16:06 +0100213 int (*init_hw)(struct intel_engine_cs *engine);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800214
John Harrison87531812015-05-29 17:43:44 +0100215 int (*init_context)(struct drm_i915_gem_request *req);
Arun Siluvery86d7f232014-08-26 14:44:50 +0100216
Chris Wilsonddd66c52016-08-02 22:50:31 +0100217 int (*emit_flush)(struct drm_i915_gem_request *request,
218 u32 mode);
219#define EMIT_INVALIDATE BIT(0)
220#define EMIT_FLUSH BIT(1)
221#define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
222 int (*emit_bb_start)(struct drm_i915_gem_request *req,
223 u64 offset, u32 length,
224 unsigned int dispatch_flags);
225#define I915_DISPATCH_SECURE BIT(0)
226#define I915_DISPATCH_PINNED BIT(1)
227#define I915_DISPATCH_RS BIT(2)
228 int (*emit_request)(struct drm_i915_gem_request *req);
229 void (*submit_request)(struct drm_i915_gem_request *req);
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100230 /* Some chipsets are not quite as coherent as advertised and need
231 * an expensive kick to force a true read of the up-to-date seqno.
232 * However, the up-to-date seqno is not always required and the last
233 * seen value is good enough. Note that the seqno will always be
234 * monotonic, even if not coherent.
235 */
Dave Gordon38a0f2d2016-07-20 18:16:06 +0100236 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
Dave Gordon38a0f2d2016-07-20 18:16:06 +0100237 void (*cleanup)(struct intel_engine_cs *engine);
Ben Widawskyebc348b2014-04-29 14:52:28 -0700238
Ben Widawsky3e789982014-06-30 09:53:37 -0700239 /* GEN8 signal/wait table - never trust comments!
240 * signal to signal to signal to signal to signal to
241 * RCS VCS BCS VECS VCS2
242 * --------------------------------------------------------------------
243 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
244 * |-------------------------------------------------------------------
245 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
246 * |-------------------------------------------------------------------
247 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
248 * |-------------------------------------------------------------------
249 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
250 * |-------------------------------------------------------------------
251 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
252 * |-------------------------------------------------------------------
253 *
254 * Generalization:
255 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
256 * ie. transpose of g(x, y)
257 *
258 * sync from sync from sync from sync from sync from
259 * RCS VCS BCS VECS VCS2
260 * --------------------------------------------------------------------
261 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
262 * |-------------------------------------------------------------------
263 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
264 * |-------------------------------------------------------------------
265 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
266 * |-------------------------------------------------------------------
267 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
268 * |-------------------------------------------------------------------
269 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
270 * |-------------------------------------------------------------------
271 *
272 * Generalization:
273 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
274 * ie. transpose of f(x, y)
275 */
Ben Widawskyebc348b2014-04-29 14:52:28 -0700276 struct {
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000277 u32 sync_seqno[I915_NUM_ENGINES-1];
Ben Widawsky78325f22014-04-29 14:52:29 -0700278
Ben Widawsky3e789982014-06-30 09:53:37 -0700279 union {
Tvrtko Ursulin318f89c2016-08-16 17:04:21 +0100280#define GEN6_SEMAPHORE_LAST VECS_HW
281#define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
282#define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
Ben Widawsky3e789982014-06-30 09:53:37 -0700283 struct {
284 /* our mbox written by others */
Tvrtko Ursulin318f89c2016-08-16 17:04:21 +0100285 u32 wait[GEN6_NUM_SEMAPHORES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700286 /* mboxes this ring signals to */
Tvrtko Ursulin318f89c2016-08-16 17:04:21 +0100287 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700288 } mbox;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000289 u64 signal_ggtt[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -0700290 };
Ben Widawsky78325f22014-04-29 14:52:29 -0700291
292 /* AKA wait() */
Chris Wilsonad7bdb22016-08-02 22:50:40 +0100293 int (*sync_to)(struct drm_i915_gem_request *req,
294 struct drm_i915_gem_request *signal);
295 int (*signal)(struct drm_i915_gem_request *req);
Ben Widawskyebc348b2014-04-29 14:52:28 -0700296 } semaphore;
Ben Widawskyad776f82013-05-28 19:22:18 -0700297
Oscar Mateo4da46e12014-07-24 17:04:27 +0100298 /* Execlists */
Tvrtko Ursulin27af5ee2016-04-04 12:11:56 +0100299 struct tasklet_struct irq_tasklet;
300 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
Michel Thierryacdd8842014-07-24 17:04:38 +0100301 struct list_head execlist_queue;
Tvrtko Ursulin37566852016-04-12 14:37:31 +0100302 unsigned int fw_domains;
Tvrtko Ursulinc6a2ac72016-02-26 16:58:32 +0000303 unsigned int next_context_status_buffer;
304 unsigned int idle_lite_restore_wa;
Tvrtko Ursulinca825802016-01-15 15:10:27 +0000305 bool disable_lite_restore_wa;
306 u32 ctx_desc_template;
Oscar Mateo4da46e12014-07-24 17:04:27 +0100307
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800308 /**
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800309 * List of breadcrumbs associated with GPU requests currently
310 * outstanding.
311 */
312 struct list_head request_list;
313
Chris Wilsona56ba562010-09-28 10:07:56 +0100314 /**
Tomas Elf94f7bbe2015-07-09 15:30:57 +0100315 * Seqno of request most recently submitted to request_list.
316 * Used exclusively by hang checker to avoid grabbing lock while
317 * inspecting request list.
318 */
319 u32 last_submitted_seqno;
320
Chris Wilsondcff85c2016-08-05 10:14:11 +0100321 /* An RCU guarded pointer to the last request. No reference is
322 * held to the request, users must carefully acquire a reference to
Chris Wilson1426f712016-08-09 17:03:22 +0100323 * the request using i915_gem_active_get_rcu(), or hold the
Chris Wilsondcff85c2016-08-05 10:14:11 +0100324 * struct_mutex.
325 */
326 struct i915_gem_active last_request;
327
Chris Wilsone2efd132016-05-24 14:53:34 +0100328 struct i915_gem_context *last_context;
Ben Widawsky40521052012-06-04 14:42:43 -0700329
Chris Wilson7e37f882016-08-02 22:50:21 +0100330 struct intel_engine_hangcheck hangcheck;
Mika Kuoppala92cab732013-05-24 17:16:07 +0300331
Brad Volkin44e895a2014-05-10 14:10:43 -0700332 bool needs_cmd_parser;
333
Brad Volkin351e3db2014-02-18 10:15:46 -0800334 /*
Brad Volkin44e895a2014-05-10 14:10:43 -0700335 * Table of commands the command parser needs to know about
Chris Wilson33a051a2016-07-27 09:07:26 +0100336 * for this engine.
Brad Volkin351e3db2014-02-18 10:15:46 -0800337 */
Brad Volkin44e895a2014-05-10 14:10:43 -0700338 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
Brad Volkin351e3db2014-02-18 10:15:46 -0800339
340 /*
341 * Table of registers allowed in commands that read/write registers.
342 */
Jordan Justen361b0272016-03-06 23:30:27 -0800343 const struct drm_i915_reg_table *reg_tables;
344 int reg_table_count;
Brad Volkin351e3db2014-02-18 10:15:46 -0800345
346 /*
347 * Returns the bitmask for the length field of the specified command.
348 * Return 0 for an unrecognized/invalid command.
349 *
Chris Wilson33a051a2016-07-27 09:07:26 +0100350 * If the command parser finds an entry for a command in the engine's
Brad Volkin351e3db2014-02-18 10:15:46 -0800351 * cmd_tables, it gets the command's length based on the table entry.
Chris Wilson33a051a2016-07-27 09:07:26 +0100352 * If not, it calls this function to determine the per-engine length
353 * field encoding for the command (i.e. different opcode ranges use
354 * certain bits to encode the command length in the header).
Brad Volkin351e3db2014-02-18 10:15:46 -0800355 */
356 u32 (*get_cmd_length_mask)(u32 cmd_header);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800357};
358
Dave Gordonb0366a52015-12-08 15:02:36 +0000359static inline bool
Chris Wilson67d97da2016-07-04 08:08:31 +0100360intel_engine_initialized(const struct intel_engine_cs *engine)
Dave Gordonb0366a52015-12-08 15:02:36 +0000361{
Chris Wilsonc0336662016-05-06 15:40:21 +0100362 return engine->i915 != NULL;
Dave Gordonb0366a52015-12-08 15:02:36 +0000363}
Chris Wilsonb4519512012-05-11 14:29:30 +0100364
Daniel Vetter96154f22011-12-14 13:57:00 +0100365static inline unsigned
Chris Wilson67d97da2016-07-04 08:08:31 +0100366intel_engine_flag(const struct intel_engine_cs *engine)
Daniel Vetter96154f22011-12-14 13:57:00 +0100367{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000368 return 1 << engine->id;
Daniel Vetter96154f22011-12-14 13:57:00 +0100369}
370
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800371static inline u32
Chris Wilson7e37f882016-08-02 22:50:21 +0100372intel_engine_sync_index(struct intel_engine_cs *engine,
373 struct intel_engine_cs *other)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000374{
375 int idx;
376
377 /*
Rodrigo Vividdd4dbc2014-06-30 09:51:11 -0700378 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
379 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
380 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
381 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
382 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000383 */
384
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000385 idx = (other - engine) - 1;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000386 if (idx < 0)
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000387 idx += I915_NUM_ENGINES;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000388
389 return idx;
390}
391
Imre Deak319404d2015-08-14 18:35:27 +0300392static inline void
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000393intel_flush_status_page(struct intel_engine_cs *engine, int reg)
Imre Deak319404d2015-08-14 18:35:27 +0300394{
Chris Wilson0d317ce2016-04-09 10:57:56 +0100395 mb();
396 clflush(&engine->status_page.page_addr[reg]);
397 mb();
Imre Deak319404d2015-08-14 18:35:27 +0300398}
399
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000400static inline u32
Chris Wilson5dd8e502016-04-09 10:57:57 +0100401intel_read_status_page(struct intel_engine_cs *engine, int reg)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800402{
Daniel Vetter4225d0f2012-04-26 23:28:16 +0200403 /* Ensure that the compiler doesn't optimize away the load. */
Chris Wilson5dd8e502016-04-09 10:57:57 +0100404 return READ_ONCE(engine->status_page.page_addr[reg]);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800405}
406
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200407static inline void
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000408intel_write_status_page(struct intel_engine_cs *engine,
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200409 int reg, u32 value)
410{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000411 engine->status_page.page_addr[reg] = value;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200412}
413
Jani Nikulae2828912016-01-18 09:19:47 +0200414/*
Chris Wilson311bd682011-01-13 19:06:50 +0000415 * Reads a dword out of the status page, which is written to from the command
416 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
417 * MI_STORE_DATA_IMM.
418 *
419 * The following dwords have a reserved meaning:
420 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
421 * 0x04: ring 0 head pointer
422 * 0x05: ring 1 head pointer (915-class)
423 * 0x06: ring 2 head pointer (915-class)
424 * 0x10-0x1b: Context status DWords (GM45)
425 * 0x1f: Last written status offset. (GM45)
Thomas Danielb07da532015-02-18 11:48:21 +0000426 * 0x20-0x2f: Reserved (Gen6+)
Chris Wilson311bd682011-01-13 19:06:50 +0000427 *
Thomas Danielb07da532015-02-18 11:48:21 +0000428 * The area from dword 0x30 to 0x3ff is available for driver usage.
Chris Wilson311bd682011-01-13 19:06:50 +0000429 */
Thomas Danielb07da532015-02-18 11:48:21 +0000430#define I915_GEM_HWS_INDEX 0x30
Chris Wilson7c17d372016-01-20 15:43:35 +0200431#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
Thomas Danielb07da532015-02-18 11:48:21 +0000432#define I915_GEM_HWS_SCRATCH_INDEX 0x40
Jesse Barnes9a289772012-10-26 09:42:42 -0700433#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
Chris Wilson311bd682011-01-13 19:06:50 +0000434
Chris Wilson7e37f882016-08-02 22:50:21 +0100435struct intel_ring *
436intel_engine_create_ring(struct intel_engine_cs *engine, int size);
Chris Wilsonaad29fb2016-08-02 22:50:23 +0100437int intel_ring_pin(struct intel_ring *ring);
438void intel_ring_unpin(struct intel_ring *ring);
Chris Wilson7e37f882016-08-02 22:50:21 +0100439void intel_ring_free(struct intel_ring *ring);
Oscar Mateo84c23772014-07-24 17:04:15 +0100440
Chris Wilson7e37f882016-08-02 22:50:21 +0100441void intel_engine_stop(struct intel_engine_cs *engine);
442void intel_engine_cleanup(struct intel_engine_cs *engine);
Ben Widawsky96f298a2011-03-19 18:14:27 -0700443
John Harrison6689cb22015-03-19 12:30:08 +0000444int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
445
John Harrison5fb9de12015-05-29 17:44:07 +0100446int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
John Harrisonbba09b12015-05-29 17:44:06 +0100447int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
Chris Wilson406ea8d2016-07-20 13:31:55 +0100448
Chris Wilson7e37f882016-08-02 22:50:21 +0100449static inline void intel_ring_emit(struct intel_ring *ring, u32 data)
Chris Wilsone898cd22010-08-04 15:18:14 +0100450{
Chris Wilsonb5321f32016-08-02 22:50:18 +0100451 *(uint32_t *)(ring->vaddr + ring->tail) = data;
452 ring->tail += 4;
Chris Wilsone898cd22010-08-04 15:18:14 +0100453}
Chris Wilson406ea8d2016-07-20 13:31:55 +0100454
Chris Wilson7e37f882016-08-02 22:50:21 +0100455static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg)
Ville Syrjäläf92a9162015-11-04 23:20:07 +0200456{
Chris Wilsonb5321f32016-08-02 22:50:18 +0100457 intel_ring_emit(ring, i915_mmio_reg_offset(reg));
Ville Syrjäläf92a9162015-11-04 23:20:07 +0200458}
Chris Wilson406ea8d2016-07-20 13:31:55 +0100459
Chris Wilson7e37f882016-08-02 22:50:21 +0100460static inline void intel_ring_advance(struct intel_ring *ring)
Chris Wilson09246732013-08-10 22:16:32 +0100461{
Chris Wilson8f942012016-08-02 22:50:30 +0100462 /* Dummy function.
463 *
464 * This serves as a placeholder in the code so that the reader
465 * can compare against the preceding intel_ring_begin() and
466 * check that the number of dwords emitted matches the space
467 * reserved for the command packet (i.e. the value passed to
468 * intel_ring_begin()).
Chris Wilsonc5efa1a2016-08-02 22:50:29 +0100469 */
Chris Wilson8f942012016-08-02 22:50:30 +0100470}
471
472static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value)
473{
474 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
475 return value & (ring->size - 1);
Chris Wilson09246732013-08-10 22:16:32 +0100476}
Chris Wilson406ea8d2016-07-20 13:31:55 +0100477
Oscar Mateo82e104c2014-07-24 17:04:26 +0100478int __intel_ring_space(int head, int tail, int size);
Chris Wilson32c04f12016-08-02 22:50:22 +0100479void intel_ring_update_space(struct intel_ring *ring);
Chris Wilson09246732013-08-10 22:16:32 +0100480
Chris Wilson7e37f882016-08-02 22:50:21 +0100481void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800482
Tvrtko Ursulin019bf272016-07-13 16:03:41 +0100483void intel_engine_setup_common(struct intel_engine_cs *engine);
484int intel_engine_init_common(struct intel_engine_cs *engine);
Chris Wilsonadc320c2016-08-15 10:48:59 +0100485int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
Chris Wilson96a945a2016-08-03 13:19:16 +0100486void intel_engine_cleanup_common(struct intel_engine_cs *engine);
Tvrtko Ursulin019bf272016-07-13 16:03:41 +0100487
Chris Wilsondcff85c2016-08-05 10:14:11 +0100488static inline int intel_engine_idle(struct intel_engine_cs *engine,
489 bool interruptible)
490{
491 /* Wait upon the last request to be completed */
492 return i915_gem_active_wait_unlocked(&engine->last_request,
493 interruptible, NULL, NULL);
494}
495
Tvrtko Ursulin8b3e2d32016-07-13 16:03:37 +0100496int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
497int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
498int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
499int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
500int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800501
Chris Wilson7e37f882016-08-02 22:50:21 +0100502u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
Chris Wilson1b7744e2016-07-01 17:23:17 +0100503static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
504{
505 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
506}
Daniel Vetter79f321b2010-09-24 21:20:10 +0200507
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +0000508int init_workarounds_ring(struct intel_engine_cs *engine);
Michel Thierry771b9a52014-11-11 16:47:33 +0000509
John Harrison29b1b412015-06-18 13:10:09 +0100510/*
511 * Arbitrary size for largest possible 'add request' sequence. The code paths
512 * are complex and variable. Empirical measurement shows that the worst case
Chris Wilson596e5ef2016-04-29 09:07:04 +0100513 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
514 * we need to allocate double the largest single packet within that emission
515 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
John Harrison29b1b412015-06-18 13:10:09 +0100516 */
Chris Wilson596e5ef2016-04-29 09:07:04 +0100517#define MIN_SPACE_FOR_ADD_REQUEST 336
John Harrison29b1b412015-06-18 13:10:09 +0100518
Chris Wilsona58c01a2016-04-29 13:18:21 +0100519static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
520{
Chris Wilson57e88532016-08-15 10:48:57 +0100521 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
Chris Wilsona58c01a2016-04-29 13:18:21 +0100522}
523
Chris Wilson688e6c72016-07-01 17:23:15 +0100524/* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
Chris Wilson688e6c72016-07-01 17:23:15 +0100525int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
526
527static inline void intel_wait_init(struct intel_wait *wait, u32 seqno)
528{
529 wait->tsk = current;
530 wait->seqno = seqno;
531}
532
533static inline bool intel_wait_complete(const struct intel_wait *wait)
534{
535 return RB_EMPTY_NODE(&wait->node);
536}
537
538bool intel_engine_add_wait(struct intel_engine_cs *engine,
539 struct intel_wait *wait);
540void intel_engine_remove_wait(struct intel_engine_cs *engine,
541 struct intel_wait *wait);
Chris Wilsonb3850852016-07-01 17:23:26 +0100542void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
Chris Wilson688e6c72016-07-01 17:23:15 +0100543
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100544static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
Chris Wilson688e6c72016-07-01 17:23:15 +0100545{
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100546 return rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh);
Chris Wilson688e6c72016-07-01 17:23:15 +0100547}
548
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100549static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
Chris Wilson688e6c72016-07-01 17:23:15 +0100550{
551 bool wakeup = false;
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100552
Chris Wilson688e6c72016-07-01 17:23:15 +0100553 /* Note that for this not to dangerously chase a dangling pointer,
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100554 * we must hold the rcu_read_lock here.
Chris Wilson688e6c72016-07-01 17:23:15 +0100555 *
556 * Also note that tsk is likely to be in !TASK_RUNNING state so an
557 * early test for tsk->state != TASK_RUNNING before wake_up_process()
558 * is unlikely to be beneficial.
559 */
Chris Wilsondbd6ef22016-08-09 17:47:52 +0100560 if (intel_engine_has_waiter(engine)) {
561 struct task_struct *tsk;
562
563 rcu_read_lock();
564 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
565 if (tsk)
566 wakeup = wake_up_process(tsk);
567 rcu_read_unlock();
568 }
569
Chris Wilson688e6c72016-07-01 17:23:15 +0100570 return wakeup;
571}
572
Chris Wilson688e6c72016-07-01 17:23:15 +0100573void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
574unsigned int intel_kick_waiters(struct drm_i915_private *i915);
Chris Wilsonc81d4612016-07-01 17:23:25 +0100575unsigned int intel_kick_signalers(struct drm_i915_private *i915);
Chris Wilson688e6c72016-07-01 17:23:15 +0100576
Chris Wilsondcff85c2016-08-05 10:14:11 +0100577static inline bool intel_engine_is_active(struct intel_engine_cs *engine)
578{
579 return i915_gem_active_isset(&engine->last_request);
580}
581
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800582#endif /* _INTEL_RINGBUFFER_H_ */