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Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001/*
2 * Copyright (C) 2015 Microchip Technology
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/version.h>
18#include <linux/module.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000022#include <linux/usb.h>
23#include <linux/crc32.h>
24#include <linux/signal.h>
25#include <linux/slab.h>
26#include <linux/if_vlan.h>
27#include <linux/uaccess.h>
28#include <linux/list.h>
29#include <linux/ip.h>
30#include <linux/ipv6.h>
31#include <linux/mdio.h>
32#include <net/ip6_checksum.h>
Woojung Huhcc89c322016-11-01 20:02:00 +000033#include <linux/interrupt.h>
34#include <linux/irqdomain.h>
35#include <linux/irq.h>
36#include <linux/irqchip/chained_irq.h>
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +000037#include <linux/microchipphy.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000038#include "lan78xx.h"
39
40#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
41#define DRIVER_DESC "LAN78XX USB 3.0 Gigabit Ethernet Devices"
42#define DRIVER_NAME "lan78xx"
Woojung Huhcc89c322016-11-01 20:02:00 +000043#define DRIVER_VERSION "1.0.5"
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000044
45#define TX_TIMEOUT_JIFFIES (5 * HZ)
46#define THROTTLE_JIFFIES (HZ / 8)
47#define UNLINK_TIMEOUT_MS 3
48
49#define RX_MAX_QUEUE_MEMORY (60 * 1518)
50
51#define SS_USB_PKT_SIZE (1024)
52#define HS_USB_PKT_SIZE (512)
53#define FS_USB_PKT_SIZE (64)
54
55#define MAX_RX_FIFO_SIZE (12 * 1024)
56#define MAX_TX_FIFO_SIZE (12 * 1024)
57#define DEFAULT_BURST_CAP_SIZE (MAX_TX_FIFO_SIZE)
58#define DEFAULT_BULK_IN_DELAY (0x0800)
59#define MAX_SINGLE_PACKET_SIZE (9000)
60#define DEFAULT_TX_CSUM_ENABLE (true)
61#define DEFAULT_RX_CSUM_ENABLE (true)
62#define DEFAULT_TSO_CSUM_ENABLE (true)
63#define DEFAULT_VLAN_FILTER_ENABLE (true)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000064#define TX_OVERHEAD (8)
65#define RXW_PADDING 2
66
67#define LAN78XX_USB_VENDOR_ID (0x0424)
68#define LAN7800_USB_PRODUCT_ID (0x7800)
69#define LAN7850_USB_PRODUCT_ID (0x7850)
70#define LAN78XX_EEPROM_MAGIC (0x78A5)
71#define LAN78XX_OTP_MAGIC (0x78F3)
72
73#define MII_READ 1
74#define MII_WRITE 0
75
76#define EEPROM_INDICATOR (0xA5)
77#define EEPROM_MAC_OFFSET (0x01)
78#define MAX_EEPROM_SIZE 512
79#define OTP_INDICATOR_1 (0xF3)
80#define OTP_INDICATOR_2 (0xF7)
81
82#define WAKE_ALL (WAKE_PHY | WAKE_UCAST | \
83 WAKE_MCAST | WAKE_BCAST | \
84 WAKE_ARP | WAKE_MAGIC)
85
86/* USB related defines */
87#define BULK_IN_PIPE 1
88#define BULK_OUT_PIPE 2
89
90/* default autosuspend delay (mSec)*/
91#define DEFAULT_AUTOSUSPEND_DELAY (10 * 1000)
92
Woojung Huh20ff5562016-03-16 22:10:40 +000093/* statistic update interval (mSec) */
94#define STAT_UPDATE_TIMER (1 * 1000)
95
Woojung Huhcc89c322016-11-01 20:02:00 +000096/* defines interrupts from interrupt EP */
97#define MAX_INT_EP (32)
98#define INT_EP_INTEP (31)
99#define INT_EP_OTP_WR_DONE (28)
100#define INT_EP_EEE_TX_LPI_START (26)
101#define INT_EP_EEE_TX_LPI_STOP (25)
102#define INT_EP_EEE_RX_LPI (24)
103#define INT_EP_MAC_RESET_TIMEOUT (23)
104#define INT_EP_RDFO (22)
105#define INT_EP_TXE (21)
106#define INT_EP_USB_STATUS (20)
107#define INT_EP_TX_DIS (19)
108#define INT_EP_RX_DIS (18)
109#define INT_EP_PHY (17)
110#define INT_EP_DP (16)
111#define INT_EP_MAC_ERR (15)
112#define INT_EP_TDFU (14)
113#define INT_EP_TDFO (13)
114#define INT_EP_UTX (12)
115#define INT_EP_GPIO_11 (11)
116#define INT_EP_GPIO_10 (10)
117#define INT_EP_GPIO_9 (9)
118#define INT_EP_GPIO_8 (8)
119#define INT_EP_GPIO_7 (7)
120#define INT_EP_GPIO_6 (6)
121#define INT_EP_GPIO_5 (5)
122#define INT_EP_GPIO_4 (4)
123#define INT_EP_GPIO_3 (3)
124#define INT_EP_GPIO_2 (2)
125#define INT_EP_GPIO_1 (1)
126#define INT_EP_GPIO_0 (0)
127
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000128static const char lan78xx_gstrings[][ETH_GSTRING_LEN] = {
129 "RX FCS Errors",
130 "RX Alignment Errors",
131 "Rx Fragment Errors",
132 "RX Jabber Errors",
133 "RX Undersize Frame Errors",
134 "RX Oversize Frame Errors",
135 "RX Dropped Frames",
136 "RX Unicast Byte Count",
137 "RX Broadcast Byte Count",
138 "RX Multicast Byte Count",
139 "RX Unicast Frames",
140 "RX Broadcast Frames",
141 "RX Multicast Frames",
142 "RX Pause Frames",
143 "RX 64 Byte Frames",
144 "RX 65 - 127 Byte Frames",
145 "RX 128 - 255 Byte Frames",
146 "RX 256 - 511 Bytes Frames",
147 "RX 512 - 1023 Byte Frames",
148 "RX 1024 - 1518 Byte Frames",
149 "RX Greater 1518 Byte Frames",
150 "EEE RX LPI Transitions",
151 "EEE RX LPI Time",
152 "TX FCS Errors",
153 "TX Excess Deferral Errors",
154 "TX Carrier Errors",
155 "TX Bad Byte Count",
156 "TX Single Collisions",
157 "TX Multiple Collisions",
158 "TX Excessive Collision",
159 "TX Late Collisions",
160 "TX Unicast Byte Count",
161 "TX Broadcast Byte Count",
162 "TX Multicast Byte Count",
163 "TX Unicast Frames",
164 "TX Broadcast Frames",
165 "TX Multicast Frames",
166 "TX Pause Frames",
167 "TX 64 Byte Frames",
168 "TX 65 - 127 Byte Frames",
169 "TX 128 - 255 Byte Frames",
170 "TX 256 - 511 Bytes Frames",
171 "TX 512 - 1023 Byte Frames",
172 "TX 1024 - 1518 Byte Frames",
173 "TX Greater 1518 Byte Frames",
174 "EEE TX LPI Transitions",
175 "EEE TX LPI Time",
176};
177
178struct lan78xx_statstage {
179 u32 rx_fcs_errors;
180 u32 rx_alignment_errors;
181 u32 rx_fragment_errors;
182 u32 rx_jabber_errors;
183 u32 rx_undersize_frame_errors;
184 u32 rx_oversize_frame_errors;
185 u32 rx_dropped_frames;
186 u32 rx_unicast_byte_count;
187 u32 rx_broadcast_byte_count;
188 u32 rx_multicast_byte_count;
189 u32 rx_unicast_frames;
190 u32 rx_broadcast_frames;
191 u32 rx_multicast_frames;
192 u32 rx_pause_frames;
193 u32 rx_64_byte_frames;
194 u32 rx_65_127_byte_frames;
195 u32 rx_128_255_byte_frames;
196 u32 rx_256_511_bytes_frames;
197 u32 rx_512_1023_byte_frames;
198 u32 rx_1024_1518_byte_frames;
199 u32 rx_greater_1518_byte_frames;
200 u32 eee_rx_lpi_transitions;
201 u32 eee_rx_lpi_time;
202 u32 tx_fcs_errors;
203 u32 tx_excess_deferral_errors;
204 u32 tx_carrier_errors;
205 u32 tx_bad_byte_count;
206 u32 tx_single_collisions;
207 u32 tx_multiple_collisions;
208 u32 tx_excessive_collision;
209 u32 tx_late_collisions;
210 u32 tx_unicast_byte_count;
211 u32 tx_broadcast_byte_count;
212 u32 tx_multicast_byte_count;
213 u32 tx_unicast_frames;
214 u32 tx_broadcast_frames;
215 u32 tx_multicast_frames;
216 u32 tx_pause_frames;
217 u32 tx_64_byte_frames;
218 u32 tx_65_127_byte_frames;
219 u32 tx_128_255_byte_frames;
220 u32 tx_256_511_bytes_frames;
221 u32 tx_512_1023_byte_frames;
222 u32 tx_1024_1518_byte_frames;
223 u32 tx_greater_1518_byte_frames;
224 u32 eee_tx_lpi_transitions;
225 u32 eee_tx_lpi_time;
226};
227
Woojung Huh20ff5562016-03-16 22:10:40 +0000228struct lan78xx_statstage64 {
229 u64 rx_fcs_errors;
230 u64 rx_alignment_errors;
231 u64 rx_fragment_errors;
232 u64 rx_jabber_errors;
233 u64 rx_undersize_frame_errors;
234 u64 rx_oversize_frame_errors;
235 u64 rx_dropped_frames;
236 u64 rx_unicast_byte_count;
237 u64 rx_broadcast_byte_count;
238 u64 rx_multicast_byte_count;
239 u64 rx_unicast_frames;
240 u64 rx_broadcast_frames;
241 u64 rx_multicast_frames;
242 u64 rx_pause_frames;
243 u64 rx_64_byte_frames;
244 u64 rx_65_127_byte_frames;
245 u64 rx_128_255_byte_frames;
246 u64 rx_256_511_bytes_frames;
247 u64 rx_512_1023_byte_frames;
248 u64 rx_1024_1518_byte_frames;
249 u64 rx_greater_1518_byte_frames;
250 u64 eee_rx_lpi_transitions;
251 u64 eee_rx_lpi_time;
252 u64 tx_fcs_errors;
253 u64 tx_excess_deferral_errors;
254 u64 tx_carrier_errors;
255 u64 tx_bad_byte_count;
256 u64 tx_single_collisions;
257 u64 tx_multiple_collisions;
258 u64 tx_excessive_collision;
259 u64 tx_late_collisions;
260 u64 tx_unicast_byte_count;
261 u64 tx_broadcast_byte_count;
262 u64 tx_multicast_byte_count;
263 u64 tx_unicast_frames;
264 u64 tx_broadcast_frames;
265 u64 tx_multicast_frames;
266 u64 tx_pause_frames;
267 u64 tx_64_byte_frames;
268 u64 tx_65_127_byte_frames;
269 u64 tx_128_255_byte_frames;
270 u64 tx_256_511_bytes_frames;
271 u64 tx_512_1023_byte_frames;
272 u64 tx_1024_1518_byte_frames;
273 u64 tx_greater_1518_byte_frames;
274 u64 eee_tx_lpi_transitions;
275 u64 eee_tx_lpi_time;
276};
277
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000278struct lan78xx_net;
279
280struct lan78xx_priv {
281 struct lan78xx_net *dev;
282 u32 rfe_ctl;
283 u32 mchash_table[DP_SEL_VHF_HASH_LEN]; /* multicat hash table */
284 u32 pfilter_table[NUM_OF_MAF][2]; /* perfect filter table */
285 u32 vlan_table[DP_SEL_VHF_VLAN_LEN];
286 struct mutex dataport_mutex; /* for dataport access */
287 spinlock_t rfe_ctl_lock; /* for rfe register access */
288 struct work_struct set_multicast;
289 struct work_struct set_vlan;
290 u32 wol;
291};
292
293enum skb_state {
294 illegal = 0,
295 tx_start,
296 tx_done,
297 rx_start,
298 rx_done,
299 rx_cleanup,
300 unlink_start
301};
302
303struct skb_data { /* skb->cb is one of these */
304 struct urb *urb;
305 struct lan78xx_net *dev;
306 enum skb_state state;
307 size_t length;
Woojung Huh74d79a22016-04-25 22:22:32 +0000308 int num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000309};
310
311struct usb_context {
312 struct usb_ctrlrequest req;
313 struct lan78xx_net *dev;
314};
315
316#define EVENT_TX_HALT 0
317#define EVENT_RX_HALT 1
318#define EVENT_RX_MEMORY 2
319#define EVENT_STS_SPLIT 3
320#define EVENT_LINK_RESET 4
321#define EVENT_RX_PAUSED 5
322#define EVENT_DEV_WAKING 6
323#define EVENT_DEV_ASLEEP 7
324#define EVENT_DEV_OPEN 8
Woojung Huh20ff5562016-03-16 22:10:40 +0000325#define EVENT_STAT_UPDATE 9
326
327struct statstage {
328 struct mutex access_lock; /* for stats access */
329 struct lan78xx_statstage saved;
330 struct lan78xx_statstage rollover_count;
331 struct lan78xx_statstage rollover_max;
332 struct lan78xx_statstage64 curr_stat;
333};
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000334
Woojung Huhcc89c322016-11-01 20:02:00 +0000335struct irq_domain_data {
336 struct irq_domain *irqdomain;
337 unsigned int phyirq;
338 struct irq_chip *irqchip;
339 irq_flow_handler_t irq_handler;
340 u32 irqenable;
341 struct mutex irq_lock; /* for irq bus access */
342};
343
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000344struct lan78xx_net {
345 struct net_device *net;
346 struct usb_device *udev;
347 struct usb_interface *intf;
348 void *driver_priv;
349
350 int rx_qlen;
351 int tx_qlen;
352 struct sk_buff_head rxq;
353 struct sk_buff_head txq;
354 struct sk_buff_head done;
355 struct sk_buff_head rxq_pause;
356 struct sk_buff_head txq_pend;
357
358 struct tasklet_struct bh;
359 struct delayed_work wq;
360
361 struct usb_host_endpoint *ep_blkin;
362 struct usb_host_endpoint *ep_blkout;
363 struct usb_host_endpoint *ep_intr;
364
365 int msg_enable;
366
367 struct urb *urb_intr;
368 struct usb_anchor deferred;
369
370 struct mutex phy_mutex; /* for phy access */
371 unsigned pipe_in, pipe_out, pipe_intr;
372
373 u32 hard_mtu; /* count any extra framing */
374 size_t rx_urb_size; /* size for rx urbs */
375
376 unsigned long flags;
377
378 wait_queue_head_t *wait;
379 unsigned char suspend_count;
380
381 unsigned maxpacket;
382 struct timer_list delay;
Woojung Huh20ff5562016-03-16 22:10:40 +0000383 struct timer_list stat_monitor;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000384
385 unsigned long data[5];
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000386
387 int link_on;
388 u8 mdix_ctrl;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000389
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000390 u32 chipid;
391 u32 chiprev;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000392 struct mii_bus *mdiobus;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +0000393
394 int fc_autoneg;
395 u8 fc_request_control;
Woojung Huh20ff5562016-03-16 22:10:40 +0000396
397 int delta;
398 struct statstage stats;
Woojung Huhcc89c322016-11-01 20:02:00 +0000399
400 struct irq_domain_data domain_data;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000401};
402
403/* use ethtool to change the level for any given device */
404static int msg_level = -1;
405module_param(msg_level, int, 0);
406MODULE_PARM_DESC(msg_level, "Override default message level");
407
408static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
409{
410 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
411 int ret;
412
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000413 if (!buf)
414 return -ENOMEM;
415
416 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
417 USB_VENDOR_REQUEST_READ_REGISTER,
418 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
419 0, index, buf, 4, USB_CTRL_GET_TIMEOUT);
420 if (likely(ret >= 0)) {
421 le32_to_cpus(buf);
422 *data = *buf;
423 } else {
424 netdev_warn(dev->net,
425 "Failed to read register index 0x%08x. ret = %d",
426 index, ret);
427 }
428
429 kfree(buf);
430
431 return ret;
432}
433
434static int lan78xx_write_reg(struct lan78xx_net *dev, u32 index, u32 data)
435{
436 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
437 int ret;
438
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000439 if (!buf)
440 return -ENOMEM;
441
442 *buf = data;
443 cpu_to_le32s(buf);
444
445 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
446 USB_VENDOR_REQUEST_WRITE_REGISTER,
447 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
448 0, index, buf, 4, USB_CTRL_SET_TIMEOUT);
449 if (unlikely(ret < 0)) {
450 netdev_warn(dev->net,
451 "Failed to write register index 0x%08x. ret = %d",
452 index, ret);
453 }
454
455 kfree(buf);
456
457 return ret;
458}
459
460static int lan78xx_read_stats(struct lan78xx_net *dev,
461 struct lan78xx_statstage *data)
462{
463 int ret = 0;
464 int i;
465 struct lan78xx_statstage *stats;
466 u32 *src;
467 u32 *dst;
468
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000469 stats = kmalloc(sizeof(*stats), GFP_KERNEL);
470 if (!stats)
471 return -ENOMEM;
472
473 ret = usb_control_msg(dev->udev,
474 usb_rcvctrlpipe(dev->udev, 0),
475 USB_VENDOR_REQUEST_GET_STATS,
476 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
477 0,
478 0,
479 (void *)stats,
480 sizeof(*stats),
481 USB_CTRL_SET_TIMEOUT);
482 if (likely(ret >= 0)) {
483 src = (u32 *)stats;
484 dst = (u32 *)data;
485 for (i = 0; i < sizeof(*stats)/sizeof(u32); i++) {
486 le32_to_cpus(&src[i]);
487 dst[i] = src[i];
488 }
489 } else {
490 netdev_warn(dev->net,
491 "Failed to read stat ret = 0x%x", ret);
492 }
493
494 kfree(stats);
495
496 return ret;
497}
498
Woojung Huh20ff5562016-03-16 22:10:40 +0000499#define check_counter_rollover(struct1, dev_stats, member) { \
500 if (struct1->member < dev_stats.saved.member) \
501 dev_stats.rollover_count.member++; \
502 }
503
504static void lan78xx_check_stat_rollover(struct lan78xx_net *dev,
505 struct lan78xx_statstage *stats)
506{
507 check_counter_rollover(stats, dev->stats, rx_fcs_errors);
508 check_counter_rollover(stats, dev->stats, rx_alignment_errors);
509 check_counter_rollover(stats, dev->stats, rx_fragment_errors);
510 check_counter_rollover(stats, dev->stats, rx_jabber_errors);
511 check_counter_rollover(stats, dev->stats, rx_undersize_frame_errors);
512 check_counter_rollover(stats, dev->stats, rx_oversize_frame_errors);
513 check_counter_rollover(stats, dev->stats, rx_dropped_frames);
514 check_counter_rollover(stats, dev->stats, rx_unicast_byte_count);
515 check_counter_rollover(stats, dev->stats, rx_broadcast_byte_count);
516 check_counter_rollover(stats, dev->stats, rx_multicast_byte_count);
517 check_counter_rollover(stats, dev->stats, rx_unicast_frames);
518 check_counter_rollover(stats, dev->stats, rx_broadcast_frames);
519 check_counter_rollover(stats, dev->stats, rx_multicast_frames);
520 check_counter_rollover(stats, dev->stats, rx_pause_frames);
521 check_counter_rollover(stats, dev->stats, rx_64_byte_frames);
522 check_counter_rollover(stats, dev->stats, rx_65_127_byte_frames);
523 check_counter_rollover(stats, dev->stats, rx_128_255_byte_frames);
524 check_counter_rollover(stats, dev->stats, rx_256_511_bytes_frames);
525 check_counter_rollover(stats, dev->stats, rx_512_1023_byte_frames);
526 check_counter_rollover(stats, dev->stats, rx_1024_1518_byte_frames);
527 check_counter_rollover(stats, dev->stats, rx_greater_1518_byte_frames);
528 check_counter_rollover(stats, dev->stats, eee_rx_lpi_transitions);
529 check_counter_rollover(stats, dev->stats, eee_rx_lpi_time);
530 check_counter_rollover(stats, dev->stats, tx_fcs_errors);
531 check_counter_rollover(stats, dev->stats, tx_excess_deferral_errors);
532 check_counter_rollover(stats, dev->stats, tx_carrier_errors);
533 check_counter_rollover(stats, dev->stats, tx_bad_byte_count);
534 check_counter_rollover(stats, dev->stats, tx_single_collisions);
535 check_counter_rollover(stats, dev->stats, tx_multiple_collisions);
536 check_counter_rollover(stats, dev->stats, tx_excessive_collision);
537 check_counter_rollover(stats, dev->stats, tx_late_collisions);
538 check_counter_rollover(stats, dev->stats, tx_unicast_byte_count);
539 check_counter_rollover(stats, dev->stats, tx_broadcast_byte_count);
540 check_counter_rollover(stats, dev->stats, tx_multicast_byte_count);
541 check_counter_rollover(stats, dev->stats, tx_unicast_frames);
542 check_counter_rollover(stats, dev->stats, tx_broadcast_frames);
543 check_counter_rollover(stats, dev->stats, tx_multicast_frames);
544 check_counter_rollover(stats, dev->stats, tx_pause_frames);
545 check_counter_rollover(stats, dev->stats, tx_64_byte_frames);
546 check_counter_rollover(stats, dev->stats, tx_65_127_byte_frames);
547 check_counter_rollover(stats, dev->stats, tx_128_255_byte_frames);
548 check_counter_rollover(stats, dev->stats, tx_256_511_bytes_frames);
549 check_counter_rollover(stats, dev->stats, tx_512_1023_byte_frames);
550 check_counter_rollover(stats, dev->stats, tx_1024_1518_byte_frames);
551 check_counter_rollover(stats, dev->stats, tx_greater_1518_byte_frames);
552 check_counter_rollover(stats, dev->stats, eee_tx_lpi_transitions);
553 check_counter_rollover(stats, dev->stats, eee_tx_lpi_time);
554
555 memcpy(&dev->stats.saved, stats, sizeof(struct lan78xx_statstage));
556}
557
558static void lan78xx_update_stats(struct lan78xx_net *dev)
559{
560 u32 *p, *count, *max;
561 u64 *data;
562 int i;
563 struct lan78xx_statstage lan78xx_stats;
564
565 if (usb_autopm_get_interface(dev->intf) < 0)
566 return;
567
568 p = (u32 *)&lan78xx_stats;
569 count = (u32 *)&dev->stats.rollover_count;
570 max = (u32 *)&dev->stats.rollover_max;
571 data = (u64 *)&dev->stats.curr_stat;
572
573 mutex_lock(&dev->stats.access_lock);
574
575 if (lan78xx_read_stats(dev, &lan78xx_stats) > 0)
576 lan78xx_check_stat_rollover(dev, &lan78xx_stats);
577
578 for (i = 0; i < (sizeof(lan78xx_stats) / (sizeof(u32))); i++)
579 data[i] = (u64)p[i] + ((u64)count[i] * ((u64)max[i] + 1));
580
581 mutex_unlock(&dev->stats.access_lock);
582
583 usb_autopm_put_interface(dev->intf);
584}
585
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000586/* Loop until the read is completed with timeout called with phy_mutex held */
587static int lan78xx_phy_wait_not_busy(struct lan78xx_net *dev)
588{
589 unsigned long start_time = jiffies;
590 u32 val;
591 int ret;
592
593 do {
594 ret = lan78xx_read_reg(dev, MII_ACC, &val);
595 if (unlikely(ret < 0))
596 return -EIO;
597
598 if (!(val & MII_ACC_MII_BUSY_))
599 return 0;
600 } while (!time_after(jiffies, start_time + HZ));
601
602 return -EIO;
603}
604
605static inline u32 mii_access(int id, int index, int read)
606{
607 u32 ret;
608
609 ret = ((u32)id << MII_ACC_PHY_ADDR_SHIFT_) & MII_ACC_PHY_ADDR_MASK_;
610 ret |= ((u32)index << MII_ACC_MIIRINDA_SHIFT_) & MII_ACC_MIIRINDA_MASK_;
611 if (read)
612 ret |= MII_ACC_MII_READ_;
613 else
614 ret |= MII_ACC_MII_WRITE_;
615 ret |= MII_ACC_MII_BUSY_;
616
617 return ret;
618}
619
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000620static int lan78xx_wait_eeprom(struct lan78xx_net *dev)
621{
622 unsigned long start_time = jiffies;
623 u32 val;
624 int ret;
625
626 do {
627 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
628 if (unlikely(ret < 0))
629 return -EIO;
630
631 if (!(val & E2P_CMD_EPC_BUSY_) ||
632 (val & E2P_CMD_EPC_TIMEOUT_))
633 break;
634 usleep_range(40, 100);
635 } while (!time_after(jiffies, start_time + HZ));
636
637 if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
638 netdev_warn(dev->net, "EEPROM read operation timeout");
639 return -EIO;
640 }
641
642 return 0;
643}
644
645static int lan78xx_eeprom_confirm_not_busy(struct lan78xx_net *dev)
646{
647 unsigned long start_time = jiffies;
648 u32 val;
649 int ret;
650
651 do {
652 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
653 if (unlikely(ret < 0))
654 return -EIO;
655
656 if (!(val & E2P_CMD_EPC_BUSY_))
657 return 0;
658
659 usleep_range(40, 100);
660 } while (!time_after(jiffies, start_time + HZ));
661
662 netdev_warn(dev->net, "EEPROM is busy");
663 return -EIO;
664}
665
666static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
667 u32 length, u8 *data)
668{
669 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000670 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000671 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000672 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000673
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000674 /* depends on chip, some EEPROM pins are muxed with LED function.
675 * disable & restore LED function to access EEPROM.
676 */
677 ret = lan78xx_read_reg(dev, HW_CFG, &val);
678 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000679 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000680 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
681 ret = lan78xx_write_reg(dev, HW_CFG, val);
682 }
683
684 retval = lan78xx_eeprom_confirm_not_busy(dev);
685 if (retval)
686 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000687
688 for (i = 0; i < length; i++) {
689 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
690 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
691 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000692 if (unlikely(ret < 0)) {
693 retval = -EIO;
694 goto exit;
695 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000696
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000697 retval = lan78xx_wait_eeprom(dev);
698 if (retval < 0)
699 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000700
701 ret = lan78xx_read_reg(dev, E2P_DATA, &val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000702 if (unlikely(ret < 0)) {
703 retval = -EIO;
704 goto exit;
705 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000706
707 data[i] = val & 0xFF;
708 offset++;
709 }
710
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000711 retval = 0;
712exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000713 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000714 ret = lan78xx_write_reg(dev, HW_CFG, saved);
715
716 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000717}
718
719static int lan78xx_read_eeprom(struct lan78xx_net *dev, u32 offset,
720 u32 length, u8 *data)
721{
722 u8 sig;
723 int ret;
724
725 ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
726 if ((ret == 0) && (sig == EEPROM_INDICATOR))
727 ret = lan78xx_read_raw_eeprom(dev, offset, length, data);
728 else
729 ret = -EINVAL;
730
731 return ret;
732}
733
734static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
735 u32 length, u8 *data)
736{
737 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000738 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000739 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000740 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000741
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000742 /* depends on chip, some EEPROM pins are muxed with LED function.
743 * disable & restore LED function to access EEPROM.
744 */
745 ret = lan78xx_read_reg(dev, HW_CFG, &val);
746 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000747 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000748 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
749 ret = lan78xx_write_reg(dev, HW_CFG, val);
750 }
751
752 retval = lan78xx_eeprom_confirm_not_busy(dev);
753 if (retval)
754 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000755
756 /* Issue write/erase enable command */
757 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
758 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000759 if (unlikely(ret < 0)) {
760 retval = -EIO;
761 goto exit;
762 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000763
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000764 retval = lan78xx_wait_eeprom(dev);
765 if (retval < 0)
766 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000767
768 for (i = 0; i < length; i++) {
769 /* Fill data register */
770 val = data[i];
771 ret = lan78xx_write_reg(dev, E2P_DATA, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000772 if (ret < 0) {
773 retval = -EIO;
774 goto exit;
775 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000776
777 /* Send "write" command */
778 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
779 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
780 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000781 if (ret < 0) {
782 retval = -EIO;
783 goto exit;
784 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000785
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000786 retval = lan78xx_wait_eeprom(dev);
787 if (retval < 0)
788 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000789
790 offset++;
791 }
792
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000793 retval = 0;
794exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000795 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000796 ret = lan78xx_write_reg(dev, HW_CFG, saved);
797
798 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000799}
800
801static int lan78xx_read_raw_otp(struct lan78xx_net *dev, u32 offset,
802 u32 length, u8 *data)
803{
804 int i;
805 int ret;
806 u32 buf;
807 unsigned long timeout;
808
809 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
810
811 if (buf & OTP_PWR_DN_PWRDN_N_) {
812 /* clear it and wait to be cleared */
813 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
814
815 timeout = jiffies + HZ;
816 do {
817 usleep_range(1, 10);
818 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
819 if (time_after(jiffies, timeout)) {
820 netdev_warn(dev->net,
821 "timeout on OTP_PWR_DN");
822 return -EIO;
823 }
824 } while (buf & OTP_PWR_DN_PWRDN_N_);
825 }
826
827 for (i = 0; i < length; i++) {
828 ret = lan78xx_write_reg(dev, OTP_ADDR1,
829 ((offset + i) >> 8) & OTP_ADDR1_15_11);
830 ret = lan78xx_write_reg(dev, OTP_ADDR2,
831 ((offset + i) & OTP_ADDR2_10_3));
832
833 ret = lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
834 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
835
836 timeout = jiffies + HZ;
837 do {
838 udelay(1);
839 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
840 if (time_after(jiffies, timeout)) {
841 netdev_warn(dev->net,
842 "timeout on OTP_STATUS");
843 return -EIO;
844 }
845 } while (buf & OTP_STATUS_BUSY_);
846
847 ret = lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
848
849 data[i] = (u8)(buf & 0xFF);
850 }
851
852 return 0;
853}
854
Woojung.Huh@microchip.com9fb60662016-01-05 17:29:59 +0000855static int lan78xx_write_raw_otp(struct lan78xx_net *dev, u32 offset,
856 u32 length, u8 *data)
857{
858 int i;
859 int ret;
860 u32 buf;
861 unsigned long timeout;
862
863 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
864
865 if (buf & OTP_PWR_DN_PWRDN_N_) {
866 /* clear it and wait to be cleared */
867 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
868
869 timeout = jiffies + HZ;
870 do {
871 udelay(1);
872 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
873 if (time_after(jiffies, timeout)) {
874 netdev_warn(dev->net,
875 "timeout on OTP_PWR_DN completion");
876 return -EIO;
877 }
878 } while (buf & OTP_PWR_DN_PWRDN_N_);
879 }
880
881 /* set to BYTE program mode */
882 ret = lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
883
884 for (i = 0; i < length; i++) {
885 ret = lan78xx_write_reg(dev, OTP_ADDR1,
886 ((offset + i) >> 8) & OTP_ADDR1_15_11);
887 ret = lan78xx_write_reg(dev, OTP_ADDR2,
888 ((offset + i) & OTP_ADDR2_10_3));
889 ret = lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
890 ret = lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
891 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
892
893 timeout = jiffies + HZ;
894 do {
895 udelay(1);
896 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
897 if (time_after(jiffies, timeout)) {
898 netdev_warn(dev->net,
899 "Timeout on OTP_STATUS completion");
900 return -EIO;
901 }
902 } while (buf & OTP_STATUS_BUSY_);
903 }
904
905 return 0;
906}
907
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000908static int lan78xx_read_otp(struct lan78xx_net *dev, u32 offset,
909 u32 length, u8 *data)
910{
911 u8 sig;
912 int ret;
913
914 ret = lan78xx_read_raw_otp(dev, 0, 1, &sig);
915
916 if (ret == 0) {
917 if (sig == OTP_INDICATOR_1)
918 offset = offset;
919 else if (sig == OTP_INDICATOR_2)
920 offset += 0x100;
921 else
922 ret = -EINVAL;
923 ret = lan78xx_read_raw_otp(dev, offset, length, data);
924 }
925
926 return ret;
927}
928
929static int lan78xx_dataport_wait_not_busy(struct lan78xx_net *dev)
930{
931 int i, ret;
932
933 for (i = 0; i < 100; i++) {
934 u32 dp_sel;
935
936 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
937 if (unlikely(ret < 0))
938 return -EIO;
939
940 if (dp_sel & DP_SEL_DPRDY_)
941 return 0;
942
943 usleep_range(40, 100);
944 }
945
946 netdev_warn(dev->net, "lan78xx_dataport_wait_not_busy timed out");
947
948 return -EIO;
949}
950
951static int lan78xx_dataport_write(struct lan78xx_net *dev, u32 ram_select,
952 u32 addr, u32 length, u32 *buf)
953{
954 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
955 u32 dp_sel;
956 int i, ret;
957
958 if (usb_autopm_get_interface(dev->intf) < 0)
959 return 0;
960
961 mutex_lock(&pdata->dataport_mutex);
962
963 ret = lan78xx_dataport_wait_not_busy(dev);
964 if (ret < 0)
965 goto done;
966
967 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
968
969 dp_sel &= ~DP_SEL_RSEL_MASK_;
970 dp_sel |= ram_select;
971 ret = lan78xx_write_reg(dev, DP_SEL, dp_sel);
972
973 for (i = 0; i < length; i++) {
974 ret = lan78xx_write_reg(dev, DP_ADDR, addr + i);
975
976 ret = lan78xx_write_reg(dev, DP_DATA, buf[i]);
977
978 ret = lan78xx_write_reg(dev, DP_CMD, DP_CMD_WRITE_);
979
980 ret = lan78xx_dataport_wait_not_busy(dev);
981 if (ret < 0)
982 goto done;
983 }
984
985done:
986 mutex_unlock(&pdata->dataport_mutex);
987 usb_autopm_put_interface(dev->intf);
988
989 return ret;
990}
991
992static void lan78xx_set_addr_filter(struct lan78xx_priv *pdata,
993 int index, u8 addr[ETH_ALEN])
994{
995 u32 temp;
996
997 if ((pdata) && (index > 0) && (index < NUM_OF_MAF)) {
998 temp = addr[3];
999 temp = addr[2] | (temp << 8);
1000 temp = addr[1] | (temp << 8);
1001 temp = addr[0] | (temp << 8);
1002 pdata->pfilter_table[index][1] = temp;
1003 temp = addr[5];
1004 temp = addr[4] | (temp << 8);
1005 temp |= MAF_HI_VALID_ | MAF_HI_TYPE_DST_;
1006 pdata->pfilter_table[index][0] = temp;
1007 }
1008}
1009
1010/* returns hash bit number for given MAC address */
1011static inline u32 lan78xx_hash(char addr[ETH_ALEN])
1012{
1013 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
1014}
1015
1016static void lan78xx_deferred_multicast_write(struct work_struct *param)
1017{
1018 struct lan78xx_priv *pdata =
1019 container_of(param, struct lan78xx_priv, set_multicast);
1020 struct lan78xx_net *dev = pdata->dev;
1021 int i;
1022 int ret;
1023
1024 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
1025 pdata->rfe_ctl);
1026
1027 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, DP_SEL_VHF_VLAN_LEN,
1028 DP_SEL_VHF_HASH_LEN, pdata->mchash_table);
1029
1030 for (i = 1; i < NUM_OF_MAF; i++) {
1031 ret = lan78xx_write_reg(dev, MAF_HI(i), 0);
1032 ret = lan78xx_write_reg(dev, MAF_LO(i),
1033 pdata->pfilter_table[i][1]);
1034 ret = lan78xx_write_reg(dev, MAF_HI(i),
1035 pdata->pfilter_table[i][0]);
1036 }
1037
1038 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1039}
1040
1041static void lan78xx_set_multicast(struct net_device *netdev)
1042{
1043 struct lan78xx_net *dev = netdev_priv(netdev);
1044 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1045 unsigned long flags;
1046 int i;
1047
1048 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
1049
1050 pdata->rfe_ctl &= ~(RFE_CTL_UCAST_EN_ | RFE_CTL_MCAST_EN_ |
1051 RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_);
1052
1053 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
1054 pdata->mchash_table[i] = 0;
1055 /* pfilter_table[0] has own HW address */
1056 for (i = 1; i < NUM_OF_MAF; i++) {
1057 pdata->pfilter_table[i][0] =
1058 pdata->pfilter_table[i][1] = 0;
1059 }
1060
1061 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_;
1062
1063 if (dev->net->flags & IFF_PROMISC) {
1064 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled");
1065 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_ | RFE_CTL_UCAST_EN_;
1066 } else {
1067 if (dev->net->flags & IFF_ALLMULTI) {
1068 netif_dbg(dev, drv, dev->net,
1069 "receive all multicast enabled");
1070 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_;
1071 }
1072 }
1073
1074 if (netdev_mc_count(dev->net)) {
1075 struct netdev_hw_addr *ha;
1076 int i;
1077
1078 netif_dbg(dev, drv, dev->net, "receive multicast hash filter");
1079
1080 pdata->rfe_ctl |= RFE_CTL_DA_PERFECT_;
1081
1082 i = 1;
1083 netdev_for_each_mc_addr(ha, netdev) {
1084 /* set first 32 into Perfect Filter */
1085 if (i < 33) {
1086 lan78xx_set_addr_filter(pdata, i, ha->addr);
1087 } else {
1088 u32 bitnum = lan78xx_hash(ha->addr);
1089
1090 pdata->mchash_table[bitnum / 32] |=
1091 (1 << (bitnum % 32));
1092 pdata->rfe_ctl |= RFE_CTL_MCAST_HASH_;
1093 }
1094 i++;
1095 }
1096 }
1097
1098 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
1099
1100 /* defer register writes to a sleepable context */
1101 schedule_work(&pdata->set_multicast);
1102}
1103
1104static int lan78xx_update_flowcontrol(struct lan78xx_net *dev, u8 duplex,
1105 u16 lcladv, u16 rmtadv)
1106{
1107 u32 flow = 0, fct_flow = 0;
1108 int ret;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001109 u8 cap;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001110
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001111 if (dev->fc_autoneg)
1112 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1113 else
1114 cap = dev->fc_request_control;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001115
1116 if (cap & FLOW_CTRL_TX)
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001117 flow |= (FLOW_CR_TX_FCEN_ | 0xFFFF);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001118
1119 if (cap & FLOW_CTRL_RX)
1120 flow |= FLOW_CR_RX_FCEN_;
1121
1122 if (dev->udev->speed == USB_SPEED_SUPER)
1123 fct_flow = 0x817;
1124 else if (dev->udev->speed == USB_SPEED_HIGH)
1125 fct_flow = 0x211;
1126
1127 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s",
1128 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1129 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1130
1131 ret = lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
1132
1133 /* threshold value should be set before enabling flow */
1134 ret = lan78xx_write_reg(dev, FLOW, flow);
1135
1136 return 0;
1137}
1138
1139static int lan78xx_link_reset(struct lan78xx_net *dev)
1140{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001141 struct phy_device *phydev = dev->net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001142 struct ethtool_link_ksettings ecmd;
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001143 int ladv, radv, ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001144 u32 buf;
1145
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001146 /* clear LAN78xx interrupt status */
1147 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_PHY_INT_);
1148 if (unlikely(ret < 0))
1149 return -EIO;
1150
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001151 phy_read_status(phydev);
1152
1153 if (!phydev->link && dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001154 dev->link_on = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001155
1156 /* reset MAC */
1157 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1158 if (unlikely(ret < 0))
1159 return -EIO;
1160 buf |= MAC_CR_RST_;
1161 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1162 if (unlikely(ret < 0))
1163 return -EIO;
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00001164
Woojung Huh20ff5562016-03-16 22:10:40 +00001165 del_timer(&dev->stat_monitor);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001166 } else if (phydev->link && !dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001167 dev->link_on = true;
1168
Philippe Reynes6e765102016-10-09 12:07:04 +02001169 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001170
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001171 if (dev->udev->speed == USB_SPEED_SUPER) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001172 if (ecmd.base.speed == 1000) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001173 /* disable U2 */
1174 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1175 buf &= ~USB_CFG1_DEV_U2_INIT_EN_;
1176 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1177 /* enable U1 */
1178 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1179 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1180 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1181 } else {
1182 /* enable U1 & U2 */
1183 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1184 buf |= USB_CFG1_DEV_U2_INIT_EN_;
1185 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1186 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1187 }
1188 }
1189
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001190 ladv = phy_read(phydev, MII_ADVERTISE);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001191 if (ladv < 0)
1192 return ladv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001193
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001194 radv = phy_read(phydev, MII_LPA);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001195 if (radv < 0)
1196 return radv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001197
1198 netif_dbg(dev, link, dev->net,
1199 "speed: %u duplex: %d anadv: 0x%04x anlpa: 0x%04x",
Philippe Reynes6e765102016-10-09 12:07:04 +02001200 ecmd.base.speed, ecmd.base.duplex, ladv, radv);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001201
Philippe Reynes6e765102016-10-09 12:07:04 +02001202 ret = lan78xx_update_flowcontrol(dev, ecmd.base.duplex, ladv,
1203 radv);
Woojung Huh20ff5562016-03-16 22:10:40 +00001204
1205 if (!timer_pending(&dev->stat_monitor)) {
1206 dev->delta = 1;
1207 mod_timer(&dev->stat_monitor,
1208 jiffies + STAT_UPDATE_TIMER);
1209 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001210 }
1211
1212 return ret;
1213}
1214
1215/* some work can't be done in tasklets, so we use keventd
1216 *
1217 * NOTE: annoying asymmetry: if it's active, schedule_work() fails,
1218 * but tasklet_schedule() doesn't. hope the failure is rare.
1219 */
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08001220static void lan78xx_defer_kevent(struct lan78xx_net *dev, int work)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001221{
1222 set_bit(work, &dev->flags);
1223 if (!schedule_delayed_work(&dev->wq, 0))
1224 netdev_err(dev->net, "kevent %d may have been dropped\n", work);
1225}
1226
1227static void lan78xx_status(struct lan78xx_net *dev, struct urb *urb)
1228{
1229 u32 intdata;
1230
1231 if (urb->actual_length != 4) {
1232 netdev_warn(dev->net,
1233 "unexpected urb length %d", urb->actual_length);
1234 return;
1235 }
1236
1237 memcpy(&intdata, urb->transfer_buffer, 4);
1238 le32_to_cpus(&intdata);
1239
1240 if (intdata & INT_ENP_PHY_INT) {
1241 netif_dbg(dev, link, dev->net, "PHY INTR: 0x%08x\n", intdata);
Woojung Huhcc89c322016-11-01 20:02:00 +00001242 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
1243
1244 if (dev->domain_data.phyirq > 0)
1245 generic_handle_irq(dev->domain_data.phyirq);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001246 } else
1247 netdev_warn(dev->net,
1248 "unexpected interrupt: 0x%08x\n", intdata);
1249}
1250
1251static int lan78xx_ethtool_get_eeprom_len(struct net_device *netdev)
1252{
1253 return MAX_EEPROM_SIZE;
1254}
1255
1256static int lan78xx_ethtool_get_eeprom(struct net_device *netdev,
1257 struct ethtool_eeprom *ee, u8 *data)
1258{
1259 struct lan78xx_net *dev = netdev_priv(netdev);
1260
1261 ee->magic = LAN78XX_EEPROM_MAGIC;
1262
1263 return lan78xx_read_raw_eeprom(dev, ee->offset, ee->len, data);
1264}
1265
1266static int lan78xx_ethtool_set_eeprom(struct net_device *netdev,
1267 struct ethtool_eeprom *ee, u8 *data)
1268{
1269 struct lan78xx_net *dev = netdev_priv(netdev);
1270
1271 /* Allow entire eeprom update only */
1272 if ((ee->magic == LAN78XX_EEPROM_MAGIC) &&
1273 (ee->offset == 0) &&
1274 (ee->len == 512) &&
1275 (data[0] == EEPROM_INDICATOR))
1276 return lan78xx_write_raw_eeprom(dev, ee->offset, ee->len, data);
1277 else if ((ee->magic == LAN78XX_OTP_MAGIC) &&
1278 (ee->offset == 0) &&
1279 (ee->len == 512) &&
1280 (data[0] == OTP_INDICATOR_1))
Woojung.Huh@microchip.com9fb60662016-01-05 17:29:59 +00001281 return lan78xx_write_raw_otp(dev, ee->offset, ee->len, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001282
1283 return -EINVAL;
1284}
1285
1286static void lan78xx_get_strings(struct net_device *netdev, u32 stringset,
1287 u8 *data)
1288{
1289 if (stringset == ETH_SS_STATS)
1290 memcpy(data, lan78xx_gstrings, sizeof(lan78xx_gstrings));
1291}
1292
1293static int lan78xx_get_sset_count(struct net_device *netdev, int sset)
1294{
1295 if (sset == ETH_SS_STATS)
1296 return ARRAY_SIZE(lan78xx_gstrings);
1297 else
1298 return -EOPNOTSUPP;
1299}
1300
1301static void lan78xx_get_stats(struct net_device *netdev,
1302 struct ethtool_stats *stats, u64 *data)
1303{
1304 struct lan78xx_net *dev = netdev_priv(netdev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001305
Woojung Huh20ff5562016-03-16 22:10:40 +00001306 lan78xx_update_stats(dev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001307
Woojung Huh20ff5562016-03-16 22:10:40 +00001308 mutex_lock(&dev->stats.access_lock);
1309 memcpy(data, &dev->stats.curr_stat, sizeof(dev->stats.curr_stat));
1310 mutex_unlock(&dev->stats.access_lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001311}
1312
1313static void lan78xx_get_wol(struct net_device *netdev,
1314 struct ethtool_wolinfo *wol)
1315{
1316 struct lan78xx_net *dev = netdev_priv(netdev);
1317 int ret;
1318 u32 buf;
1319 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1320
1321 if (usb_autopm_get_interface(dev->intf) < 0)
1322 return;
1323
1324 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
1325 if (unlikely(ret < 0)) {
1326 wol->supported = 0;
1327 wol->wolopts = 0;
1328 } else {
1329 if (buf & USB_CFG_RMT_WKP_) {
1330 wol->supported = WAKE_ALL;
1331 wol->wolopts = pdata->wol;
1332 } else {
1333 wol->supported = 0;
1334 wol->wolopts = 0;
1335 }
1336 }
1337
1338 usb_autopm_put_interface(dev->intf);
1339}
1340
1341static int lan78xx_set_wol(struct net_device *netdev,
1342 struct ethtool_wolinfo *wol)
1343{
1344 struct lan78xx_net *dev = netdev_priv(netdev);
1345 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1346 int ret;
1347
1348 ret = usb_autopm_get_interface(dev->intf);
1349 if (ret < 0)
1350 return ret;
1351
1352 pdata->wol = 0;
1353 if (wol->wolopts & WAKE_UCAST)
1354 pdata->wol |= WAKE_UCAST;
1355 if (wol->wolopts & WAKE_MCAST)
1356 pdata->wol |= WAKE_MCAST;
1357 if (wol->wolopts & WAKE_BCAST)
1358 pdata->wol |= WAKE_BCAST;
1359 if (wol->wolopts & WAKE_MAGIC)
1360 pdata->wol |= WAKE_MAGIC;
1361 if (wol->wolopts & WAKE_PHY)
1362 pdata->wol |= WAKE_PHY;
1363 if (wol->wolopts & WAKE_ARP)
1364 pdata->wol |= WAKE_ARP;
1365
1366 device_set_wakeup_enable(&dev->udev->dev, (bool)wol->wolopts);
1367
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001368 phy_ethtool_set_wol(netdev->phydev, wol);
1369
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001370 usb_autopm_put_interface(dev->intf);
1371
1372 return ret;
1373}
1374
1375static int lan78xx_get_eee(struct net_device *net, struct ethtool_eee *edata)
1376{
1377 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001378 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001379 int ret;
1380 u32 buf;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001381
1382 ret = usb_autopm_get_interface(dev->intf);
1383 if (ret < 0)
1384 return ret;
1385
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001386 ret = phy_ethtool_get_eee(phydev, edata);
1387 if (ret < 0)
1388 goto exit;
1389
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001390 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1391 if (buf & MAC_CR_EEE_EN_) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001392 edata->eee_enabled = true;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001393 edata->eee_active = !!(edata->advertised &
1394 edata->lp_advertised);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001395 edata->tx_lpi_enabled = true;
1396 /* EEE_TX_LPI_REQ_DLY & tx_lpi_timer are same uSec unit */
1397 ret = lan78xx_read_reg(dev, EEE_TX_LPI_REQ_DLY, &buf);
1398 edata->tx_lpi_timer = buf;
1399 } else {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001400 edata->eee_enabled = false;
1401 edata->eee_active = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001402 edata->tx_lpi_enabled = false;
1403 edata->tx_lpi_timer = 0;
1404 }
1405
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001406 ret = 0;
1407exit:
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001408 usb_autopm_put_interface(dev->intf);
1409
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001410 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001411}
1412
1413static int lan78xx_set_eee(struct net_device *net, struct ethtool_eee *edata)
1414{
1415 struct lan78xx_net *dev = netdev_priv(net);
1416 int ret;
1417 u32 buf;
1418
1419 ret = usb_autopm_get_interface(dev->intf);
1420 if (ret < 0)
1421 return ret;
1422
1423 if (edata->eee_enabled) {
1424 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1425 buf |= MAC_CR_EEE_EN_;
1426 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1427
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001428 phy_ethtool_set_eee(net->phydev, edata);
1429
1430 buf = (u32)edata->tx_lpi_timer;
1431 ret = lan78xx_write_reg(dev, EEE_TX_LPI_REQ_DLY, buf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001432 } else {
1433 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1434 buf &= ~MAC_CR_EEE_EN_;
1435 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1436 }
1437
1438 usb_autopm_put_interface(dev->intf);
1439
1440 return 0;
1441}
1442
1443static u32 lan78xx_get_link(struct net_device *net)
1444{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001445 phy_read_status(net->phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001446
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001447 return net->phydev->link;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001448}
1449
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001450static void lan78xx_get_drvinfo(struct net_device *net,
1451 struct ethtool_drvinfo *info)
1452{
1453 struct lan78xx_net *dev = netdev_priv(net);
1454
1455 strncpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1456 strncpy(info->version, DRIVER_VERSION, sizeof(info->version));
1457 usb_make_path(dev->udev, info->bus_info, sizeof(info->bus_info));
1458}
1459
1460static u32 lan78xx_get_msglevel(struct net_device *net)
1461{
1462 struct lan78xx_net *dev = netdev_priv(net);
1463
1464 return dev->msg_enable;
1465}
1466
1467static void lan78xx_set_msglevel(struct net_device *net, u32 level)
1468{
1469 struct lan78xx_net *dev = netdev_priv(net);
1470
1471 dev->msg_enable = level;
1472}
1473
Woojung.Huh@microchip.com758c5c12015-09-16 23:41:14 +00001474static int lan78xx_get_mdix_status(struct net_device *net)
1475{
1476 struct phy_device *phydev = net->phydev;
1477 int buf;
1478
1479 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
1480 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
1481 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
1482
1483 return buf;
1484}
1485
1486static void lan78xx_set_mdix_status(struct net_device *net, __u8 mdix_ctrl)
1487{
1488 struct lan78xx_net *dev = netdev_priv(net);
1489 struct phy_device *phydev = net->phydev;
1490 int buf;
1491
1492 if (mdix_ctrl == ETH_TP_MDI) {
1493 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1494 LAN88XX_EXT_PAGE_SPACE_1);
1495 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
1496 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
1497 phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
1498 buf | LAN88XX_EXT_MODE_CTRL_MDI_);
1499 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1500 LAN88XX_EXT_PAGE_SPACE_0);
1501 } else if (mdix_ctrl == ETH_TP_MDI_X) {
1502 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1503 LAN88XX_EXT_PAGE_SPACE_1);
1504 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
1505 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
1506 phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
1507 buf | LAN88XX_EXT_MODE_CTRL_MDI_X_);
1508 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1509 LAN88XX_EXT_PAGE_SPACE_0);
1510 } else if (mdix_ctrl == ETH_TP_MDI_AUTO) {
1511 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1512 LAN88XX_EXT_PAGE_SPACE_1);
1513 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
1514 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
1515 phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
1516 buf | LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_);
1517 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
1518 LAN88XX_EXT_PAGE_SPACE_0);
1519 }
1520 dev->mdix_ctrl = mdix_ctrl;
1521}
1522
Philippe Reynes6e765102016-10-09 12:07:04 +02001523static int lan78xx_get_link_ksettings(struct net_device *net,
1524 struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001525{
1526 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001527 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001528 int ret;
1529 int buf;
1530
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001531 ret = usb_autopm_get_interface(dev->intf);
1532 if (ret < 0)
1533 return ret;
1534
Philippe Reynes6e765102016-10-09 12:07:04 +02001535 ret = phy_ethtool_ksettings_get(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001536
Woojung.Huh@microchip.com758c5c12015-09-16 23:41:14 +00001537 buf = lan78xx_get_mdix_status(net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001538
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +00001539 buf &= LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
1540 if (buf == LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001541 cmd->base.eth_tp_mdix = ETH_TP_MDI_AUTO;
1542 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +00001543 } else if (buf == LAN88XX_EXT_MODE_CTRL_MDI_) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001544 cmd->base.eth_tp_mdix = ETH_TP_MDI;
1545 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI;
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +00001546 } else if (buf == LAN88XX_EXT_MODE_CTRL_MDI_X_) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001547 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
1548 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_X;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001549 }
1550
1551 usb_autopm_put_interface(dev->intf);
1552
1553 return ret;
1554}
1555
Philippe Reynes6e765102016-10-09 12:07:04 +02001556static int lan78xx_set_link_ksettings(struct net_device *net,
1557 const struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001558{
1559 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001560 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001561 int ret = 0;
1562 int temp;
1563
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001564 ret = usb_autopm_get_interface(dev->intf);
1565 if (ret < 0)
1566 return ret;
1567
Philippe Reynes6e765102016-10-09 12:07:04 +02001568 if (dev->mdix_ctrl != cmd->base.eth_tp_mdix_ctrl)
1569 lan78xx_set_mdix_status(net, cmd->base.eth_tp_mdix_ctrl);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001570
1571 /* change speed & duplex */
Philippe Reynes6e765102016-10-09 12:07:04 +02001572 ret = phy_ethtool_ksettings_set(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001573
Philippe Reynes6e765102016-10-09 12:07:04 +02001574 if (!cmd->base.autoneg) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001575 /* force link down */
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001576 temp = phy_read(phydev, MII_BMCR);
1577 phy_write(phydev, MII_BMCR, temp | BMCR_LOOPBACK);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001578 mdelay(1);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001579 phy_write(phydev, MII_BMCR, temp);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001580 }
1581
1582 usb_autopm_put_interface(dev->intf);
1583
1584 return ret;
1585}
1586
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001587static void lan78xx_get_pause(struct net_device *net,
1588 struct ethtool_pauseparam *pause)
1589{
1590 struct lan78xx_net *dev = netdev_priv(net);
1591 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001592 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001593
Philippe Reynes6e765102016-10-09 12:07:04 +02001594 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001595
1596 pause->autoneg = dev->fc_autoneg;
1597
1598 if (dev->fc_request_control & FLOW_CTRL_TX)
1599 pause->tx_pause = 1;
1600
1601 if (dev->fc_request_control & FLOW_CTRL_RX)
1602 pause->rx_pause = 1;
1603}
1604
1605static int lan78xx_set_pause(struct net_device *net,
1606 struct ethtool_pauseparam *pause)
1607{
1608 struct lan78xx_net *dev = netdev_priv(net);
1609 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001610 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001611 int ret;
1612
Philippe Reynes6e765102016-10-09 12:07:04 +02001613 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001614
Philippe Reynes6e765102016-10-09 12:07:04 +02001615 if (pause->autoneg && !ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001616 ret = -EINVAL;
1617 goto exit;
1618 }
1619
1620 dev->fc_request_control = 0;
1621 if (pause->rx_pause)
1622 dev->fc_request_control |= FLOW_CTRL_RX;
1623
1624 if (pause->tx_pause)
1625 dev->fc_request_control |= FLOW_CTRL_TX;
1626
Philippe Reynes6e765102016-10-09 12:07:04 +02001627 if (ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001628 u32 mii_adv;
Philippe Reynes6e765102016-10-09 12:07:04 +02001629 u32 advertising;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001630
Philippe Reynes6e765102016-10-09 12:07:04 +02001631 ethtool_convert_link_mode_to_legacy_u32(
1632 &advertising, ecmd.link_modes.advertising);
1633
1634 advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001635 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
Philippe Reynes6e765102016-10-09 12:07:04 +02001636 advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
1637
1638 ethtool_convert_legacy_u32_to_link_mode(
1639 ecmd.link_modes.advertising, advertising);
1640
1641 phy_ethtool_ksettings_set(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001642 }
1643
1644 dev->fc_autoneg = pause->autoneg;
1645
1646 ret = 0;
1647exit:
1648 return ret;
1649}
1650
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001651static const struct ethtool_ops lan78xx_ethtool_ops = {
1652 .get_link = lan78xx_get_link,
Florian Fainelli860ce4b2016-11-15 10:06:44 -08001653 .nway_reset = phy_ethtool_nway_reset,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001654 .get_drvinfo = lan78xx_get_drvinfo,
1655 .get_msglevel = lan78xx_get_msglevel,
1656 .set_msglevel = lan78xx_set_msglevel,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001657 .get_eeprom_len = lan78xx_ethtool_get_eeprom_len,
1658 .get_eeprom = lan78xx_ethtool_get_eeprom,
1659 .set_eeprom = lan78xx_ethtool_set_eeprom,
1660 .get_ethtool_stats = lan78xx_get_stats,
1661 .get_sset_count = lan78xx_get_sset_count,
1662 .get_strings = lan78xx_get_strings,
1663 .get_wol = lan78xx_get_wol,
1664 .set_wol = lan78xx_set_wol,
1665 .get_eee = lan78xx_get_eee,
1666 .set_eee = lan78xx_set_eee,
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001667 .get_pauseparam = lan78xx_get_pause,
1668 .set_pauseparam = lan78xx_set_pause,
Philippe Reynes6e765102016-10-09 12:07:04 +02001669 .get_link_ksettings = lan78xx_get_link_ksettings,
1670 .set_link_ksettings = lan78xx_set_link_ksettings,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001671};
1672
1673static int lan78xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
1674{
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001675 if (!netif_running(netdev))
1676 return -EINVAL;
1677
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001678 return phy_mii_ioctl(netdev->phydev, rq, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001679}
1680
1681static void lan78xx_init_mac_address(struct lan78xx_net *dev)
1682{
1683 u32 addr_lo, addr_hi;
1684 int ret;
1685 u8 addr[6];
1686
1687 ret = lan78xx_read_reg(dev, RX_ADDRL, &addr_lo);
1688 ret = lan78xx_read_reg(dev, RX_ADDRH, &addr_hi);
1689
1690 addr[0] = addr_lo & 0xFF;
1691 addr[1] = (addr_lo >> 8) & 0xFF;
1692 addr[2] = (addr_lo >> 16) & 0xFF;
1693 addr[3] = (addr_lo >> 24) & 0xFF;
1694 addr[4] = addr_hi & 0xFF;
1695 addr[5] = (addr_hi >> 8) & 0xFF;
1696
1697 if (!is_valid_ether_addr(addr)) {
1698 /* reading mac address from EEPROM or OTP */
1699 if ((lan78xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
1700 addr) == 0) ||
1701 (lan78xx_read_otp(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
1702 addr) == 0)) {
1703 if (is_valid_ether_addr(addr)) {
1704 /* eeprom values are valid so use them */
1705 netif_dbg(dev, ifup, dev->net,
1706 "MAC address read from EEPROM");
1707 } else {
1708 /* generate random MAC */
1709 random_ether_addr(addr);
1710 netif_dbg(dev, ifup, dev->net,
1711 "MAC address set to random addr");
1712 }
1713
1714 addr_lo = addr[0] | (addr[1] << 8) |
1715 (addr[2] << 16) | (addr[3] << 24);
1716 addr_hi = addr[4] | (addr[5] << 8);
1717
1718 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
1719 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
1720 } else {
1721 /* generate random MAC */
1722 random_ether_addr(addr);
1723 netif_dbg(dev, ifup, dev->net,
1724 "MAC address set to random addr");
1725 }
1726 }
1727
1728 ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
1729 ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
1730
1731 ether_addr_copy(dev->net->dev_addr, addr);
1732}
1733
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001734/* MDIO read and write wrappers for phylib */
1735static int lan78xx_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001736{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001737 struct lan78xx_net *dev = bus->priv;
1738 u32 val, addr;
1739 int ret;
1740
1741 ret = usb_autopm_get_interface(dev->intf);
1742 if (ret < 0)
1743 return ret;
1744
1745 mutex_lock(&dev->phy_mutex);
1746
1747 /* confirm MII not busy */
1748 ret = lan78xx_phy_wait_not_busy(dev);
1749 if (ret < 0)
1750 goto done;
1751
1752 /* set the address, index & direction (read from PHY) */
1753 addr = mii_access(phy_id, idx, MII_READ);
1754 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1755
1756 ret = lan78xx_phy_wait_not_busy(dev);
1757 if (ret < 0)
1758 goto done;
1759
1760 ret = lan78xx_read_reg(dev, MII_DATA, &val);
1761
1762 ret = (int)(val & 0xFFFF);
1763
1764done:
1765 mutex_unlock(&dev->phy_mutex);
1766 usb_autopm_put_interface(dev->intf);
1767 return ret;
1768}
1769
1770static int lan78xx_mdiobus_write(struct mii_bus *bus, int phy_id, int idx,
1771 u16 regval)
1772{
1773 struct lan78xx_net *dev = bus->priv;
1774 u32 val, addr;
1775 int ret;
1776
1777 ret = usb_autopm_get_interface(dev->intf);
1778 if (ret < 0)
1779 return ret;
1780
1781 mutex_lock(&dev->phy_mutex);
1782
1783 /* confirm MII not busy */
1784 ret = lan78xx_phy_wait_not_busy(dev);
1785 if (ret < 0)
1786 goto done;
1787
1788 val = (u32)regval;
1789 ret = lan78xx_write_reg(dev, MII_DATA, val);
1790
1791 /* set the address, index & direction (write to PHY) */
1792 addr = mii_access(phy_id, idx, MII_WRITE);
1793 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1794
1795 ret = lan78xx_phy_wait_not_busy(dev);
1796 if (ret < 0)
1797 goto done;
1798
1799done:
1800 mutex_unlock(&dev->phy_mutex);
1801 usb_autopm_put_interface(dev->intf);
1802 return 0;
1803}
1804
1805static int lan78xx_mdio_init(struct lan78xx_net *dev)
1806{
1807 int ret;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001808
1809 dev->mdiobus = mdiobus_alloc();
1810 if (!dev->mdiobus) {
1811 netdev_err(dev->net, "can't allocate MDIO bus\n");
1812 return -ENOMEM;
1813 }
1814
1815 dev->mdiobus->priv = (void *)dev;
1816 dev->mdiobus->read = lan78xx_mdiobus_read;
1817 dev->mdiobus->write = lan78xx_mdiobus_write;
1818 dev->mdiobus->name = "lan78xx-mdiobus";
1819
1820 snprintf(dev->mdiobus->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
1821 dev->udev->bus->busnum, dev->udev->devnum);
1822
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00001823 switch (dev->chipid) {
1824 case ID_REV_CHIP_ID_7800_:
1825 case ID_REV_CHIP_ID_7850_:
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001826 /* set to internal PHY id */
1827 dev->mdiobus->phy_mask = ~(1 << 1);
1828 break;
1829 }
1830
1831 ret = mdiobus_register(dev->mdiobus);
1832 if (ret) {
1833 netdev_err(dev->net, "can't register MDIO bus\n");
Andrew Lunne7f4dc32016-01-06 20:11:15 +01001834 goto exit1;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001835 }
1836
1837 netdev_dbg(dev->net, "registered mdiobus bus %s\n", dev->mdiobus->id);
1838 return 0;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001839exit1:
1840 mdiobus_free(dev->mdiobus);
1841 return ret;
1842}
1843
1844static void lan78xx_remove_mdio(struct lan78xx_net *dev)
1845{
1846 mdiobus_unregister(dev->mdiobus);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001847 mdiobus_free(dev->mdiobus);
1848}
1849
1850static void lan78xx_link_status_change(struct net_device *net)
1851{
Woojung Huh14437e32016-04-25 22:22:36 +00001852 struct phy_device *phydev = net->phydev;
1853 int ret, temp;
1854
1855 /* At forced 100 F/H mode, chip may fail to set mode correctly
1856 * when cable is switched between long(~50+m) and short one.
1857 * As workaround, set to 10 before setting to 100
1858 * at forced 100 F/H mode.
1859 */
1860 if (!phydev->autoneg && (phydev->speed == 100)) {
1861 /* disable phy interrupt */
1862 temp = phy_read(phydev, LAN88XX_INT_MASK);
1863 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
1864 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1865
1866 temp = phy_read(phydev, MII_BMCR);
1867 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
1868 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
1869 temp |= BMCR_SPEED100;
1870 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
1871
1872 /* clear pending interrupt generated while workaround */
1873 temp = phy_read(phydev, LAN88XX_INT_STS);
1874
1875 /* enable phy interrupt back */
1876 temp = phy_read(phydev, LAN88XX_INT_MASK);
1877 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
1878 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1879 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001880}
1881
Woojung Huhcc89c322016-11-01 20:02:00 +00001882static int irq_map(struct irq_domain *d, unsigned int irq,
1883 irq_hw_number_t hwirq)
1884{
1885 struct irq_domain_data *data = d->host_data;
1886
1887 irq_set_chip_data(irq, data);
1888 irq_set_chip_and_handler(irq, data->irqchip, data->irq_handler);
1889 irq_set_noprobe(irq);
1890
1891 return 0;
1892}
1893
1894static void irq_unmap(struct irq_domain *d, unsigned int irq)
1895{
1896 irq_set_chip_and_handler(irq, NULL, NULL);
1897 irq_set_chip_data(irq, NULL);
1898}
1899
1900static const struct irq_domain_ops chip_domain_ops = {
1901 .map = irq_map,
1902 .unmap = irq_unmap,
1903};
1904
1905static void lan78xx_irq_mask(struct irq_data *irqd)
1906{
1907 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1908
1909 data->irqenable &= ~BIT(irqd_to_hwirq(irqd));
1910}
1911
1912static void lan78xx_irq_unmask(struct irq_data *irqd)
1913{
1914 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1915
1916 data->irqenable |= BIT(irqd_to_hwirq(irqd));
1917}
1918
1919static void lan78xx_irq_bus_lock(struct irq_data *irqd)
1920{
1921 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1922
1923 mutex_lock(&data->irq_lock);
1924}
1925
1926static void lan78xx_irq_bus_sync_unlock(struct irq_data *irqd)
1927{
1928 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1929 struct lan78xx_net *dev =
1930 container_of(data, struct lan78xx_net, domain_data);
1931 u32 buf;
1932 int ret;
1933
1934 /* call register access here because irq_bus_lock & irq_bus_sync_unlock
1935 * are only two callbacks executed in non-atomic contex.
1936 */
1937 ret = lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1938 if (buf != data->irqenable)
1939 ret = lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
1940
1941 mutex_unlock(&data->irq_lock);
1942}
1943
1944static struct irq_chip lan78xx_irqchip = {
1945 .name = "lan78xx-irqs",
1946 .irq_mask = lan78xx_irq_mask,
1947 .irq_unmask = lan78xx_irq_unmask,
1948 .irq_bus_lock = lan78xx_irq_bus_lock,
1949 .irq_bus_sync_unlock = lan78xx_irq_bus_sync_unlock,
1950};
1951
1952static int lan78xx_setup_irq_domain(struct lan78xx_net *dev)
1953{
1954 struct device_node *of_node;
1955 struct irq_domain *irqdomain;
1956 unsigned int irqmap = 0;
1957 u32 buf;
1958 int ret = 0;
1959
1960 of_node = dev->udev->dev.parent->of_node;
1961
1962 mutex_init(&dev->domain_data.irq_lock);
1963
1964 lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1965 dev->domain_data.irqenable = buf;
1966
1967 dev->domain_data.irqchip = &lan78xx_irqchip;
1968 dev->domain_data.irq_handler = handle_simple_irq;
1969
1970 irqdomain = irq_domain_add_simple(of_node, MAX_INT_EP, 0,
1971 &chip_domain_ops, &dev->domain_data);
1972 if (irqdomain) {
1973 /* create mapping for PHY interrupt */
1974 irqmap = irq_create_mapping(irqdomain, INT_EP_PHY);
1975 if (!irqmap) {
1976 irq_domain_remove(irqdomain);
1977
1978 irqdomain = NULL;
1979 ret = -EINVAL;
1980 }
1981 } else {
1982 ret = -EINVAL;
1983 }
1984
1985 dev->domain_data.irqdomain = irqdomain;
1986 dev->domain_data.phyirq = irqmap;
1987
1988 return ret;
1989}
1990
1991static void lan78xx_remove_irq_domain(struct lan78xx_net *dev)
1992{
1993 if (dev->domain_data.phyirq > 0) {
1994 irq_dispose_mapping(dev->domain_data.phyirq);
1995
1996 if (dev->domain_data.irqdomain)
1997 irq_domain_remove(dev->domain_data.irqdomain);
1998 }
1999 dev->domain_data.phyirq = 0;
2000 dev->domain_data.irqdomain = NULL;
2001}
2002
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002003static int lan78xx_phy_init(struct lan78xx_net *dev)
2004{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002005 int ret;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002006 u32 mii_adv;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002007 struct phy_device *phydev = dev->net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002008
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002009 phydev = phy_find_first(dev->mdiobus);
2010 if (!phydev) {
2011 netdev_err(dev->net, "no PHY found\n");
2012 return -EIO;
2013 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002014
Woojung Huhcc89c322016-11-01 20:02:00 +00002015 /* if phyirq is not set, use polling mode in phylib */
2016 if (dev->domain_data.phyirq > 0)
2017 phydev->irq = dev->domain_data.phyirq;
2018 else
2019 phydev->irq = 0;
2020 netdev_dbg(dev->net, "phydev->irq = %d\n", phydev->irq);
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00002021
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002022 ret = phy_connect_direct(dev->net, phydev,
2023 lan78xx_link_status_change,
2024 PHY_INTERFACE_MODE_GMII);
2025 if (ret) {
2026 netdev_err(dev->net, "can't attach PHY to %s\n",
2027 dev->mdiobus->id);
2028 return -EIO;
2029 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002030
2031 /* set to AUTOMDIX */
Woojung.Huh@microchip.com758c5c12015-09-16 23:41:14 +00002032 lan78xx_set_mdix_status(dev->net, ETH_TP_MDI_AUTO);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002033
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002034 /* MAC doesn't support 1000T Half */
2035 phydev->supported &= ~SUPPORTED_1000baseT_Half;
Woojung.Huh@microchip.come270b2d2016-02-25 23:33:09 +00002036
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002037 /* support both flow controls */
2038 dev->fc_request_control = (FLOW_CTRL_RX | FLOW_CTRL_TX);
2039 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
2040 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
2041 phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
2042
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002043 genphy_config_aneg(phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002044
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002045 dev->fc_autoneg = phydev->autoneg;
2046
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002047 phy_start(phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002048
2049 netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
2050
2051 return 0;
2052}
2053
2054static int lan78xx_set_rx_max_frame_length(struct lan78xx_net *dev, int size)
2055{
2056 int ret = 0;
2057 u32 buf;
2058 bool rxenabled;
2059
2060 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2061
2062 rxenabled = ((buf & MAC_RX_RXEN_) != 0);
2063
2064 if (rxenabled) {
2065 buf &= ~MAC_RX_RXEN_;
2066 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2067 }
2068
2069 /* add 4 to size for FCS */
2070 buf &= ~MAC_RX_MAX_SIZE_MASK_;
2071 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
2072
2073 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2074
2075 if (rxenabled) {
2076 buf |= MAC_RX_RXEN_;
2077 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2078 }
2079
2080 return 0;
2081}
2082
2083static int unlink_urbs(struct lan78xx_net *dev, struct sk_buff_head *q)
2084{
2085 struct sk_buff *skb;
2086 unsigned long flags;
2087 int count = 0;
2088
2089 spin_lock_irqsave(&q->lock, flags);
2090 while (!skb_queue_empty(q)) {
2091 struct skb_data *entry;
2092 struct urb *urb;
2093 int ret;
2094
2095 skb_queue_walk(q, skb) {
2096 entry = (struct skb_data *)skb->cb;
2097 if (entry->state != unlink_start)
2098 goto found;
2099 }
2100 break;
2101found:
2102 entry->state = unlink_start;
2103 urb = entry->urb;
2104
2105 /* Get reference count of the URB to avoid it to be
2106 * freed during usb_unlink_urb, which may trigger
2107 * use-after-free problem inside usb_unlink_urb since
2108 * usb_unlink_urb is always racing with .complete
2109 * handler(include defer_bh).
2110 */
2111 usb_get_urb(urb);
2112 spin_unlock_irqrestore(&q->lock, flags);
2113 /* during some PM-driven resume scenarios,
2114 * these (async) unlinks complete immediately
2115 */
2116 ret = usb_unlink_urb(urb);
2117 if (ret != -EINPROGRESS && ret != 0)
2118 netdev_dbg(dev->net, "unlink urb err, %d\n", ret);
2119 else
2120 count++;
2121 usb_put_urb(urb);
2122 spin_lock_irqsave(&q->lock, flags);
2123 }
2124 spin_unlock_irqrestore(&q->lock, flags);
2125 return count;
2126}
2127
2128static int lan78xx_change_mtu(struct net_device *netdev, int new_mtu)
2129{
2130 struct lan78xx_net *dev = netdev_priv(netdev);
2131 int ll_mtu = new_mtu + netdev->hard_header_len;
2132 int old_hard_mtu = dev->hard_mtu;
2133 int old_rx_urb_size = dev->rx_urb_size;
2134 int ret;
2135
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002136 /* no second zero-length packet read wanted after mtu-sized packets */
2137 if ((ll_mtu % dev->maxpacket) == 0)
2138 return -EDOM;
2139
2140 ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
2141
2142 netdev->mtu = new_mtu;
2143
2144 dev->hard_mtu = netdev->mtu + netdev->hard_header_len;
2145 if (dev->rx_urb_size == old_hard_mtu) {
2146 dev->rx_urb_size = dev->hard_mtu;
2147 if (dev->rx_urb_size > old_rx_urb_size) {
2148 if (netif_running(dev->net)) {
2149 unlink_urbs(dev, &dev->rxq);
2150 tasklet_schedule(&dev->bh);
2151 }
2152 }
2153 }
2154
2155 return 0;
2156}
2157
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002158static int lan78xx_set_mac_addr(struct net_device *netdev, void *p)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002159{
2160 struct lan78xx_net *dev = netdev_priv(netdev);
2161 struct sockaddr *addr = p;
2162 u32 addr_lo, addr_hi;
2163 int ret;
2164
2165 if (netif_running(netdev))
2166 return -EBUSY;
2167
2168 if (!is_valid_ether_addr(addr->sa_data))
2169 return -EADDRNOTAVAIL;
2170
2171 ether_addr_copy(netdev->dev_addr, addr->sa_data);
2172
2173 addr_lo = netdev->dev_addr[0] |
2174 netdev->dev_addr[1] << 8 |
2175 netdev->dev_addr[2] << 16 |
2176 netdev->dev_addr[3] << 24;
2177 addr_hi = netdev->dev_addr[4] |
2178 netdev->dev_addr[5] << 8;
2179
2180 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
2181 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
2182
2183 return 0;
2184}
2185
2186/* Enable or disable Rx checksum offload engine */
2187static int lan78xx_set_features(struct net_device *netdev,
2188 netdev_features_t features)
2189{
2190 struct lan78xx_net *dev = netdev_priv(netdev);
2191 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2192 unsigned long flags;
2193 int ret;
2194
2195 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
2196
2197 if (features & NETIF_F_RXCSUM) {
2198 pdata->rfe_ctl |= RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_;
2199 pdata->rfe_ctl |= RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_;
2200 } else {
2201 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_);
2202 pdata->rfe_ctl &= ~(RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_);
2203 }
2204
2205 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2206 pdata->rfe_ctl |= RFE_CTL_VLAN_FILTER_;
2207 else
2208 pdata->rfe_ctl &= ~RFE_CTL_VLAN_FILTER_;
2209
2210 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
2211
2212 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2213
2214 return 0;
2215}
2216
2217static void lan78xx_deferred_vlan_write(struct work_struct *param)
2218{
2219 struct lan78xx_priv *pdata =
2220 container_of(param, struct lan78xx_priv, set_vlan);
2221 struct lan78xx_net *dev = pdata->dev;
2222
2223 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, 0,
2224 DP_SEL_VHF_VLAN_LEN, pdata->vlan_table);
2225}
2226
2227static int lan78xx_vlan_rx_add_vid(struct net_device *netdev,
2228 __be16 proto, u16 vid)
2229{
2230 struct lan78xx_net *dev = netdev_priv(netdev);
2231 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2232 u16 vid_bit_index;
2233 u16 vid_dword_index;
2234
2235 vid_dword_index = (vid >> 5) & 0x7F;
2236 vid_bit_index = vid & 0x1F;
2237
2238 pdata->vlan_table[vid_dword_index] |= (1 << vid_bit_index);
2239
2240 /* defer register writes to a sleepable context */
2241 schedule_work(&pdata->set_vlan);
2242
2243 return 0;
2244}
2245
2246static int lan78xx_vlan_rx_kill_vid(struct net_device *netdev,
2247 __be16 proto, u16 vid)
2248{
2249 struct lan78xx_net *dev = netdev_priv(netdev);
2250 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2251 u16 vid_bit_index;
2252 u16 vid_dword_index;
2253
2254 vid_dword_index = (vid >> 5) & 0x7F;
2255 vid_bit_index = vid & 0x1F;
2256
2257 pdata->vlan_table[vid_dword_index] &= ~(1 << vid_bit_index);
2258
2259 /* defer register writes to a sleepable context */
2260 schedule_work(&pdata->set_vlan);
2261
2262 return 0;
2263}
2264
2265static void lan78xx_init_ltm(struct lan78xx_net *dev)
2266{
2267 int ret;
2268 u32 buf;
2269 u32 regs[6] = { 0 };
2270
2271 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
2272 if (buf & USB_CFG1_LTM_ENABLE_) {
2273 u8 temp[2];
2274 /* Get values from EEPROM first */
2275 if (lan78xx_read_eeprom(dev, 0x3F, 2, temp) == 0) {
2276 if (temp[0] == 24) {
2277 ret = lan78xx_read_raw_eeprom(dev,
2278 temp[1] * 2,
2279 24,
2280 (u8 *)regs);
2281 if (ret < 0)
2282 return;
2283 }
2284 } else if (lan78xx_read_otp(dev, 0x3F, 2, temp) == 0) {
2285 if (temp[0] == 24) {
2286 ret = lan78xx_read_raw_otp(dev,
2287 temp[1] * 2,
2288 24,
2289 (u8 *)regs);
2290 if (ret < 0)
2291 return;
2292 }
2293 }
2294 }
2295
2296 lan78xx_write_reg(dev, LTM_BELT_IDLE0, regs[0]);
2297 lan78xx_write_reg(dev, LTM_BELT_IDLE1, regs[1]);
2298 lan78xx_write_reg(dev, LTM_BELT_ACT0, regs[2]);
2299 lan78xx_write_reg(dev, LTM_BELT_ACT1, regs[3]);
2300 lan78xx_write_reg(dev, LTM_INACTIVE0, regs[4]);
2301 lan78xx_write_reg(dev, LTM_INACTIVE1, regs[5]);
2302}
2303
2304static int lan78xx_reset(struct lan78xx_net *dev)
2305{
2306 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2307 u32 buf;
2308 int ret = 0;
2309 unsigned long timeout;
2310
2311 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2312 buf |= HW_CFG_LRST_;
2313 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2314
2315 timeout = jiffies + HZ;
2316 do {
2317 mdelay(1);
2318 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2319 if (time_after(jiffies, timeout)) {
2320 netdev_warn(dev->net,
2321 "timeout on completion of LiteReset");
2322 return -EIO;
2323 }
2324 } while (buf & HW_CFG_LRST_);
2325
2326 lan78xx_init_mac_address(dev);
2327
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002328 /* save DEVID for later usage */
2329 ret = lan78xx_read_reg(dev, ID_REV, &buf);
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00002330 dev->chipid = (buf & ID_REV_CHIP_ID_MASK_) >> 16;
2331 dev->chiprev = buf & ID_REV_CHIP_REV_MASK_;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002332
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002333 /* Respond to the IN token with a NAK */
2334 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2335 buf |= USB_CFG_BIR_;
2336 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2337
2338 /* Init LTM */
2339 lan78xx_init_ltm(dev);
2340
2341 dev->net->hard_header_len += TX_OVERHEAD;
2342 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
2343
2344 if (dev->udev->speed == USB_SPEED_SUPER) {
2345 buf = DEFAULT_BURST_CAP_SIZE / SS_USB_PKT_SIZE;
2346 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2347 dev->rx_qlen = 4;
2348 dev->tx_qlen = 4;
2349 } else if (dev->udev->speed == USB_SPEED_HIGH) {
2350 buf = DEFAULT_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
2351 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2352 dev->rx_qlen = RX_MAX_QUEUE_MEMORY / dev->rx_urb_size;
2353 dev->tx_qlen = RX_MAX_QUEUE_MEMORY / dev->hard_mtu;
2354 } else {
2355 buf = DEFAULT_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
2356 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2357 dev->rx_qlen = 4;
2358 }
2359
2360 ret = lan78xx_write_reg(dev, BURST_CAP, buf);
2361 ret = lan78xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
2362
2363 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2364 buf |= HW_CFG_MEF_;
2365 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2366
2367 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2368 buf |= USB_CFG_BCE_;
2369 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2370
2371 /* set FIFO sizes */
2372 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
2373 ret = lan78xx_write_reg(dev, FCT_RX_FIFO_END, buf);
2374
2375 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
2376 ret = lan78xx_write_reg(dev, FCT_TX_FIFO_END, buf);
2377
2378 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
2379 ret = lan78xx_write_reg(dev, FLOW, 0);
2380 ret = lan78xx_write_reg(dev, FCT_FLOW, 0);
2381
2382 /* Don't need rfe_ctl_lock during initialisation */
2383 ret = lan78xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
2384 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_ | RFE_CTL_DA_PERFECT_;
2385 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2386
2387 /* Enable or disable checksum offload engines */
2388 lan78xx_set_features(dev->net, dev->net->features);
2389
2390 lan78xx_set_multicast(dev->net);
2391
2392 /* reset PHY */
2393 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2394 buf |= PMT_CTL_PHY_RST_;
2395 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
2396
2397 timeout = jiffies + HZ;
2398 do {
2399 mdelay(1);
2400 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2401 if (time_after(jiffies, timeout)) {
2402 netdev_warn(dev->net, "timeout waiting for PHY Reset");
2403 return -EIO;
2404 }
Woojung.Huh@microchip.com6c595b02015-09-16 23:40:39 +00002405 } while ((buf & PMT_CTL_PHY_RST_) || !(buf & PMT_CTL_READY_));
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002406
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002407 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002408 buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002409 ret = lan78xx_write_reg(dev, MAC_CR, buf);
2410
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002411 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
2412 buf |= MAC_TX_TXEN_;
2413 ret = lan78xx_write_reg(dev, MAC_TX, buf);
2414
2415 ret = lan78xx_read_reg(dev, FCT_TX_CTL, &buf);
2416 buf |= FCT_TX_CTL_EN_;
2417 ret = lan78xx_write_reg(dev, FCT_TX_CTL, buf);
2418
2419 ret = lan78xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
2420
2421 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2422 buf |= MAC_RX_RXEN_;
2423 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2424
2425 ret = lan78xx_read_reg(dev, FCT_RX_CTL, &buf);
2426 buf |= FCT_RX_CTL_EN_;
2427 ret = lan78xx_write_reg(dev, FCT_RX_CTL, buf);
2428
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002429 return 0;
2430}
2431
Woojung Huh20ff5562016-03-16 22:10:40 +00002432static void lan78xx_init_stats(struct lan78xx_net *dev)
2433{
2434 u32 *p;
2435 int i;
2436
2437 /* initialize for stats update
2438 * some counters are 20bits and some are 32bits
2439 */
2440 p = (u32 *)&dev->stats.rollover_max;
2441 for (i = 0; i < (sizeof(dev->stats.rollover_max) / (sizeof(u32))); i++)
2442 p[i] = 0xFFFFF;
2443
2444 dev->stats.rollover_max.rx_unicast_byte_count = 0xFFFFFFFF;
2445 dev->stats.rollover_max.rx_broadcast_byte_count = 0xFFFFFFFF;
2446 dev->stats.rollover_max.rx_multicast_byte_count = 0xFFFFFFFF;
2447 dev->stats.rollover_max.eee_rx_lpi_transitions = 0xFFFFFFFF;
2448 dev->stats.rollover_max.eee_rx_lpi_time = 0xFFFFFFFF;
2449 dev->stats.rollover_max.tx_unicast_byte_count = 0xFFFFFFFF;
2450 dev->stats.rollover_max.tx_broadcast_byte_count = 0xFFFFFFFF;
2451 dev->stats.rollover_max.tx_multicast_byte_count = 0xFFFFFFFF;
2452 dev->stats.rollover_max.eee_tx_lpi_transitions = 0xFFFFFFFF;
2453 dev->stats.rollover_max.eee_tx_lpi_time = 0xFFFFFFFF;
2454
2455 lan78xx_defer_kevent(dev, EVENT_STAT_UPDATE);
2456}
2457
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002458static int lan78xx_open(struct net_device *net)
2459{
2460 struct lan78xx_net *dev = netdev_priv(net);
2461 int ret;
2462
2463 ret = usb_autopm_get_interface(dev->intf);
2464 if (ret < 0)
2465 goto out;
2466
2467 ret = lan78xx_reset(dev);
2468 if (ret < 0)
2469 goto done;
2470
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002471 ret = lan78xx_phy_init(dev);
2472 if (ret < 0)
2473 goto done;
2474
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002475 /* for Link Check */
2476 if (dev->urb_intr) {
2477 ret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);
2478 if (ret < 0) {
2479 netif_err(dev, ifup, dev->net,
2480 "intr submit %d\n", ret);
2481 goto done;
2482 }
2483 }
2484
Woojung Huh20ff5562016-03-16 22:10:40 +00002485 lan78xx_init_stats(dev);
2486
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002487 set_bit(EVENT_DEV_OPEN, &dev->flags);
2488
2489 netif_start_queue(net);
2490
2491 dev->link_on = false;
2492
2493 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
2494done:
2495 usb_autopm_put_interface(dev->intf);
2496
2497out:
2498 return ret;
2499}
2500
2501static void lan78xx_terminate_urbs(struct lan78xx_net *dev)
2502{
2503 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(unlink_wakeup);
2504 DECLARE_WAITQUEUE(wait, current);
2505 int temp;
2506
2507 /* ensure there are no more active urbs */
2508 add_wait_queue(&unlink_wakeup, &wait);
2509 set_current_state(TASK_UNINTERRUPTIBLE);
2510 dev->wait = &unlink_wakeup;
2511 temp = unlink_urbs(dev, &dev->txq) + unlink_urbs(dev, &dev->rxq);
2512
2513 /* maybe wait for deletions to finish. */
2514 while (!skb_queue_empty(&dev->rxq) &&
2515 !skb_queue_empty(&dev->txq) &&
2516 !skb_queue_empty(&dev->done)) {
2517 schedule_timeout(msecs_to_jiffies(UNLINK_TIMEOUT_MS));
2518 set_current_state(TASK_UNINTERRUPTIBLE);
2519 netif_dbg(dev, ifdown, dev->net,
2520 "waited for %d urb completions\n", temp);
2521 }
2522 set_current_state(TASK_RUNNING);
2523 dev->wait = NULL;
2524 remove_wait_queue(&unlink_wakeup, &wait);
2525}
2526
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002527static int lan78xx_stop(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002528{
2529 struct lan78xx_net *dev = netdev_priv(net);
2530
Woojung Huh20ff5562016-03-16 22:10:40 +00002531 if (timer_pending(&dev->stat_monitor))
2532 del_timer_sync(&dev->stat_monitor);
2533
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002534 phy_stop(net->phydev);
2535 phy_disconnect(net->phydev);
2536 net->phydev = NULL;
2537
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002538 clear_bit(EVENT_DEV_OPEN, &dev->flags);
2539 netif_stop_queue(net);
2540
2541 netif_info(dev, ifdown, dev->net,
2542 "stop stats: rx/tx %lu/%lu, errs %lu/%lu\n",
2543 net->stats.rx_packets, net->stats.tx_packets,
2544 net->stats.rx_errors, net->stats.tx_errors);
2545
2546 lan78xx_terminate_urbs(dev);
2547
2548 usb_kill_urb(dev->urb_intr);
2549
2550 skb_queue_purge(&dev->rxq_pause);
2551
2552 /* deferred work (task, timer, softirq) must also stop.
2553 * can't flush_scheduled_work() until we drop rtnl (later),
2554 * else workers could deadlock; so make workers a NOP.
2555 */
2556 dev->flags = 0;
2557 cancel_delayed_work_sync(&dev->wq);
2558 tasklet_kill(&dev->bh);
2559
2560 usb_autopm_put_interface(dev->intf);
2561
2562 return 0;
2563}
2564
2565static int lan78xx_linearize(struct sk_buff *skb)
2566{
2567 return skb_linearize(skb);
2568}
2569
2570static struct sk_buff *lan78xx_tx_prep(struct lan78xx_net *dev,
2571 struct sk_buff *skb, gfp_t flags)
2572{
2573 u32 tx_cmd_a, tx_cmd_b;
2574
2575 if (skb_headroom(skb) < TX_OVERHEAD) {
2576 struct sk_buff *skb2;
2577
2578 skb2 = skb_copy_expand(skb, TX_OVERHEAD, 0, flags);
2579 dev_kfree_skb_any(skb);
2580 skb = skb2;
2581 if (!skb)
2582 return NULL;
2583 }
2584
2585 if (lan78xx_linearize(skb) < 0)
2586 return NULL;
2587
2588 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN_MASK_) | TX_CMD_A_FCS_;
2589
2590 if (skb->ip_summed == CHECKSUM_PARTIAL)
2591 tx_cmd_a |= TX_CMD_A_IPE_ | TX_CMD_A_TPE_;
2592
2593 tx_cmd_b = 0;
2594 if (skb_is_gso(skb)) {
2595 u16 mss = max(skb_shinfo(skb)->gso_size, TX_CMD_B_MSS_MIN_);
2596
2597 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT_) & TX_CMD_B_MSS_MASK_;
2598
2599 tx_cmd_a |= TX_CMD_A_LSO_;
2600 }
2601
2602 if (skb_vlan_tag_present(skb)) {
2603 tx_cmd_a |= TX_CMD_A_IVTG_;
2604 tx_cmd_b |= skb_vlan_tag_get(skb) & TX_CMD_B_VTAG_MASK_;
2605 }
2606
2607 skb_push(skb, 4);
2608 cpu_to_le32s(&tx_cmd_b);
2609 memcpy(skb->data, &tx_cmd_b, 4);
2610
2611 skb_push(skb, 4);
2612 cpu_to_le32s(&tx_cmd_a);
2613 memcpy(skb->data, &tx_cmd_a, 4);
2614
2615 return skb;
2616}
2617
2618static enum skb_state defer_bh(struct lan78xx_net *dev, struct sk_buff *skb,
2619 struct sk_buff_head *list, enum skb_state state)
2620{
2621 unsigned long flags;
2622 enum skb_state old_state;
2623 struct skb_data *entry = (struct skb_data *)skb->cb;
2624
2625 spin_lock_irqsave(&list->lock, flags);
2626 old_state = entry->state;
2627 entry->state = state;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002628
2629 __skb_unlink(skb, list);
2630 spin_unlock(&list->lock);
2631 spin_lock(&dev->done.lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002632
2633 __skb_queue_tail(&dev->done, skb);
2634 if (skb_queue_len(&dev->done) == 1)
2635 tasklet_schedule(&dev->bh);
2636 spin_unlock_irqrestore(&dev->done.lock, flags);
2637
2638 return old_state;
2639}
2640
2641static void tx_complete(struct urb *urb)
2642{
2643 struct sk_buff *skb = (struct sk_buff *)urb->context;
2644 struct skb_data *entry = (struct skb_data *)skb->cb;
2645 struct lan78xx_net *dev = entry->dev;
2646
2647 if (urb->status == 0) {
Woojung Huh74d79a22016-04-25 22:22:32 +00002648 dev->net->stats.tx_packets += entry->num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002649 dev->net->stats.tx_bytes += entry->length;
2650 } else {
2651 dev->net->stats.tx_errors++;
2652
2653 switch (urb->status) {
2654 case -EPIPE:
2655 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
2656 break;
2657
2658 /* software-driven interface shutdown */
2659 case -ECONNRESET:
2660 case -ESHUTDOWN:
2661 break;
2662
2663 case -EPROTO:
2664 case -ETIME:
2665 case -EILSEQ:
2666 netif_stop_queue(dev->net);
2667 break;
2668 default:
2669 netif_dbg(dev, tx_err, dev->net,
2670 "tx err %d\n", entry->urb->status);
2671 break;
2672 }
2673 }
2674
2675 usb_autopm_put_interface_async(dev->intf);
2676
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002677 defer_bh(dev, skb, &dev->txq, tx_done);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002678}
2679
2680static void lan78xx_queue_skb(struct sk_buff_head *list,
2681 struct sk_buff *newsk, enum skb_state state)
2682{
2683 struct skb_data *entry = (struct skb_data *)newsk->cb;
2684
2685 __skb_queue_tail(list, newsk);
2686 entry->state = state;
2687}
2688
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002689static netdev_tx_t
2690lan78xx_start_xmit(struct sk_buff *skb, struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002691{
2692 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002693 struct sk_buff *skb2 = NULL;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002694
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002695 if (skb) {
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002696 skb_tx_timestamp(skb);
2697 skb2 = lan78xx_tx_prep(dev, skb, GFP_ATOMIC);
2698 }
2699
2700 if (skb2) {
2701 skb_queue_tail(&dev->txq_pend, skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002702
Woojung.Huh@microchip.com4b2a4a92016-01-27 22:57:54 +00002703 /* throttle TX patch at slower than SUPER SPEED USB */
2704 if ((dev->udev->speed < USB_SPEED_SUPER) &&
2705 (skb_queue_len(&dev->txq_pend) > 10))
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002706 netif_stop_queue(net);
2707 } else {
2708 netif_dbg(dev, tx_err, dev->net,
2709 "lan78xx_tx_prep return NULL\n");
2710 dev->net->stats.tx_errors++;
2711 dev->net->stats.tx_dropped++;
2712 }
2713
2714 tasklet_schedule(&dev->bh);
2715
2716 return NETDEV_TX_OK;
2717}
2718
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002719static int
2720lan78xx_get_endpoints(struct lan78xx_net *dev, struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002721{
2722 int tmp;
2723 struct usb_host_interface *alt = NULL;
2724 struct usb_host_endpoint *in = NULL, *out = NULL;
2725 struct usb_host_endpoint *status = NULL;
2726
2727 for (tmp = 0; tmp < intf->num_altsetting; tmp++) {
2728 unsigned ep;
2729
2730 in = NULL;
2731 out = NULL;
2732 status = NULL;
2733 alt = intf->altsetting + tmp;
2734
2735 for (ep = 0; ep < alt->desc.bNumEndpoints; ep++) {
2736 struct usb_host_endpoint *e;
2737 int intr = 0;
2738
2739 e = alt->endpoint + ep;
2740 switch (e->desc.bmAttributes) {
2741 case USB_ENDPOINT_XFER_INT:
2742 if (!usb_endpoint_dir_in(&e->desc))
2743 continue;
2744 intr = 1;
2745 /* FALLTHROUGH */
2746 case USB_ENDPOINT_XFER_BULK:
2747 break;
2748 default:
2749 continue;
2750 }
2751 if (usb_endpoint_dir_in(&e->desc)) {
2752 if (!intr && !in)
2753 in = e;
2754 else if (intr && !status)
2755 status = e;
2756 } else {
2757 if (!out)
2758 out = e;
2759 }
2760 }
2761 if (in && out)
2762 break;
2763 }
2764 if (!alt || !in || !out)
2765 return -EINVAL;
2766
2767 dev->pipe_in = usb_rcvbulkpipe(dev->udev,
2768 in->desc.bEndpointAddress &
2769 USB_ENDPOINT_NUMBER_MASK);
2770 dev->pipe_out = usb_sndbulkpipe(dev->udev,
2771 out->desc.bEndpointAddress &
2772 USB_ENDPOINT_NUMBER_MASK);
2773 dev->ep_intr = status;
2774
2775 return 0;
2776}
2777
2778static int lan78xx_bind(struct lan78xx_net *dev, struct usb_interface *intf)
2779{
2780 struct lan78xx_priv *pdata = NULL;
2781 int ret;
2782 int i;
2783
2784 ret = lan78xx_get_endpoints(dev, intf);
2785
2786 dev->data[0] = (unsigned long)kzalloc(sizeof(*pdata), GFP_KERNEL);
2787
2788 pdata = (struct lan78xx_priv *)(dev->data[0]);
2789 if (!pdata) {
2790 netdev_warn(dev->net, "Unable to allocate lan78xx_priv");
2791 return -ENOMEM;
2792 }
2793
2794 pdata->dev = dev;
2795
2796 spin_lock_init(&pdata->rfe_ctl_lock);
2797 mutex_init(&pdata->dataport_mutex);
2798
2799 INIT_WORK(&pdata->set_multicast, lan78xx_deferred_multicast_write);
2800
2801 for (i = 0; i < DP_SEL_VHF_VLAN_LEN; i++)
2802 pdata->vlan_table[i] = 0;
2803
2804 INIT_WORK(&pdata->set_vlan, lan78xx_deferred_vlan_write);
2805
2806 dev->net->features = 0;
2807
2808 if (DEFAULT_TX_CSUM_ENABLE)
2809 dev->net->features |= NETIF_F_HW_CSUM;
2810
2811 if (DEFAULT_RX_CSUM_ENABLE)
2812 dev->net->features |= NETIF_F_RXCSUM;
2813
2814 if (DEFAULT_TSO_CSUM_ENABLE)
2815 dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
2816
2817 dev->net->hw_features = dev->net->features;
2818
Woojung Huhcc89c322016-11-01 20:02:00 +00002819 ret = lan78xx_setup_irq_domain(dev);
2820 if (ret < 0) {
2821 netdev_warn(dev->net,
2822 "lan78xx_setup_irq_domain() failed : %d", ret);
2823 kfree(pdata);
2824 return ret;
2825 }
2826
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002827 /* Init all registers */
2828 ret = lan78xx_reset(dev);
2829
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002830 lan78xx_mdio_init(dev);
2831
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002832 dev->net->flags |= IFF_MULTICAST;
2833
2834 pdata->wol = WAKE_MAGIC;
2835
2836 return 0;
2837}
2838
2839static void lan78xx_unbind(struct lan78xx_net *dev, struct usb_interface *intf)
2840{
2841 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2842
Woojung Huhcc89c322016-11-01 20:02:00 +00002843 lan78xx_remove_irq_domain(dev);
2844
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002845 lan78xx_remove_mdio(dev);
2846
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002847 if (pdata) {
2848 netif_dbg(dev, ifdown, dev->net, "free pdata");
2849 kfree(pdata);
2850 pdata = NULL;
2851 dev->data[0] = 0;
2852 }
2853}
2854
2855static void lan78xx_rx_csum_offload(struct lan78xx_net *dev,
2856 struct sk_buff *skb,
2857 u32 rx_cmd_a, u32 rx_cmd_b)
2858{
2859 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2860 unlikely(rx_cmd_a & RX_CMD_A_ICSM_)) {
2861 skb->ip_summed = CHECKSUM_NONE;
2862 } else {
2863 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT_));
2864 skb->ip_summed = CHECKSUM_COMPLETE;
2865 }
2866}
2867
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002868static void lan78xx_skb_return(struct lan78xx_net *dev, struct sk_buff *skb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002869{
2870 int status;
2871
2872 if (test_bit(EVENT_RX_PAUSED, &dev->flags)) {
2873 skb_queue_tail(&dev->rxq_pause, skb);
2874 return;
2875 }
2876
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002877 dev->net->stats.rx_packets++;
2878 dev->net->stats.rx_bytes += skb->len;
2879
Woojung Huh74d79a22016-04-25 22:22:32 +00002880 skb->protocol = eth_type_trans(skb, dev->net);
2881
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002882 netif_dbg(dev, rx_status, dev->net, "< rx, len %zu, type 0x%x\n",
2883 skb->len + sizeof(struct ethhdr), skb->protocol);
2884 memset(skb->cb, 0, sizeof(struct skb_data));
2885
2886 if (skb_defer_rx_timestamp(skb))
2887 return;
2888
2889 status = netif_rx(skb);
2890 if (status != NET_RX_SUCCESS)
2891 netif_dbg(dev, rx_err, dev->net,
2892 "netif_rx status %d\n", status);
2893}
2894
2895static int lan78xx_rx(struct lan78xx_net *dev, struct sk_buff *skb)
2896{
2897 if (skb->len < dev->net->hard_header_len)
2898 return 0;
2899
2900 while (skb->len > 0) {
2901 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2902 u16 rx_cmd_c;
2903 struct sk_buff *skb2;
2904 unsigned char *packet;
2905
2906 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2907 le32_to_cpus(&rx_cmd_a);
2908 skb_pull(skb, sizeof(rx_cmd_a));
2909
2910 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2911 le32_to_cpus(&rx_cmd_b);
2912 skb_pull(skb, sizeof(rx_cmd_b));
2913
2914 memcpy(&rx_cmd_c, skb->data, sizeof(rx_cmd_c));
2915 le16_to_cpus(&rx_cmd_c);
2916 skb_pull(skb, sizeof(rx_cmd_c));
2917
2918 packet = skb->data;
2919
2920 /* get the packet length */
2921 size = (rx_cmd_a & RX_CMD_A_LEN_MASK_);
2922 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
2923
2924 if (unlikely(rx_cmd_a & RX_CMD_A_RED_)) {
2925 netif_dbg(dev, rx_err, dev->net,
2926 "Error rx_cmd_a=0x%08x", rx_cmd_a);
2927 } else {
2928 /* last frame in this batch */
2929 if (skb->len == size) {
2930 lan78xx_rx_csum_offload(dev, skb,
2931 rx_cmd_a, rx_cmd_b);
2932
2933 skb_trim(skb, skb->len - 4); /* remove fcs */
2934 skb->truesize = size + sizeof(struct sk_buff);
2935
2936 return 1;
2937 }
2938
2939 skb2 = skb_clone(skb, GFP_ATOMIC);
2940 if (unlikely(!skb2)) {
2941 netdev_warn(dev->net, "Error allocating skb");
2942 return 0;
2943 }
2944
2945 skb2->len = size;
2946 skb2->data = packet;
2947 skb_set_tail_pointer(skb2, size);
2948
2949 lan78xx_rx_csum_offload(dev, skb2, rx_cmd_a, rx_cmd_b);
2950
2951 skb_trim(skb2, skb2->len - 4); /* remove fcs */
2952 skb2->truesize = size + sizeof(struct sk_buff);
2953
2954 lan78xx_skb_return(dev, skb2);
2955 }
2956
2957 skb_pull(skb, size);
2958
2959 /* padding bytes before the next frame starts */
2960 if (skb->len)
2961 skb_pull(skb, align_count);
2962 }
2963
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002964 return 1;
2965}
2966
2967static inline void rx_process(struct lan78xx_net *dev, struct sk_buff *skb)
2968{
2969 if (!lan78xx_rx(dev, skb)) {
2970 dev->net->stats.rx_errors++;
2971 goto done;
2972 }
2973
2974 if (skb->len) {
2975 lan78xx_skb_return(dev, skb);
2976 return;
2977 }
2978
2979 netif_dbg(dev, rx_err, dev->net, "drop\n");
2980 dev->net->stats.rx_errors++;
2981done:
2982 skb_queue_tail(&dev->done, skb);
2983}
2984
2985static void rx_complete(struct urb *urb);
2986
2987static int rx_submit(struct lan78xx_net *dev, struct urb *urb, gfp_t flags)
2988{
2989 struct sk_buff *skb;
2990 struct skb_data *entry;
2991 unsigned long lockflags;
2992 size_t size = dev->rx_urb_size;
2993 int ret = 0;
2994
2995 skb = netdev_alloc_skb_ip_align(dev->net, size);
2996 if (!skb) {
2997 usb_free_urb(urb);
2998 return -ENOMEM;
2999 }
3000
3001 entry = (struct skb_data *)skb->cb;
3002 entry->urb = urb;
3003 entry->dev = dev;
3004 entry->length = 0;
3005
3006 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_in,
3007 skb->data, size, rx_complete, skb);
3008
3009 spin_lock_irqsave(&dev->rxq.lock, lockflags);
3010
3011 if (netif_device_present(dev->net) &&
3012 netif_running(dev->net) &&
3013 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3014 !test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3015 ret = usb_submit_urb(urb, GFP_ATOMIC);
3016 switch (ret) {
3017 case 0:
3018 lan78xx_queue_skb(&dev->rxq, skb, rx_start);
3019 break;
3020 case -EPIPE:
3021 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3022 break;
3023 case -ENODEV:
3024 netif_dbg(dev, ifdown, dev->net, "device gone\n");
3025 netif_device_detach(dev->net);
3026 break;
3027 case -EHOSTUNREACH:
3028 ret = -ENOLINK;
3029 break;
3030 default:
3031 netif_dbg(dev, rx_err, dev->net,
3032 "rx submit, %d\n", ret);
3033 tasklet_schedule(&dev->bh);
3034 }
3035 } else {
3036 netif_dbg(dev, ifdown, dev->net, "rx: stopped\n");
3037 ret = -ENOLINK;
3038 }
3039 spin_unlock_irqrestore(&dev->rxq.lock, lockflags);
3040 if (ret) {
3041 dev_kfree_skb_any(skb);
3042 usb_free_urb(urb);
3043 }
3044 return ret;
3045}
3046
3047static void rx_complete(struct urb *urb)
3048{
3049 struct sk_buff *skb = (struct sk_buff *)urb->context;
3050 struct skb_data *entry = (struct skb_data *)skb->cb;
3051 struct lan78xx_net *dev = entry->dev;
3052 int urb_status = urb->status;
3053 enum skb_state state;
3054
3055 skb_put(skb, urb->actual_length);
3056 state = rx_done;
3057 entry->urb = NULL;
3058
3059 switch (urb_status) {
3060 case 0:
3061 if (skb->len < dev->net->hard_header_len) {
3062 state = rx_cleanup;
3063 dev->net->stats.rx_errors++;
3064 dev->net->stats.rx_length_errors++;
3065 netif_dbg(dev, rx_err, dev->net,
3066 "rx length %d\n", skb->len);
3067 }
3068 usb_mark_last_busy(dev->udev);
3069 break;
3070 case -EPIPE:
3071 dev->net->stats.rx_errors++;
3072 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3073 /* FALLTHROUGH */
3074 case -ECONNRESET: /* async unlink */
3075 case -ESHUTDOWN: /* hardware gone */
3076 netif_dbg(dev, ifdown, dev->net,
3077 "rx shutdown, code %d\n", urb_status);
3078 state = rx_cleanup;
3079 entry->urb = urb;
3080 urb = NULL;
3081 break;
3082 case -EPROTO:
3083 case -ETIME:
3084 case -EILSEQ:
3085 dev->net->stats.rx_errors++;
3086 state = rx_cleanup;
3087 entry->urb = urb;
3088 urb = NULL;
3089 break;
3090
3091 /* data overrun ... flush fifo? */
3092 case -EOVERFLOW:
3093 dev->net->stats.rx_over_errors++;
3094 /* FALLTHROUGH */
3095
3096 default:
3097 state = rx_cleanup;
3098 dev->net->stats.rx_errors++;
3099 netif_dbg(dev, rx_err, dev->net, "rx status %d\n", urb_status);
3100 break;
3101 }
3102
3103 state = defer_bh(dev, skb, &dev->rxq, state);
3104
3105 if (urb) {
3106 if (netif_running(dev->net) &&
3107 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3108 state != unlink_start) {
3109 rx_submit(dev, urb, GFP_ATOMIC);
3110 return;
3111 }
3112 usb_free_urb(urb);
3113 }
3114 netif_dbg(dev, rx_err, dev->net, "no read resubmitted\n");
3115}
3116
3117static void lan78xx_tx_bh(struct lan78xx_net *dev)
3118{
3119 int length;
3120 struct urb *urb = NULL;
3121 struct skb_data *entry;
3122 unsigned long flags;
3123 struct sk_buff_head *tqp = &dev->txq_pend;
3124 struct sk_buff *skb, *skb2;
3125 int ret;
3126 int count, pos;
3127 int skb_totallen, pkt_cnt;
3128
3129 skb_totallen = 0;
3130 pkt_cnt = 0;
Woojung Huh74d79a22016-04-25 22:22:32 +00003131 count = 0;
3132 length = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003133 for (skb = tqp->next; pkt_cnt < tqp->qlen; skb = skb->next) {
3134 if (skb_is_gso(skb)) {
3135 if (pkt_cnt) {
3136 /* handle previous packets first */
3137 break;
3138 }
Woojung Huh74d79a22016-04-25 22:22:32 +00003139 count = 1;
3140 length = skb->len - TX_OVERHEAD;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003141 skb2 = skb_dequeue(tqp);
3142 goto gso_skb;
3143 }
3144
3145 if ((skb_totallen + skb->len) > MAX_SINGLE_PACKET_SIZE)
3146 break;
3147 skb_totallen = skb->len + roundup(skb_totallen, sizeof(u32));
3148 pkt_cnt++;
3149 }
3150
3151 /* copy to a single skb */
3152 skb = alloc_skb(skb_totallen, GFP_ATOMIC);
3153 if (!skb)
3154 goto drop;
3155
3156 skb_put(skb, skb_totallen);
3157
3158 for (count = pos = 0; count < pkt_cnt; count++) {
3159 skb2 = skb_dequeue(tqp);
3160 if (skb2) {
Woojung Huh74d79a22016-04-25 22:22:32 +00003161 length += (skb2->len - TX_OVERHEAD);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003162 memcpy(skb->data + pos, skb2->data, skb2->len);
3163 pos += roundup(skb2->len, sizeof(u32));
3164 dev_kfree_skb(skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003165 }
3166 }
3167
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003168gso_skb:
3169 urb = usb_alloc_urb(0, GFP_ATOMIC);
Wolfram Sangd7c4e842016-08-11 23:05:27 +02003170 if (!urb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003171 goto drop;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003172
3173 entry = (struct skb_data *)skb->cb;
3174 entry->urb = urb;
3175 entry->dev = dev;
3176 entry->length = length;
Woojung Huh74d79a22016-04-25 22:22:32 +00003177 entry->num_of_packet = count;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003178
3179 spin_lock_irqsave(&dev->txq.lock, flags);
3180 ret = usb_autopm_get_interface_async(dev->intf);
3181 if (ret < 0) {
3182 spin_unlock_irqrestore(&dev->txq.lock, flags);
3183 goto drop;
3184 }
3185
3186 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_out,
3187 skb->data, skb->len, tx_complete, skb);
3188
3189 if (length % dev->maxpacket == 0) {
3190 /* send USB_ZERO_PACKET */
3191 urb->transfer_flags |= URB_ZERO_PACKET;
3192 }
3193
3194#ifdef CONFIG_PM
3195 /* if this triggers the device is still a sleep */
3196 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3197 /* transmission will be done in resume */
3198 usb_anchor_urb(urb, &dev->deferred);
3199 /* no use to process more packets */
3200 netif_stop_queue(dev->net);
3201 usb_put_urb(urb);
3202 spin_unlock_irqrestore(&dev->txq.lock, flags);
3203 netdev_dbg(dev->net, "Delaying transmission for resumption\n");
3204 return;
3205 }
3206#endif
3207
3208 ret = usb_submit_urb(urb, GFP_ATOMIC);
3209 switch (ret) {
3210 case 0:
Florian Westphal860e9532016-05-03 16:33:13 +02003211 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003212 lan78xx_queue_skb(&dev->txq, skb, tx_start);
3213 if (skb_queue_len(&dev->txq) >= dev->tx_qlen)
3214 netif_stop_queue(dev->net);
3215 break;
3216 case -EPIPE:
3217 netif_stop_queue(dev->net);
3218 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
3219 usb_autopm_put_interface_async(dev->intf);
3220 break;
3221 default:
3222 usb_autopm_put_interface_async(dev->intf);
3223 netif_dbg(dev, tx_err, dev->net,
3224 "tx: submit urb err %d\n", ret);
3225 break;
3226 }
3227
3228 spin_unlock_irqrestore(&dev->txq.lock, flags);
3229
3230 if (ret) {
3231 netif_dbg(dev, tx_err, dev->net, "drop, code %d\n", ret);
3232drop:
3233 dev->net->stats.tx_dropped++;
3234 if (skb)
3235 dev_kfree_skb_any(skb);
3236 usb_free_urb(urb);
3237 } else
3238 netif_dbg(dev, tx_queued, dev->net,
3239 "> tx, len %d, type 0x%x\n", length, skb->protocol);
3240}
3241
3242static void lan78xx_rx_bh(struct lan78xx_net *dev)
3243{
3244 struct urb *urb;
3245 int i;
3246
3247 if (skb_queue_len(&dev->rxq) < dev->rx_qlen) {
3248 for (i = 0; i < 10; i++) {
3249 if (skb_queue_len(&dev->rxq) >= dev->rx_qlen)
3250 break;
3251 urb = usb_alloc_urb(0, GFP_ATOMIC);
3252 if (urb)
3253 if (rx_submit(dev, urb, GFP_ATOMIC) == -ENOLINK)
3254 return;
3255 }
3256
3257 if (skb_queue_len(&dev->rxq) < dev->rx_qlen)
3258 tasklet_schedule(&dev->bh);
3259 }
3260 if (skb_queue_len(&dev->txq) < dev->tx_qlen)
3261 netif_wake_queue(dev->net);
3262}
3263
3264static void lan78xx_bh(unsigned long param)
3265{
3266 struct lan78xx_net *dev = (struct lan78xx_net *)param;
3267 struct sk_buff *skb;
3268 struct skb_data *entry;
3269
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003270 while ((skb = skb_dequeue(&dev->done))) {
3271 entry = (struct skb_data *)(skb->cb);
3272 switch (entry->state) {
3273 case rx_done:
3274 entry->state = rx_cleanup;
3275 rx_process(dev, skb);
3276 continue;
3277 case tx_done:
3278 usb_free_urb(entry->urb);
3279 dev_kfree_skb(skb);
3280 continue;
3281 case rx_cleanup:
3282 usb_free_urb(entry->urb);
3283 dev_kfree_skb(skb);
3284 continue;
3285 default:
3286 netdev_dbg(dev->net, "skb state %d\n", entry->state);
3287 return;
3288 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003289 }
3290
3291 if (netif_device_present(dev->net) && netif_running(dev->net)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00003292 /* reset update timer delta */
3293 if (timer_pending(&dev->stat_monitor) && (dev->delta != 1)) {
3294 dev->delta = 1;
3295 mod_timer(&dev->stat_monitor,
3296 jiffies + STAT_UPDATE_TIMER);
3297 }
3298
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003299 if (!skb_queue_empty(&dev->txq_pend))
3300 lan78xx_tx_bh(dev);
3301
3302 if (!timer_pending(&dev->delay) &&
3303 !test_bit(EVENT_RX_HALT, &dev->flags))
3304 lan78xx_rx_bh(dev);
3305 }
3306}
3307
3308static void lan78xx_delayedwork(struct work_struct *work)
3309{
3310 int status;
3311 struct lan78xx_net *dev;
3312
3313 dev = container_of(work, struct lan78xx_net, wq.work);
3314
3315 if (test_bit(EVENT_TX_HALT, &dev->flags)) {
3316 unlink_urbs(dev, &dev->txq);
3317 status = usb_autopm_get_interface(dev->intf);
3318 if (status < 0)
3319 goto fail_pipe;
3320 status = usb_clear_halt(dev->udev, dev->pipe_out);
3321 usb_autopm_put_interface(dev->intf);
3322 if (status < 0 &&
3323 status != -EPIPE &&
3324 status != -ESHUTDOWN) {
3325 if (netif_msg_tx_err(dev))
3326fail_pipe:
3327 netdev_err(dev->net,
3328 "can't clear tx halt, status %d\n",
3329 status);
3330 } else {
3331 clear_bit(EVENT_TX_HALT, &dev->flags);
3332 if (status != -ESHUTDOWN)
3333 netif_wake_queue(dev->net);
3334 }
3335 }
3336 if (test_bit(EVENT_RX_HALT, &dev->flags)) {
3337 unlink_urbs(dev, &dev->rxq);
3338 status = usb_autopm_get_interface(dev->intf);
3339 if (status < 0)
3340 goto fail_halt;
3341 status = usb_clear_halt(dev->udev, dev->pipe_in);
3342 usb_autopm_put_interface(dev->intf);
3343 if (status < 0 &&
3344 status != -EPIPE &&
3345 status != -ESHUTDOWN) {
3346 if (netif_msg_rx_err(dev))
3347fail_halt:
3348 netdev_err(dev->net,
3349 "can't clear rx halt, status %d\n",
3350 status);
3351 } else {
3352 clear_bit(EVENT_RX_HALT, &dev->flags);
3353 tasklet_schedule(&dev->bh);
3354 }
3355 }
3356
3357 if (test_bit(EVENT_LINK_RESET, &dev->flags)) {
3358 int ret = 0;
3359
3360 clear_bit(EVENT_LINK_RESET, &dev->flags);
3361 status = usb_autopm_get_interface(dev->intf);
3362 if (status < 0)
3363 goto skip_reset;
3364 if (lan78xx_link_reset(dev) < 0) {
3365 usb_autopm_put_interface(dev->intf);
3366skip_reset:
3367 netdev_info(dev->net, "link reset failed (%d)\n",
3368 ret);
3369 } else {
3370 usb_autopm_put_interface(dev->intf);
3371 }
3372 }
Woojung Huh20ff5562016-03-16 22:10:40 +00003373
3374 if (test_bit(EVENT_STAT_UPDATE, &dev->flags)) {
3375 lan78xx_update_stats(dev);
3376
3377 clear_bit(EVENT_STAT_UPDATE, &dev->flags);
3378
3379 mod_timer(&dev->stat_monitor,
3380 jiffies + (STAT_UPDATE_TIMER * dev->delta));
3381
3382 dev->delta = min((dev->delta * 2), 50);
3383 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003384}
3385
3386static void intr_complete(struct urb *urb)
3387{
3388 struct lan78xx_net *dev = urb->context;
3389 int status = urb->status;
3390
3391 switch (status) {
3392 /* success */
3393 case 0:
3394 lan78xx_status(dev, urb);
3395 break;
3396
3397 /* software-driven interface shutdown */
3398 case -ENOENT: /* urb killed */
3399 case -ESHUTDOWN: /* hardware gone */
3400 netif_dbg(dev, ifdown, dev->net,
3401 "intr shutdown, code %d\n", status);
3402 return;
3403
3404 /* NOTE: not throttling like RX/TX, since this endpoint
3405 * already polls infrequently
3406 */
3407 default:
3408 netdev_dbg(dev->net, "intr status %d\n", status);
3409 break;
3410 }
3411
3412 if (!netif_running(dev->net))
3413 return;
3414
3415 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
3416 status = usb_submit_urb(urb, GFP_ATOMIC);
3417 if (status != 0)
3418 netif_err(dev, timer, dev->net,
3419 "intr resubmit --> %d\n", status);
3420}
3421
3422static void lan78xx_disconnect(struct usb_interface *intf)
3423{
3424 struct lan78xx_net *dev;
3425 struct usb_device *udev;
3426 struct net_device *net;
3427
3428 dev = usb_get_intfdata(intf);
3429 usb_set_intfdata(intf, NULL);
3430 if (!dev)
3431 return;
3432
3433 udev = interface_to_usbdev(intf);
3434
3435 net = dev->net;
3436 unregister_netdev(net);
3437
3438 cancel_delayed_work_sync(&dev->wq);
3439
3440 usb_scuttle_anchored_urbs(&dev->deferred);
3441
3442 lan78xx_unbind(dev, intf);
3443
3444 usb_kill_urb(dev->urb_intr);
3445 usb_free_urb(dev->urb_intr);
3446
3447 free_netdev(net);
3448 usb_put_dev(udev);
3449}
3450
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003451static void lan78xx_tx_timeout(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003452{
3453 struct lan78xx_net *dev = netdev_priv(net);
3454
3455 unlink_urbs(dev, &dev->txq);
3456 tasklet_schedule(&dev->bh);
3457}
3458
3459static const struct net_device_ops lan78xx_netdev_ops = {
3460 .ndo_open = lan78xx_open,
3461 .ndo_stop = lan78xx_stop,
3462 .ndo_start_xmit = lan78xx_start_xmit,
3463 .ndo_tx_timeout = lan78xx_tx_timeout,
3464 .ndo_change_mtu = lan78xx_change_mtu,
3465 .ndo_set_mac_address = lan78xx_set_mac_addr,
3466 .ndo_validate_addr = eth_validate_addr,
3467 .ndo_do_ioctl = lan78xx_ioctl,
3468 .ndo_set_rx_mode = lan78xx_set_multicast,
3469 .ndo_set_features = lan78xx_set_features,
3470 .ndo_vlan_rx_add_vid = lan78xx_vlan_rx_add_vid,
3471 .ndo_vlan_rx_kill_vid = lan78xx_vlan_rx_kill_vid,
3472};
3473
Woojung Huh20ff5562016-03-16 22:10:40 +00003474static void lan78xx_stat_monitor(unsigned long param)
3475{
3476 struct lan78xx_net *dev;
3477
3478 dev = (struct lan78xx_net *)param;
3479
3480 lan78xx_defer_kevent(dev, EVENT_STAT_UPDATE);
3481}
3482
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003483static int lan78xx_probe(struct usb_interface *intf,
3484 const struct usb_device_id *id)
3485{
3486 struct lan78xx_net *dev;
3487 struct net_device *netdev;
3488 struct usb_device *udev;
3489 int ret;
3490 unsigned maxp;
3491 unsigned period;
3492 u8 *buf = NULL;
3493
3494 udev = interface_to_usbdev(intf);
3495 udev = usb_get_dev(udev);
3496
3497 ret = -ENOMEM;
3498 netdev = alloc_etherdev(sizeof(struct lan78xx_net));
3499 if (!netdev) {
3500 dev_err(&intf->dev, "Error: OOM\n");
3501 goto out1;
3502 }
3503
3504 /* netdev_printk() needs this */
3505 SET_NETDEV_DEV(netdev, &intf->dev);
3506
3507 dev = netdev_priv(netdev);
3508 dev->udev = udev;
3509 dev->intf = intf;
3510 dev->net = netdev;
3511 dev->msg_enable = netif_msg_init(msg_level, NETIF_MSG_DRV
3512 | NETIF_MSG_PROBE | NETIF_MSG_LINK);
3513
3514 skb_queue_head_init(&dev->rxq);
3515 skb_queue_head_init(&dev->txq);
3516 skb_queue_head_init(&dev->done);
3517 skb_queue_head_init(&dev->rxq_pause);
3518 skb_queue_head_init(&dev->txq_pend);
3519 mutex_init(&dev->phy_mutex);
3520
3521 tasklet_init(&dev->bh, lan78xx_bh, (unsigned long)dev);
3522 INIT_DELAYED_WORK(&dev->wq, lan78xx_delayedwork);
3523 init_usb_anchor(&dev->deferred);
3524
3525 netdev->netdev_ops = &lan78xx_netdev_ops;
3526 netdev->watchdog_timeo = TX_TIMEOUT_JIFFIES;
3527 netdev->ethtool_ops = &lan78xx_ethtool_ops;
3528
Woojung Huh20ff5562016-03-16 22:10:40 +00003529 dev->stat_monitor.function = lan78xx_stat_monitor;
3530 dev->stat_monitor.data = (unsigned long)dev;
3531 dev->delta = 1;
3532 init_timer(&dev->stat_monitor);
3533
3534 mutex_init(&dev->stats.access_lock);
3535
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003536 ret = lan78xx_bind(dev, intf);
3537 if (ret < 0)
3538 goto out2;
3539 strcpy(netdev->name, "eth%d");
3540
3541 if (netdev->mtu > (dev->hard_mtu - netdev->hard_header_len))
3542 netdev->mtu = dev->hard_mtu - netdev->hard_header_len;
3543
Jarod Wilsonf77f0ae2016-10-20 13:55:17 -04003544 /* MTU range: 68 - 9000 */
3545 netdev->max_mtu = MAX_SINGLE_PACKET_SIZE;
3546
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003547 dev->ep_blkin = (intf->cur_altsetting)->endpoint + 0;
3548 dev->ep_blkout = (intf->cur_altsetting)->endpoint + 1;
3549 dev->ep_intr = (intf->cur_altsetting)->endpoint + 2;
3550
3551 dev->pipe_in = usb_rcvbulkpipe(udev, BULK_IN_PIPE);
3552 dev->pipe_out = usb_sndbulkpipe(udev, BULK_OUT_PIPE);
3553
3554 dev->pipe_intr = usb_rcvintpipe(dev->udev,
3555 dev->ep_intr->desc.bEndpointAddress &
3556 USB_ENDPOINT_NUMBER_MASK);
3557 period = dev->ep_intr->desc.bInterval;
3558
3559 maxp = usb_maxpacket(dev->udev, dev->pipe_intr, 0);
3560 buf = kmalloc(maxp, GFP_KERNEL);
3561 if (buf) {
3562 dev->urb_intr = usb_alloc_urb(0, GFP_KERNEL);
3563 if (!dev->urb_intr) {
3564 kfree(buf);
3565 goto out3;
3566 } else {
3567 usb_fill_int_urb(dev->urb_intr, dev->udev,
3568 dev->pipe_intr, buf, maxp,
3569 intr_complete, dev, period);
3570 }
3571 }
3572
3573 dev->maxpacket = usb_maxpacket(dev->udev, dev->pipe_out, 1);
3574
3575 /* driver requires remote-wakeup capability during autosuspend. */
3576 intf->needs_remote_wakeup = 1;
3577
3578 ret = register_netdev(netdev);
3579 if (ret != 0) {
3580 netif_err(dev, probe, netdev, "couldn't register the device\n");
3581 goto out2;
3582 }
3583
3584 usb_set_intfdata(intf, dev);
3585
3586 ret = device_set_wakeup_enable(&udev->dev, true);
3587
3588 /* Default delay of 2sec has more overhead than advantage.
3589 * Set to 10sec as default.
3590 */
3591 pm_runtime_set_autosuspend_delay(&udev->dev,
3592 DEFAULT_AUTOSUSPEND_DELAY);
3593
3594 return 0;
3595
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003596out3:
3597 lan78xx_unbind(dev, intf);
3598out2:
3599 free_netdev(netdev);
3600out1:
3601 usb_put_dev(udev);
3602
3603 return ret;
3604}
3605
3606static u16 lan78xx_wakeframe_crc16(const u8 *buf, int len)
3607{
3608 const u16 crc16poly = 0x8005;
3609 int i;
3610 u16 bit, crc, msb;
3611 u8 data;
3612
3613 crc = 0xFFFF;
3614 for (i = 0; i < len; i++) {
3615 data = *buf++;
3616 for (bit = 0; bit < 8; bit++) {
3617 msb = crc >> 15;
3618 crc <<= 1;
3619
3620 if (msb ^ (u16)(data & 1)) {
3621 crc ^= crc16poly;
3622 crc |= (u16)0x0001U;
3623 }
3624 data >>= 1;
3625 }
3626 }
3627
3628 return crc;
3629}
3630
3631static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)
3632{
3633 u32 buf;
3634 int ret;
3635 int mask_index;
3636 u16 crc;
3637 u32 temp_wucsr;
3638 u32 temp_pmt_ctl;
3639 const u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };
3640 const u8 ipv6_multicast[3] = { 0x33, 0x33 };
3641 const u8 arp_type[2] = { 0x08, 0x06 };
3642
3643 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3644 buf &= ~MAC_TX_TXEN_;
3645 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3646 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3647 buf &= ~MAC_RX_RXEN_;
3648 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3649
3650 ret = lan78xx_write_reg(dev, WUCSR, 0);
3651 ret = lan78xx_write_reg(dev, WUCSR2, 0);
3652 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3653
3654 temp_wucsr = 0;
3655
3656 temp_pmt_ctl = 0;
3657 ret = lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);
3658 temp_pmt_ctl &= ~PMT_CTL_RES_CLR_WKP_EN_;
3659 temp_pmt_ctl |= PMT_CTL_RES_CLR_WKP_STS_;
3660
3661 for (mask_index = 0; mask_index < NUM_OF_WUF_CFG; mask_index++)
3662 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
3663
3664 mask_index = 0;
3665 if (wol & WAKE_PHY) {
3666 temp_pmt_ctl |= PMT_CTL_PHY_WAKE_EN_;
3667
3668 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3669 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3670 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3671 }
3672 if (wol & WAKE_MAGIC) {
3673 temp_wucsr |= WUCSR_MPEN_;
3674
3675 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3676 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3677 temp_pmt_ctl |= PMT_CTL_SUS_MODE_3_;
3678 }
3679 if (wol & WAKE_BCAST) {
3680 temp_wucsr |= WUCSR_BCST_EN_;
3681
3682 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3683 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3684 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3685 }
3686 if (wol & WAKE_MCAST) {
3687 temp_wucsr |= WUCSR_WAKE_EN_;
3688
3689 /* set WUF_CFG & WUF_MASK for IPv4 Multicast */
3690 crc = lan78xx_wakeframe_crc16(ipv4_multicast, 3);
3691 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3692 WUF_CFGX_EN_ |
3693 WUF_CFGX_TYPE_MCAST_ |
3694 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3695 (crc & WUF_CFGX_CRC16_MASK_));
3696
3697 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
3698 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3699 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3700 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3701 mask_index++;
3702
3703 /* for IPv6 Multicast */
3704 crc = lan78xx_wakeframe_crc16(ipv6_multicast, 2);
3705 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3706 WUF_CFGX_EN_ |
3707 WUF_CFGX_TYPE_MCAST_ |
3708 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3709 (crc & WUF_CFGX_CRC16_MASK_));
3710
3711 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
3712 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3713 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3714 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3715 mask_index++;
3716
3717 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3718 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3719 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3720 }
3721 if (wol & WAKE_UCAST) {
3722 temp_wucsr |= WUCSR_PFDA_EN_;
3723
3724 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3725 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3726 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3727 }
3728 if (wol & WAKE_ARP) {
3729 temp_wucsr |= WUCSR_WAKE_EN_;
3730
3731 /* set WUF_CFG & WUF_MASK
3732 * for packettype (offset 12,13) = ARP (0x0806)
3733 */
3734 crc = lan78xx_wakeframe_crc16(arp_type, 2);
3735 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3736 WUF_CFGX_EN_ |
3737 WUF_CFGX_TYPE_ALL_ |
3738 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3739 (crc & WUF_CFGX_CRC16_MASK_));
3740
3741 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
3742 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3743 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3744 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3745 mask_index++;
3746
3747 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3748 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3749 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3750 }
3751
3752 ret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);
3753
3754 /* when multiple WOL bits are set */
3755 if (hweight_long((unsigned long)wol) > 1) {
3756 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3757 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3758 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3759 }
3760 ret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
3761
3762 /* clear WUPS */
3763 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3764 buf |= PMT_CTL_WUPS_MASK_;
3765 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3766
3767 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3768 buf |= MAC_RX_RXEN_;
3769 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3770
3771 return 0;
3772}
3773
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003774static int lan78xx_suspend(struct usb_interface *intf, pm_message_t message)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003775{
3776 struct lan78xx_net *dev = usb_get_intfdata(intf);
3777 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
3778 u32 buf;
3779 int ret;
3780 int event;
3781
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003782 event = message.event;
3783
3784 if (!dev->suspend_count++) {
3785 spin_lock_irq(&dev->txq.lock);
3786 /* don't autosuspend while transmitting */
3787 if ((skb_queue_len(&dev->txq) ||
3788 skb_queue_len(&dev->txq_pend)) &&
3789 PMSG_IS_AUTO(message)) {
3790 spin_unlock_irq(&dev->txq.lock);
3791 ret = -EBUSY;
3792 goto out;
3793 } else {
3794 set_bit(EVENT_DEV_ASLEEP, &dev->flags);
3795 spin_unlock_irq(&dev->txq.lock);
3796 }
3797
3798 /* stop TX & RX */
3799 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3800 buf &= ~MAC_TX_TXEN_;
3801 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3802 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3803 buf &= ~MAC_RX_RXEN_;
3804 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3805
3806 /* empty out the rx and queues */
3807 netif_device_detach(dev->net);
3808 lan78xx_terminate_urbs(dev);
3809 usb_kill_urb(dev->urb_intr);
3810
3811 /* reattach */
3812 netif_device_attach(dev->net);
3813 }
3814
3815 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00003816 del_timer(&dev->stat_monitor);
3817
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003818 if (PMSG_IS_AUTO(message)) {
3819 /* auto suspend (selective suspend) */
3820 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3821 buf &= ~MAC_TX_TXEN_;
3822 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3823 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3824 buf &= ~MAC_RX_RXEN_;
3825 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3826
3827 ret = lan78xx_write_reg(dev, WUCSR, 0);
3828 ret = lan78xx_write_reg(dev, WUCSR2, 0);
3829 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3830
3831 /* set goodframe wakeup */
3832 ret = lan78xx_read_reg(dev, WUCSR, &buf);
3833
3834 buf |= WUCSR_RFE_WAKE_EN_;
3835 buf |= WUCSR_STORE_WAKE_;
3836
3837 ret = lan78xx_write_reg(dev, WUCSR, buf);
3838
3839 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3840
3841 buf &= ~PMT_CTL_RES_CLR_WKP_EN_;
3842 buf |= PMT_CTL_RES_CLR_WKP_STS_;
3843
3844 buf |= PMT_CTL_PHY_WAKE_EN_;
3845 buf |= PMT_CTL_WOL_EN_;
3846 buf &= ~PMT_CTL_SUS_MODE_MASK_;
3847 buf |= PMT_CTL_SUS_MODE_3_;
3848
3849 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3850
3851 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3852
3853 buf |= PMT_CTL_WUPS_MASK_;
3854
3855 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3856
3857 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3858 buf |= MAC_RX_RXEN_;
3859 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3860 } else {
3861 lan78xx_set_suspend(dev, pdata->wol);
3862 }
3863 }
3864
Woojung.Huh@microchip.com49d28b562015-09-25 21:13:48 +00003865 ret = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003866out:
3867 return ret;
3868}
3869
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003870static int lan78xx_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003871{
3872 struct lan78xx_net *dev = usb_get_intfdata(intf);
3873 struct sk_buff *skb;
3874 struct urb *res;
3875 int ret;
3876 u32 buf;
3877
Woojung Huh20ff5562016-03-16 22:10:40 +00003878 if (!timer_pending(&dev->stat_monitor)) {
3879 dev->delta = 1;
3880 mod_timer(&dev->stat_monitor,
3881 jiffies + STAT_UPDATE_TIMER);
3882 }
3883
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003884 if (!--dev->suspend_count) {
3885 /* resume interrupt URBs */
3886 if (dev->urb_intr && test_bit(EVENT_DEV_OPEN, &dev->flags))
3887 usb_submit_urb(dev->urb_intr, GFP_NOIO);
3888
3889 spin_lock_irq(&dev->txq.lock);
3890 while ((res = usb_get_from_anchor(&dev->deferred))) {
3891 skb = (struct sk_buff *)res->context;
3892 ret = usb_submit_urb(res, GFP_ATOMIC);
3893 if (ret < 0) {
3894 dev_kfree_skb_any(skb);
3895 usb_free_urb(res);
3896 usb_autopm_put_interface_async(dev->intf);
3897 } else {
Florian Westphal860e9532016-05-03 16:33:13 +02003898 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003899 lan78xx_queue_skb(&dev->txq, skb, tx_start);
3900 }
3901 }
3902
3903 clear_bit(EVENT_DEV_ASLEEP, &dev->flags);
3904 spin_unlock_irq(&dev->txq.lock);
3905
3906 if (test_bit(EVENT_DEV_OPEN, &dev->flags)) {
3907 if (!(skb_queue_len(&dev->txq) >= dev->tx_qlen))
3908 netif_start_queue(dev->net);
3909 tasklet_schedule(&dev->bh);
3910 }
3911 }
3912
3913 ret = lan78xx_write_reg(dev, WUCSR2, 0);
3914 ret = lan78xx_write_reg(dev, WUCSR, 0);
3915 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3916
3917 ret = lan78xx_write_reg(dev, WUCSR2, WUCSR2_NS_RCD_ |
3918 WUCSR2_ARP_RCD_ |
3919 WUCSR2_IPV6_TCPSYN_RCD_ |
3920 WUCSR2_IPV4_TCPSYN_RCD_);
3921
3922 ret = lan78xx_write_reg(dev, WUCSR, WUCSR_EEE_TX_WAKE_ |
3923 WUCSR_EEE_RX_WAKE_ |
3924 WUCSR_PFDA_FR_ |
3925 WUCSR_RFE_WAKE_FR_ |
3926 WUCSR_WUFR_ |
3927 WUCSR_MPR_ |
3928 WUCSR_BCST_FR_);
3929
3930 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3931 buf |= MAC_TX_TXEN_;
3932 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3933
3934 return 0;
3935}
3936
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003937static int lan78xx_reset_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003938{
3939 struct lan78xx_net *dev = usb_get_intfdata(intf);
3940
3941 lan78xx_reset(dev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00003942
3943 lan78xx_phy_init(dev);
3944
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003945 return lan78xx_resume(intf);
3946}
3947
3948static const struct usb_device_id products[] = {
3949 {
3950 /* LAN7800 USB Gigabit Ethernet Device */
3951 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7800_USB_PRODUCT_ID),
3952 },
3953 {
3954 /* LAN7850 USB Gigabit Ethernet Device */
3955 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7850_USB_PRODUCT_ID),
3956 },
3957 {},
3958};
3959MODULE_DEVICE_TABLE(usb, products);
3960
3961static struct usb_driver lan78xx_driver = {
3962 .name = DRIVER_NAME,
3963 .id_table = products,
3964 .probe = lan78xx_probe,
3965 .disconnect = lan78xx_disconnect,
3966 .suspend = lan78xx_suspend,
3967 .resume = lan78xx_resume,
3968 .reset_resume = lan78xx_reset_resume,
3969 .supports_autosuspend = 1,
3970 .disable_hub_initiated_lpm = 1,
3971};
3972
3973module_usb_driver(lan78xx_driver);
3974
3975MODULE_AUTHOR(DRIVER_AUTHOR);
3976MODULE_DESCRIPTION(DRIVER_DESC);
3977MODULE_LICENSE("GPL");