blob: 2733fb5938a4225bce099f437c60dbbe24b867a3 [file] [log] [blame]
Jason Baron7ee40b82014-07-04 13:48:32 +02001/*
2 * Intel E3-1200
3 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
4 *
5 * Support for the E3-1200 processor family. Heavily based on previous
6 * Intel EDAC drivers.
7 *
8 * Since the DRAM controller is on the cpu chip, we can use its PCI device
9 * id to identify these processors.
10 *
11 * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/)
12 *
13 * 0108: Xeon E3-1200 Processor Family DRAM Controller
14 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
15 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
16 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
17 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
18 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
19 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
Jason Baron953dee92016-05-06 11:18:47 -040020 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
Jason Baron7ee40b82014-07-04 13:48:32 +020021 *
22 * Based on Intel specification:
23 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
24 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
25 *
26 * According to the above datasheet (p.16):
27 * "
28 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
29 * requests that cross a DW boundary.
30 * "
31 *
32 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
33 * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
34 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
35 */
36
37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/pci.h>
40#include <linux/pci_ids.h>
41#include <linux/edac.h>
42
Christoph Hellwig2f8e2c82015-08-28 09:27:14 +020043#include <linux/io-64-nonatomic-lo-hi.h>
Mauro Carvalho Chehab78d88e82016-10-29 15:16:34 -020044#include "edac_module.h"
Jason Baron7ee40b82014-07-04 13:48:32 +020045
46#define IE31200_REVISION "1.0"
47#define EDAC_MOD_STR "ie31200_edac"
48
49#define ie31200_printk(level, fmt, arg...) \
50 edac_printk(level, "ie31200", fmt, ##arg)
51
52#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
53#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
54#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
55#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
56#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
57#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
58#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
Jason Baron953dee92016-05-06 11:18:47 -040059#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
Jason Baron7ee40b82014-07-04 13:48:32 +020060
61#define IE31200_DIMMS 4
62#define IE31200_RANKS 8
63#define IE31200_RANKS_PER_CHANNEL 4
64#define IE31200_DIMMS_PER_CHANNEL 2
65#define IE31200_CHANNELS 2
66
67/* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
68#define IE31200_MCHBAR_LOW 0x48
69#define IE31200_MCHBAR_HIGH 0x4c
70#define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
71#define IE31200_MMR_WINDOW_SIZE BIT(15)
72
73/*
74 * Error Status Register (16b)
75 *
76 * 15 reserved
77 * 14 Isochronous TBWRR Run Behind FIFO Full
78 * (ITCV)
79 * 13 Isochronous TBWRR Run Behind FIFO Put
80 * (ITSTV)
81 * 12 reserved
82 * 11 MCH Thermal Sensor Event
83 * for SMI/SCI/SERR (GTSE)
84 * 10 reserved
85 * 9 LOCK to non-DRAM Memory Flag (LCKF)
86 * 8 reserved
87 * 7 DRAM Throttle Flag (DTF)
88 * 6:2 reserved
89 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
90 * 0 Single-bit DRAM ECC Error Flag (DSERR)
91 */
92#define IE31200_ERRSTS 0xc8
93#define IE31200_ERRSTS_UE BIT(1)
94#define IE31200_ERRSTS_CE BIT(0)
95#define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
96
97/*
98 * Channel 0 ECC Error Log (64b)
99 *
100 * 63:48 Error Column Address (ERRCOL)
101 * 47:32 Error Row Address (ERRROW)
102 * 31:29 Error Bank Address (ERRBANK)
103 * 28:27 Error Rank Address (ERRRANK)
104 * 26:24 reserved
105 * 23:16 Error Syndrome (ERRSYND)
106 * 15: 2 reserved
107 * 1 Multiple Bit Error Status (MERRSTS)
108 * 0 Correctable Error Status (CERRSTS)
109 */
Jason Baron953dee92016-05-06 11:18:47 -0400110
Jason Baron7ee40b82014-07-04 13:48:32 +0200111#define IE31200_C0ECCERRLOG 0x40c8
112#define IE31200_C1ECCERRLOG 0x44c8
Jason Baron953dee92016-05-06 11:18:47 -0400113#define IE31200_C0ECCERRLOG_SKL 0x4048
114#define IE31200_C1ECCERRLOG_SKL 0x4448
Jason Baron7ee40b82014-07-04 13:48:32 +0200115#define IE31200_ECCERRLOG_CE BIT(0)
116#define IE31200_ECCERRLOG_UE BIT(1)
117#define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
118#define IE31200_ECCERRLOG_RANK_SHIFT 27
119#define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
120#define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
121
122#define IE31200_ECCERRLOG_SYNDROME(log) \
123 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
124 IE31200_ECCERRLOG_SYNDROME_SHIFT)
125
126#define IE31200_CAPID0 0xe4
127#define IE31200_CAPID0_PDCD BIT(4)
128#define IE31200_CAPID0_DDPCD BIT(6)
129#define IE31200_CAPID0_ECC BIT(1)
130
Jason Baron953dee92016-05-06 11:18:47 -0400131#define IE31200_MAD_DIMM_0_OFFSET 0x5004
132#define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
133#define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
134#define IE31200_MAD_DIMM_A_RANK BIT(17)
135#define IE31200_MAD_DIMM_A_RANK_SHIFT 17
136#define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
137#define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
138#define IE31200_MAD_DIMM_A_WIDTH BIT(19)
139#define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
140#define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
141#define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
Jason Baron7ee40b82014-07-04 13:48:32 +0200142
Jason Baron953dee92016-05-06 11:18:47 -0400143/* Skylake reports 1GB increments, everything else is 256MB */
144#define IE31200_PAGES(n, skl) \
145 (n << (28 + (2 * skl) - PAGE_SHIFT))
Jason Baron7ee40b82014-07-04 13:48:32 +0200146
147static int nr_channels;
148
149struct ie31200_priv {
150 void __iomem *window;
Jason Baron953dee92016-05-06 11:18:47 -0400151 void __iomem *c0errlog;
152 void __iomem *c1errlog;
Jason Baron7ee40b82014-07-04 13:48:32 +0200153};
154
155enum ie31200_chips {
156 IE31200 = 0,
157};
158
159struct ie31200_dev_info {
160 const char *ctl_name;
161};
162
163struct ie31200_error_info {
164 u16 errsts;
165 u16 errsts2;
166 u64 eccerrlog[IE31200_CHANNELS];
167};
168
169static const struct ie31200_dev_info ie31200_devs[] = {
170 [IE31200] = {
171 .ctl_name = "IE31200"
172 },
173};
174
175struct dimm_data {
Jason Baron953dee92016-05-06 11:18:47 -0400176 u8 size; /* in multiples of 256MB, except Skylake is 1GB */
Jason Baron7ee40b82014-07-04 13:48:32 +0200177 u8 dual_rank : 1,
Jason Baron953dee92016-05-06 11:18:47 -0400178 x16_width : 2; /* 0 means x8 width */
Jason Baron7ee40b82014-07-04 13:48:32 +0200179};
180
181static int how_many_channels(struct pci_dev *pdev)
182{
183 int n_channels;
184 unsigned char capid0_2b; /* 2nd byte of CAPID0 */
185
186 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
187
188 /* check PDCD: Dual Channel Disable */
189 if (capid0_2b & IE31200_CAPID0_PDCD) {
190 edac_dbg(0, "In single channel mode\n");
191 n_channels = 1;
192 } else {
193 edac_dbg(0, "In dual channel mode\n");
194 n_channels = 2;
195 }
196
197 /* check DDPCD - check if both channels are filled */
198 if (capid0_2b & IE31200_CAPID0_DDPCD)
199 edac_dbg(0, "2 DIMMS per channel disabled\n");
200 else
201 edac_dbg(0, "2 DIMMS per channel enabled\n");
202
203 return n_channels;
204}
205
206static bool ecc_capable(struct pci_dev *pdev)
207{
208 unsigned char capid0_4b; /* 4th byte of CAPID0 */
209
210 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
211 if (capid0_4b & IE31200_CAPID0_ECC)
212 return false;
213 return true;
214}
215
Jason Baron953dee92016-05-06 11:18:47 -0400216static int eccerrlog_row(u64 log)
Jason Baron7ee40b82014-07-04 13:48:32 +0200217{
Jason Baron953dee92016-05-06 11:18:47 -0400218 return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
219 IE31200_ECCERRLOG_RANK_SHIFT);
Jason Baron7ee40b82014-07-04 13:48:32 +0200220}
221
222static void ie31200_clear_error_info(struct mem_ctl_info *mci)
223{
224 /*
225 * Clear any error bits.
226 * (Yes, we really clear bits by writing 1 to them.)
227 */
228 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
229 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
230}
231
232static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
233 struct ie31200_error_info *info)
234{
235 struct pci_dev *pdev;
236 struct ie31200_priv *priv = mci->pvt_info;
Jason Baron7ee40b82014-07-04 13:48:32 +0200237
238 pdev = to_pci_dev(mci->pdev);
239
240 /*
241 * This is a mess because there is no atomic way to read all the
242 * registers at once and the registers can transition from CE being
243 * overwritten by UE.
244 */
245 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
246 if (!(info->errsts & IE31200_ERRSTS_BITS))
247 return;
248
Jason Baron953dee92016-05-06 11:18:47 -0400249 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
Jason Baron7ee40b82014-07-04 13:48:32 +0200250 if (nr_channels == 2)
Jason Baron953dee92016-05-06 11:18:47 -0400251 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
Jason Baron7ee40b82014-07-04 13:48:32 +0200252
253 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
254
255 /*
256 * If the error is the same for both reads then the first set
257 * of reads is valid. If there is a change then there is a CE
258 * with no info and the second set of reads is valid and
259 * should be UE info.
260 */
261 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
Jason Baron953dee92016-05-06 11:18:47 -0400262 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
Jason Baron7ee40b82014-07-04 13:48:32 +0200263 if (nr_channels == 2)
264 info->eccerrlog[1] =
Jason Baron953dee92016-05-06 11:18:47 -0400265 lo_hi_readq(priv->c1errlog);
Jason Baron7ee40b82014-07-04 13:48:32 +0200266 }
267
268 ie31200_clear_error_info(mci);
269}
270
271static void ie31200_process_error_info(struct mem_ctl_info *mci,
272 struct ie31200_error_info *info)
273{
274 int channel;
275 u64 log;
276
277 if (!(info->errsts & IE31200_ERRSTS_BITS))
278 return;
279
280 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
281 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
282 -1, -1, -1, "UE overwrote CE", "");
283 info->errsts = info->errsts2;
284 }
285
286 for (channel = 0; channel < nr_channels; channel++) {
287 log = info->eccerrlog[channel];
288 if (log & IE31200_ECCERRLOG_UE) {
289 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
290 0, 0, 0,
Jason Baron953dee92016-05-06 11:18:47 -0400291 eccerrlog_row(log),
Jason Baron7ee40b82014-07-04 13:48:32 +0200292 channel, -1,
293 "ie31200 UE", "");
294 } else if (log & IE31200_ECCERRLOG_CE) {
295 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
296 0, 0,
297 IE31200_ECCERRLOG_SYNDROME(log),
Jason Baron953dee92016-05-06 11:18:47 -0400298 eccerrlog_row(log),
Jason Baron7ee40b82014-07-04 13:48:32 +0200299 channel, -1,
300 "ie31200 CE", "");
301 }
302 }
303}
304
305static void ie31200_check(struct mem_ctl_info *mci)
306{
307 struct ie31200_error_info info;
308
309 edac_dbg(1, "MC%d\n", mci->mc_idx);
310 ie31200_get_and_clear_error_info(mci, &info);
311 ie31200_process_error_info(mci, &info);
312}
313
314static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
315{
316 union {
317 u64 mchbar;
318 struct {
319 u32 mchbar_low;
320 u32 mchbar_high;
321 };
322 } u;
323 void __iomem *window;
324
325 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
326 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
327 u.mchbar &= IE31200_MCHBAR_MASK;
328
329 if (u.mchbar != (resource_size_t)u.mchbar) {
330 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
331 (unsigned long long)u.mchbar);
332 return NULL;
333 }
334
335 window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
336 if (!window)
337 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
338 (unsigned long long)u.mchbar);
339
340 return window;
341}
342
Jason Baron953dee92016-05-06 11:18:47 -0400343static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
344 int chan)
345{
346 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
347 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
348 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
349 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
350}
351
352static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
353 int chan)
354{
355 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
356 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
357 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
358}
359
360static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
361 bool skl)
362{
363 if (skl)
364 __skl_populate_dimm_info(dd, addr_decode, chan);
365 else
366 __populate_dimm_info(dd, addr_decode, chan);
367}
368
369
Jason Baron7ee40b82014-07-04 13:48:32 +0200370static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
371{
Jason Baron78fd4d12014-07-09 21:13:07 +0000372 int i, j, ret;
Jason Baron7ee40b82014-07-04 13:48:32 +0200373 struct mem_ctl_info *mci = NULL;
374 struct edac_mc_layer layers[2];
375 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
376 void __iomem *window;
377 struct ie31200_priv *priv;
Jason Baron953dee92016-05-06 11:18:47 -0400378 u32 addr_decode, mad_offset;
379 bool skl = (pdev->device == PCI_DEVICE_ID_INTEL_IE31200_HB_8);
Jason Baron7ee40b82014-07-04 13:48:32 +0200380
381 edac_dbg(0, "MC:\n");
382
383 if (!ecc_capable(pdev)) {
384 ie31200_printk(KERN_INFO, "No ECC support\n");
385 return -ENODEV;
386 }
387
Jason Baron78fd4d12014-07-09 21:13:07 +0000388 nr_channels = how_many_channels(pdev);
389 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
390 layers[0].size = IE31200_DIMMS;
391 layers[0].is_virt_csrow = true;
392 layers[1].type = EDAC_MC_LAYER_CHANNEL;
393 layers[1].size = nr_channels;
394 layers[1].is_virt_csrow = false;
395 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
396 sizeof(struct ie31200_priv));
397 if (!mci)
398 return -ENOMEM;
399
Jason Baron7ee40b82014-07-04 13:48:32 +0200400 window = ie31200_map_mchbar(pdev);
Jason Baron78fd4d12014-07-09 21:13:07 +0000401 if (!window) {
402 ret = -ENODEV;
403 goto fail_free;
404 }
405
406 edac_dbg(3, "MC: init mci\n");
407 mci->pdev = &pdev->dev;
Jason Baron953dee92016-05-06 11:18:47 -0400408 if (skl)
409 mci->mtype_cap = MEM_FLAG_DDR4;
410 else
411 mci->mtype_cap = MEM_FLAG_DDR3;
Jason Baron78fd4d12014-07-09 21:13:07 +0000412 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
413 mci->edac_cap = EDAC_FLAG_SECDED;
414 mci->mod_name = EDAC_MOD_STR;
415 mci->mod_ver = IE31200_REVISION;
416 mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
417 mci->dev_name = pci_name(pdev);
418 mci->edac_check = ie31200_check;
419 mci->ctl_page_to_phys = NULL;
420 priv = mci->pvt_info;
421 priv->window = window;
Jason Baron953dee92016-05-06 11:18:47 -0400422 if (skl) {
423 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
424 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
425 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
426 } else {
427 priv->c0errlog = window + IE31200_C0ECCERRLOG;
428 priv->c1errlog = window + IE31200_C1ECCERRLOG;
429 mad_offset = IE31200_MAD_DIMM_0_OFFSET;
430 }
Jason Baron7ee40b82014-07-04 13:48:32 +0200431
432 /* populate DIMM info */
433 for (i = 0; i < IE31200_CHANNELS; i++) {
Jason Baron953dee92016-05-06 11:18:47 -0400434 addr_decode = readl(window + mad_offset +
Jason Baron7ee40b82014-07-04 13:48:32 +0200435 (i * 4));
436 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
437 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
Jason Baron953dee92016-05-06 11:18:47 -0400438 populate_dimm_info(&dimm_info[i][j], addr_decode, j,
439 skl);
Jason Baron7ee40b82014-07-04 13:48:32 +0200440 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
441 dimm_info[i][j].size,
442 dimm_info[i][j].dual_rank,
443 dimm_info[i][j].x16_width);
444 }
445 }
446
Jason Baron7ee40b82014-07-04 13:48:32 +0200447 /*
448 * The dram rank boundary (DRB) reg values are boundary addresses
449 * for each DRAM rank with a granularity of 64MB. DRB regs are
450 * cumulative; the last one will contain the total memory
451 * contained in all ranks.
452 */
453 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
454 for (j = 0; j < IE31200_CHANNELS; j++) {
455 struct dimm_info *dimm;
456 unsigned long nr_pages;
457
Jason Baron953dee92016-05-06 11:18:47 -0400458 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
Jason Baron7ee40b82014-07-04 13:48:32 +0200459 if (nr_pages == 0)
460 continue;
461
462 if (dimm_info[j][i].dual_rank) {
463 nr_pages = nr_pages / 2;
464 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
465 mci->n_layers, (i * 2) + 1,
466 j, 0);
467 dimm->nr_pages = nr_pages;
468 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
469 dimm->grain = 8; /* just a guess */
Jason Baron953dee92016-05-06 11:18:47 -0400470 if (skl)
471 dimm->mtype = MEM_DDR4;
472 else
473 dimm->mtype = MEM_DDR3;
Jason Baron7ee40b82014-07-04 13:48:32 +0200474 dimm->dtype = DEV_UNKNOWN;
475 dimm->edac_mode = EDAC_UNKNOWN;
476 }
477 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
478 mci->n_layers, i * 2, j, 0);
479 dimm->nr_pages = nr_pages;
480 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
481 dimm->grain = 8; /* same guess */
Jason Baron953dee92016-05-06 11:18:47 -0400482 if (skl)
483 dimm->mtype = MEM_DDR4;
484 else
485 dimm->mtype = MEM_DDR3;
Jason Baron7ee40b82014-07-04 13:48:32 +0200486 dimm->dtype = DEV_UNKNOWN;
487 dimm->edac_mode = EDAC_UNKNOWN;
488 }
489 }
490
491 ie31200_clear_error_info(mci);
492
Jason Baron7ee40b82014-07-04 13:48:32 +0200493 if (edac_mc_add_mc(mci)) {
494 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
Jason Baron78fd4d12014-07-09 21:13:07 +0000495 ret = -ENODEV;
496 goto fail_unmap;
Jason Baron7ee40b82014-07-04 13:48:32 +0200497 }
498
499 /* get this far and it's successful */
500 edac_dbg(3, "MC: success\n");
501 return 0;
502
Jason Baron7ee40b82014-07-04 13:48:32 +0200503fail_unmap:
504 iounmap(window);
505
Jason Baron78fd4d12014-07-09 21:13:07 +0000506fail_free:
507 edac_mc_free(mci);
508
509 return ret;
Jason Baron7ee40b82014-07-04 13:48:32 +0200510}
511
512static int ie31200_init_one(struct pci_dev *pdev,
513 const struct pci_device_id *ent)
514{
515 edac_dbg(0, "MC:\n");
516
517 if (pci_enable_device(pdev) < 0)
518 return -EIO;
519
520 return ie31200_probe1(pdev, ent->driver_data);
521}
522
523static void ie31200_remove_one(struct pci_dev *pdev)
524{
525 struct mem_ctl_info *mci;
526 struct ie31200_priv *priv;
527
528 edac_dbg(0, "\n");
529 mci = edac_mc_del_mc(&pdev->dev);
530 if (!mci)
531 return;
532 priv = mci->pvt_info;
533 iounmap(priv->window);
534 edac_mc_free(mci);
535}
536
537static const struct pci_device_id ie31200_pci_tbl[] = {
538 {
539 PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
540 IE31200},
541 {
542 PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
543 IE31200},
544 {
545 PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
546 IE31200},
547 {
548 PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
549 IE31200},
550 {
551 PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
552 IE31200},
553 {
554 PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
555 IE31200},
556 {
557 PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
558 IE31200},
559 {
Jason Baron953dee92016-05-06 11:18:47 -0400560 PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
561 IE31200},
562 {
Jason Baron7ee40b82014-07-04 13:48:32 +0200563 0,
564 } /* 0 terminated list. */
565};
566MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
567
568static struct pci_driver ie31200_driver = {
569 .name = EDAC_MOD_STR,
570 .probe = ie31200_init_one,
571 .remove = ie31200_remove_one,
572 .id_table = ie31200_pci_tbl,
573};
574
575static int __init ie31200_init(void)
576{
577 edac_dbg(3, "MC:\n");
578 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
579 opstate_init();
580
581 return pci_register_driver(&ie31200_driver);
582}
583
584static void __exit ie31200_exit(void)
585{
586 edac_dbg(3, "MC:\n");
587 pci_unregister_driver(&ie31200_driver);
588}
589
590module_init(ie31200_init);
591module_exit(ie31200_exit);
592
593MODULE_LICENSE("GPL");
594MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
595MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");