blob: ab9298395264c0172d1714fc07565c82c3adc670 [file] [log] [blame]
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +01001/*
2 * clkgen-mux.c: ST GEN-MUX Clock driver
3 *
4 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
5 *
6 * Authors: Stephen Gallimore <stephen.gallimore@st.com>
7 * Pankaj Dev <pankaj.dev@st.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/slab.h>
17#include <linux/of_address.h>
18#include <linux/clk-provider.h>
19
20static DEFINE_SPINLOCK(clkgena_divmux_lock);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +010021static DEFINE_SPINLOCK(clkgenf_lock);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +010022
23static const char ** __init clkgen_mux_get_parents(struct device_node *np,
24 int *num_parents)
25{
26 const char **parents;
27 int nparents, i;
28
Geert Uytterhoeven0a652392015-05-29 11:25:46 +020029 nparents = of_clk_get_parent_count(np);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +010030 if (WARN_ON(nparents <= 0))
31 return ERR_PTR(-EINVAL);
32
Stephen Boyd86665d22015-07-07 18:30:05 -070033 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +010034 if (!parents)
35 return ERR_PTR(-ENOMEM);
36
37 for (i = 0; i < nparents; i++)
38 parents[i] = of_clk_get_parent_name(np, i);
39
40 *num_parents = nparents;
41 return parents;
42}
43
44/**
45 * DOC: Clock mux with a programmable divider on each of its three inputs.
46 * The mux has an input setting which effectively gates its output.
47 *
48 * Traits of this clock:
49 * prepare - clk_(un)prepare only ensures parent is (un)prepared
50 * enable - clk_enable and clk_disable are functional & control gating
51 * rate - set rate is supported
52 * parent - set/get parent
53 */
54
55#define NUM_INPUTS 3
56
57struct clkgena_divmux {
58 struct clk_hw hw;
59 /* Subclassed mux and divider structures */
60 struct clk_mux mux;
61 struct clk_divider div[NUM_INPUTS];
62 /* Enable/running feedback register bits for each input */
63 void __iomem *feedback_reg[NUM_INPUTS];
64 int feedback_bit_idx;
65
66 u8 muxsel;
67};
68
69#define to_clkgena_divmux(_hw) container_of(_hw, struct clkgena_divmux, hw)
70
71struct clkgena_divmux_data {
72 int num_outputs;
73 int mux_offset;
74 int mux_offset2;
75 int mux_start_bit;
76 int div_offsets[NUM_INPUTS];
77 int fb_offsets[NUM_INPUTS];
78 int fb_start_bit_idx;
79};
80
81#define CKGAX_CLKOPSRC_SWITCH_OFF 0x3
82
83static int clkgena_divmux_is_running(struct clkgena_divmux *mux)
84{
85 u32 regval = readl(mux->feedback_reg[mux->muxsel]);
86 u32 running = regval & BIT(mux->feedback_bit_idx);
87 return !!running;
88}
89
90static int clkgena_divmux_enable(struct clk_hw *hw)
91{
92 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
93 struct clk_hw *mux_hw = &genamux->mux.hw;
94 unsigned long timeout;
95 int ret = 0;
96
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010097 __clk_hw_set_clk(mux_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +010098
99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
100 if (ret)
101 return ret;
102
103 timeout = jiffies + msecs_to_jiffies(10);
104
105 while (!clkgena_divmux_is_running(genamux)) {
106 if (time_after(jiffies, timeout))
107 return -ETIMEDOUT;
108 cpu_relax();
109 }
110
111 return 0;
112}
113
114static void clkgena_divmux_disable(struct clk_hw *hw)
115{
116 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
117 struct clk_hw *mux_hw = &genamux->mux.hw;
118
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100119 __clk_hw_set_clk(mux_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100120
121 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
122}
123
124static int clkgena_divmux_is_enabled(struct clk_hw *hw)
125{
126 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
127 struct clk_hw *mux_hw = &genamux->mux.hw;
128
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100129 __clk_hw_set_clk(mux_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100130
131 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
132}
133
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700134static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100135{
136 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
137 struct clk_hw *mux_hw = &genamux->mux.hw;
138
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100139 __clk_hw_set_clk(mux_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100140
141 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
142 if ((s8)genamux->muxsel < 0) {
143 pr_debug("%s: %s: Invalid parent, setting to default.\n",
144 __func__, __clk_get_name(hw->clk));
145 genamux->muxsel = 0;
146 }
147
148 return genamux->muxsel;
149}
150
151static int clkgena_divmux_set_parent(struct clk_hw *hw, u8 index)
152{
153 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
154
155 if (index >= CKGAX_CLKOPSRC_SWITCH_OFF)
156 return -EINVAL;
157
158 genamux->muxsel = index;
159
160 /*
161 * If the mux is already enabled, call enable directly to set the
162 * new mux position and wait for it to start running again. Otherwise
163 * do nothing.
164 */
165 if (clkgena_divmux_is_enabled(hw))
166 clkgena_divmux_enable(hw);
167
168 return 0;
169}
170
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700171static unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100172 unsigned long parent_rate)
173{
174 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
176
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100177 __clk_hw_set_clk(div_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100178
179 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
180}
181
182static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
183 unsigned long parent_rate)
184{
185 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
187
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100188 __clk_hw_set_clk(div_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100189
190 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
191}
192
193static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
194 unsigned long *prate)
195{
196 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
198
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100199 __clk_hw_set_clk(div_hw, hw);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100200
201 return clk_divider_ops.round_rate(div_hw, rate, prate);
202}
203
204static const struct clk_ops clkgena_divmux_ops = {
205 .enable = clkgena_divmux_enable,
206 .disable = clkgena_divmux_disable,
207 .is_enabled = clkgena_divmux_is_enabled,
208 .get_parent = clkgena_divmux_get_parent,
209 .set_parent = clkgena_divmux_set_parent,
210 .round_rate = clkgena_divmux_round_rate,
211 .recalc_rate = clkgena_divmux_recalc_rate,
212 .set_rate = clkgena_divmux_set_rate,
213};
214
215/**
216 * clk_register_genamux - register a genamux clock with the clock framework
217 */
Stephen Boyd86665d22015-07-07 18:30:05 -0700218static struct clk * __init clk_register_genamux(const char *name,
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100219 const char **parent_names, u8 num_parents,
220 void __iomem *reg,
221 const struct clkgena_divmux_data *muxdata,
222 u32 idx)
223{
224 /*
225 * Fixed constants across all ClockgenA variants
226 */
227 const int mux_width = 2;
228 const int divider_width = 5;
229 struct clkgena_divmux *genamux;
230 struct clk *clk;
231 struct clk_init_data init;
232 int i;
233
234 genamux = kzalloc(sizeof(*genamux), GFP_KERNEL);
235 if (!genamux)
236 return ERR_PTR(-ENOMEM);
237
238 init.name = name;
239 init.ops = &clkgena_divmux_ops;
Pankaj Dev18fee452015-06-23 16:09:24 +0200240 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100241 init.parent_names = parent_names;
242 init.num_parents = num_parents;
243
244 genamux->mux.lock = &clkgena_divmux_lock;
245 genamux->mux.mask = BIT(mux_width) - 1;
246 genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width);
247 if (genamux->mux.shift > 31) {
248 /*
249 * We have spilled into the second mux register so
250 * adjust the register address and the bit shift accordingly
251 */
252 genamux->mux.reg = reg + muxdata->mux_offset2;
253 genamux->mux.shift -= 32;
254 } else {
255 genamux->mux.reg = reg + muxdata->mux_offset;
256 }
257
258 for (i = 0; i < NUM_INPUTS; i++) {
259 /*
260 * Divider config for each input
261 */
262 void __iomem *divbase = reg + muxdata->div_offsets[i];
263 genamux->div[i].width = divider_width;
264 genamux->div[i].reg = divbase + (idx * sizeof(u32));
265
266 /*
267 * Mux enabled/running feedback register for each input.
268 */
269 genamux->feedback_reg[i] = reg + muxdata->fb_offsets[i];
270 }
271
272 genamux->feedback_bit_idx = muxdata->fb_start_bit_idx + idx;
273 genamux->hw.init = &init;
274
275 clk = clk_register(NULL, &genamux->hw);
276 if (IS_ERR(clk)) {
277 kfree(genamux);
278 goto err;
279 }
280
281 pr_debug("%s: parent %s rate %lu\n",
282 __clk_get_name(clk),
283 __clk_get_name(clk_get_parent(clk)),
284 clk_get_rate(clk));
285err:
286 return clk;
287}
288
289static struct clkgena_divmux_data st_divmux_c65hs = {
290 .num_outputs = 4,
291 .mux_offset = 0x14,
292 .mux_start_bit = 0,
293 .div_offsets = { 0x800, 0x900, 0xb00 },
294 .fb_offsets = { 0x18, 0x1c, 0x20 },
295 .fb_start_bit_idx = 0,
296};
297
298static struct clkgena_divmux_data st_divmux_c65ls = {
299 .num_outputs = 14,
300 .mux_offset = 0x14,
301 .mux_offset2 = 0x24,
302 .mux_start_bit = 8,
303 .div_offsets = { 0x810, 0xa10, 0xb10 },
304 .fb_offsets = { 0x18, 0x1c, 0x20 },
305 .fb_start_bit_idx = 4,
306};
307
308static struct clkgena_divmux_data st_divmux_c32odf0 = {
309 .num_outputs = 8,
310 .mux_offset = 0x1c,
311 .mux_start_bit = 0,
312 .div_offsets = { 0x800, 0x900, 0xa60 },
313 .fb_offsets = { 0x2c, 0x24, 0x28 },
314 .fb_start_bit_idx = 0,
315};
316
317static struct clkgena_divmux_data st_divmux_c32odf1 = {
318 .num_outputs = 8,
319 .mux_offset = 0x1c,
320 .mux_start_bit = 16,
321 .div_offsets = { 0x820, 0x980, 0xa80 },
322 .fb_offsets = { 0x2c, 0x24, 0x28 },
323 .fb_start_bit_idx = 8,
324};
325
326static struct clkgena_divmux_data st_divmux_c32odf2 = {
327 .num_outputs = 8,
328 .mux_offset = 0x20,
329 .mux_start_bit = 0,
330 .div_offsets = { 0x840, 0xa20, 0xb10 },
331 .fb_offsets = { 0x2c, 0x24, 0x28 },
332 .fb_start_bit_idx = 16,
333};
334
335static struct clkgena_divmux_data st_divmux_c32odf3 = {
336 .num_outputs = 8,
337 .mux_offset = 0x20,
338 .mux_start_bit = 16,
339 .div_offsets = { 0x860, 0xa40, 0xb30 },
340 .fb_offsets = { 0x2c, 0x24, 0x28 },
341 .fb_start_bit_idx = 24,
342};
343
Fabian Frederickf3755732015-03-31 20:50:42 +0200344static const struct of_device_id clkgena_divmux_of_match[] = {
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100345 {
346 .compatible = "st,clkgena-divmux-c65-hs",
347 .data = &st_divmux_c65hs,
348 },
349 {
350 .compatible = "st,clkgena-divmux-c65-ls",
351 .data = &st_divmux_c65ls,
352 },
353 {
354 .compatible = "st,clkgena-divmux-c32-odf0",
355 .data = &st_divmux_c32odf0,
356 },
357 {
358 .compatible = "st,clkgena-divmux-c32-odf1",
359 .data = &st_divmux_c32odf1,
360 },
361 {
362 .compatible = "st,clkgena-divmux-c32-odf2",
363 .data = &st_divmux_c32odf2,
364 },
365 {
366 .compatible = "st,clkgena-divmux-c32-odf3",
367 .data = &st_divmux_c32odf3,
368 },
369 {}
370};
371
Stephen Boyd86665d22015-07-07 18:30:05 -0700372static void __iomem * __init clkgen_get_register_base(struct device_node *np)
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100373{
374 struct device_node *pnode;
Stephen Boyd86665d22015-07-07 18:30:05 -0700375 void __iomem *reg;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100376
377 pnode = of_get_parent(np);
378 if (!pnode)
379 return NULL;
380
381 reg = of_iomap(pnode, 0);
382
383 of_node_put(pnode);
384 return reg;
385}
386
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700387static void __init st_of_clkgena_divmux_setup(struct device_node *np)
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100388{
389 const struct of_device_id *match;
390 const struct clkgena_divmux_data *data;
391 struct clk_onecell_data *clk_data;
392 void __iomem *reg;
393 const char **parents;
394 int num_parents = 0, i;
395
396 match = of_match_node(clkgena_divmux_of_match, np);
397 if (WARN_ON(!match))
398 return;
399
Stephen Boyd86665d22015-07-07 18:30:05 -0700400 data = match->data;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100401
402 reg = clkgen_get_register_base(np);
403 if (!reg)
404 return;
405
406 parents = clkgen_mux_get_parents(np, &num_parents);
407 if (IS_ERR(parents))
Stephen Boyd86665d22015-07-07 18:30:05 -0700408 goto err_parents;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100409
410 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
411 if (!clk_data)
Stephen Boyd86665d22015-07-07 18:30:05 -0700412 goto err_alloc;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100413
414 clk_data->clk_num = data->num_outputs;
Stephen Boyd86665d22015-07-07 18:30:05 -0700415 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100416 GFP_KERNEL);
417
418 if (!clk_data->clks)
Stephen Boyd86665d22015-07-07 18:30:05 -0700419 goto err_alloc_clks;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100420
421 for (i = 0; i < clk_data->clk_num; i++) {
422 struct clk *clk;
423 const char *clk_name;
424
425 if (of_property_read_string_index(np, "clock-output-names",
426 i, &clk_name))
427 break;
428
429 /*
430 * If we read an empty clock name then the output is unused
431 */
432 if (*clk_name == '\0')
433 continue;
434
435 clk = clk_register_genamux(clk_name, parents, num_parents,
436 reg, data, i);
437
438 if (IS_ERR(clk))
439 goto err;
440
441 clk_data->clks[i] = clk;
442 }
443
444 kfree(parents);
445
446 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
447 return;
448err:
Stephen Boyd86665d22015-07-07 18:30:05 -0700449 kfree(clk_data->clks);
450err_alloc_clks:
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100451 kfree(clk_data);
Stephen Boyd86665d22015-07-07 18:30:05 -0700452err_alloc:
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100453 kfree(parents);
Stephen Boyd86665d22015-07-07 18:30:05 -0700454err_parents:
455 iounmap(reg);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100456}
457CLK_OF_DECLARE(clkgenadivmux, "st,clkgena-divmux", st_of_clkgena_divmux_setup);
458
459struct clkgena_prediv_data {
460 u32 offset;
461 u8 shift;
462 struct clk_div_table *table;
463};
464
465static struct clk_div_table prediv_table16[] = {
466 { .val = 0, .div = 1 },
467 { .val = 1, .div = 16 },
468 { .div = 0 },
469};
470
471static struct clkgena_prediv_data prediv_c65_data = {
472 .offset = 0x4c,
473 .shift = 31,
474 .table = prediv_table16,
475};
476
477static struct clkgena_prediv_data prediv_c32_data = {
478 .offset = 0x50,
479 .shift = 1,
480 .table = prediv_table16,
481};
482
Fabian Frederickf3755732015-03-31 20:50:42 +0200483static const struct of_device_id clkgena_prediv_of_match[] = {
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100484 { .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
485 { .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
486 {}
487};
488
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700489static void __init st_of_clkgena_prediv_setup(struct device_node *np)
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100490{
491 const struct of_device_id *match;
492 void __iomem *reg;
493 const char *parent_name, *clk_name;
494 struct clk *clk;
Stephen Boyd86665d22015-07-07 18:30:05 -0700495 const struct clkgena_prediv_data *data;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100496
497 match = of_match_node(clkgena_prediv_of_match, np);
498 if (!match) {
499 pr_err("%s: No matching data\n", __func__);
500 return;
501 }
502
Stephen Boyd86665d22015-07-07 18:30:05 -0700503 data = match->data;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100504
505 reg = clkgen_get_register_base(np);
506 if (!reg)
507 return;
508
509 parent_name = of_clk_get_parent_name(np, 0);
510 if (!parent_name)
Stephen Boyd86665d22015-07-07 18:30:05 -0700511 goto err;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100512
513 if (of_property_read_string_index(np, "clock-output-names",
514 0, &clk_name))
Stephen Boyd86665d22015-07-07 18:30:05 -0700515 goto err;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100516
Pankaj Dev18fee452015-06-23 16:09:24 +0200517 clk = clk_register_divider_table(NULL, clk_name, parent_name,
518 CLK_GET_RATE_NOCACHE,
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100519 reg + data->offset, data->shift, 1,
520 0, data->table, NULL);
521 if (IS_ERR(clk))
Stephen Boyd86665d22015-07-07 18:30:05 -0700522 goto err;
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100523
524 of_clk_add_provider(np, of_clk_src_simple_get, clk);
525 pr_debug("%s: parent %s rate %u\n",
526 __clk_get_name(clk),
527 __clk_get_name(clk_get_parent(clk)),
528 (unsigned int)clk_get_rate(clk));
529
530 return;
Stephen Boyd86665d22015-07-07 18:30:05 -0700531err:
532 iounmap(reg);
Gabriel FERNANDEZ94885fa2014-02-27 16:24:14 +0100533}
534CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100535
536struct clkgen_mux_data {
537 u32 offset;
538 u8 shift;
539 u8 width;
540 spinlock_t *lock;
541 unsigned long clk_flags;
542 u8 mux_flags;
543};
544
545static struct clkgen_mux_data clkgen_mux_c_vcc_hd_416 = {
546 .offset = 0,
547 .shift = 0,
548 .width = 1,
549};
550
551static struct clkgen_mux_data clkgen_mux_f_vcc_fvdp_416 = {
552 .offset = 0,
553 .shift = 0,
554 .width = 1,
555};
556
557static struct clkgen_mux_data clkgen_mux_f_vcc_hva_416 = {
558 .offset = 0,
559 .shift = 0,
560 .width = 1,
561};
562
563static struct clkgen_mux_data clkgen_mux_f_vcc_hd_416 = {
564 .offset = 0,
565 .shift = 16,
566 .width = 1,
567 .lock = &clkgenf_lock,
568};
569
570static struct clkgen_mux_data clkgen_mux_c_vcc_sd_416 = {
571 .offset = 0,
572 .shift = 17,
573 .width = 1,
574 .lock = &clkgenf_lock,
575};
576
Gabriel FERNANDEZab35dc12014-02-27 16:24:19 +0100577static struct clkgen_mux_data stih415_a9_mux_data = {
578 .offset = 0,
579 .shift = 1,
580 .width = 2,
581};
582static struct clkgen_mux_data stih416_a9_mux_data = {
583 .offset = 0,
584 .shift = 0,
585 .width = 2,
586};
Gabriel FERNANDEZ13e6f2d2014-07-15 17:20:23 +0200587static struct clkgen_mux_data stih407_a9_mux_data = {
588 .offset = 0x1a4,
Gabriel Fernandez3be6d8c2015-06-23 16:09:25 +0200589 .shift = 0,
Gabriel FERNANDEZ13e6f2d2014-07-15 17:20:23 +0200590 .width = 2,
591};
Gabriel FERNANDEZab35dc12014-02-27 16:24:19 +0100592
Fabian Frederickf3755732015-03-31 20:50:42 +0200593static const struct of_device_id mux_of_match[] = {
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100594 {
595 .compatible = "st,stih416-clkgenc-vcc-hd",
596 .data = &clkgen_mux_c_vcc_hd_416,
597 },
598 {
599 .compatible = "st,stih416-clkgenf-vcc-fvdp",
600 .data = &clkgen_mux_f_vcc_fvdp_416,
601 },
602 {
603 .compatible = "st,stih416-clkgenf-vcc-hva",
604 .data = &clkgen_mux_f_vcc_hva_416,
605 },
606 {
607 .compatible = "st,stih416-clkgenf-vcc-hd",
608 .data = &clkgen_mux_f_vcc_hd_416,
609 },
610 {
611 .compatible = "st,stih416-clkgenf-vcc-sd",
612 .data = &clkgen_mux_c_vcc_sd_416,
613 },
Gabriel FERNANDEZab35dc12014-02-27 16:24:19 +0100614 {
615 .compatible = "st,stih415-clkgen-a9-mux",
616 .data = &stih415_a9_mux_data,
617 },
618 {
619 .compatible = "st,stih416-clkgen-a9-mux",
620 .data = &stih416_a9_mux_data,
621 },
Gabriel FERNANDEZ13e6f2d2014-07-15 17:20:23 +0200622 {
623 .compatible = "st,stih407-clkgen-a9-mux",
624 .data = &stih407_a9_mux_data,
625 },
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100626 {}
627};
628
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700629static void __init st_of_clkgen_mux_setup(struct device_node *np)
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100630{
631 const struct of_device_id *match;
632 struct clk *clk;
633 void __iomem *reg;
634 const char **parents;
635 int num_parents;
Stephen Boyd86665d22015-07-07 18:30:05 -0700636 const struct clkgen_mux_data *data;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100637
638 match = of_match_node(mux_of_match, np);
639 if (!match) {
640 pr_err("%s: No matching data\n", __func__);
641 return;
642 }
643
Stephen Boyd86665d22015-07-07 18:30:05 -0700644 data = match->data;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100645
646 reg = of_iomap(np, 0);
647 if (!reg) {
648 pr_err("%s: Failed to get base address\n", __func__);
649 return;
650 }
651
652 parents = clkgen_mux_get_parents(np, &num_parents);
653 if (IS_ERR(parents)) {
654 pr_err("%s: Failed to get parents (%ld)\n",
655 __func__, PTR_ERR(parents));
Stephen Boyd86665d22015-07-07 18:30:05 -0700656 goto err_parents;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100657 }
658
659 clk = clk_register_mux(NULL, np->name, parents, num_parents,
660 data->clk_flags | CLK_SET_RATE_PARENT,
661 reg + data->offset,
662 data->shift, data->width, data->mux_flags,
663 data->lock);
664 if (IS_ERR(clk))
665 goto err;
666
667 pr_debug("%s: parent %s rate %u\n",
668 __clk_get_name(clk),
669 __clk_get_name(clk_get_parent(clk)),
670 (unsigned int)clk_get_rate(clk));
671
Stephen Boyd86665d22015-07-07 18:30:05 -0700672 kfree(parents);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100673 of_clk_add_provider(np, of_clk_src_simple_get, clk);
Stephen Boyd86665d22015-07-07 18:30:05 -0700674 return;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100675
676err:
677 kfree(parents);
Stephen Boyd86665d22015-07-07 18:30:05 -0700678err_parents:
679 iounmap(reg);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100680}
681CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
682
683#define VCC_MAX_CHANNELS 16
684
685#define VCC_GATE_OFFSET 0x0
686#define VCC_MUX_OFFSET 0x4
687#define VCC_DIV_OFFSET 0x8
688
689struct clkgen_vcc_data {
690 spinlock_t *lock;
691 unsigned long clk_flags;
692};
693
694static struct clkgen_vcc_data st_clkgenc_vcc_416 = {
695 .clk_flags = CLK_SET_RATE_PARENT,
696};
697
698static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
699 .lock = &clkgenf_lock,
700};
701
Fabian Frederickf3755732015-03-31 20:50:42 +0200702static const struct of_device_id vcc_of_match[] = {
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100703 { .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
704 { .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
705 {}
706};
707
Stephen Boyd8e6dd772015-05-01 12:45:53 -0700708static void __init st_of_clkgen_vcc_setup(struct device_node *np)
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100709{
710 const struct of_device_id *match;
711 void __iomem *reg;
712 const char **parents;
713 int num_parents, i;
714 struct clk_onecell_data *clk_data;
Stephen Boyd86665d22015-07-07 18:30:05 -0700715 const struct clkgen_vcc_data *data;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100716
717 match = of_match_node(vcc_of_match, np);
718 if (WARN_ON(!match))
719 return;
Stephen Boyd86665d22015-07-07 18:30:05 -0700720 data = match->data;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100721
722 reg = of_iomap(np, 0);
723 if (!reg)
724 return;
725
726 parents = clkgen_mux_get_parents(np, &num_parents);
727 if (IS_ERR(parents))
Stephen Boyd86665d22015-07-07 18:30:05 -0700728 goto err_parents;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100729
730 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
731 if (!clk_data)
Stephen Boyd86665d22015-07-07 18:30:05 -0700732 goto err_alloc;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100733
734 clk_data->clk_num = VCC_MAX_CHANNELS;
Stephen Boyd86665d22015-07-07 18:30:05 -0700735 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100736 GFP_KERNEL);
737
738 if (!clk_data->clks)
Stephen Boyd86665d22015-07-07 18:30:05 -0700739 goto err_alloc_clks;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100740
741 for (i = 0; i < clk_data->clk_num; i++) {
742 struct clk *clk;
743 const char *clk_name;
744 struct clk_gate *gate;
745 struct clk_divider *div;
746 struct clk_mux *mux;
747
748 if (of_property_read_string_index(np, "clock-output-names",
749 i, &clk_name))
750 break;
751
752 /*
753 * If we read an empty clock name then the output is unused
754 */
755 if (*clk_name == '\0')
756 continue;
757
Stephen Boyd86665d22015-07-07 18:30:05 -0700758 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100759 if (!gate)
Stephen Boyd86665d22015-07-07 18:30:05 -0700760 goto err;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100761
Stephen Boyd86665d22015-07-07 18:30:05 -0700762 div = kzalloc(sizeof(*div), GFP_KERNEL);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100763 if (!div) {
764 kfree(gate);
Stephen Boyd86665d22015-07-07 18:30:05 -0700765 goto err;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100766 }
767
Stephen Boyd86665d22015-07-07 18:30:05 -0700768 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100769 if (!mux) {
770 kfree(gate);
771 kfree(div);
Stephen Boyd86665d22015-07-07 18:30:05 -0700772 goto err;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100773 }
774
775 gate->reg = reg + VCC_GATE_OFFSET;
776 gate->bit_idx = i;
777 gate->flags = CLK_GATE_SET_TO_DISABLE;
778 gate->lock = data->lock;
779
780 div->reg = reg + VCC_DIV_OFFSET;
781 div->shift = 2 * i;
782 div->width = 2;
Gabriel FERNANDEZeee40bb2014-07-15 17:20:31 +0200783 div->flags = CLK_DIVIDER_POWER_OF_TWO |
784 CLK_DIVIDER_ROUND_CLOSEST;
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100785
786 mux->reg = reg + VCC_MUX_OFFSET;
787 mux->shift = 2 * i;
788 mux->mask = 0x3;
789
790 clk = clk_register_composite(NULL, clk_name, parents,
791 num_parents,
792 &mux->hw, &clk_mux_ops,
793 &div->hw, &clk_divider_ops,
794 &gate->hw, &clk_gate_ops,
Pankaj Dev18fee452015-06-23 16:09:24 +0200795 data->clk_flags |
796 CLK_GET_RATE_NOCACHE);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100797 if (IS_ERR(clk)) {
798 kfree(gate);
799 kfree(div);
800 kfree(mux);
801 goto err;
802 }
803
804 pr_debug("%s: parent %s rate %u\n",
805 __clk_get_name(clk),
806 __clk_get_name(clk_get_parent(clk)),
807 (unsigned int)clk_get_rate(clk));
808
809 clk_data->clks[i] = clk;
810 }
811
812 kfree(parents);
813
814 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
815 return;
816
817err:
818 for (i = 0; i < clk_data->clk_num; i++) {
819 struct clk_composite *composite;
820
821 if (!clk_data->clks[i])
822 continue;
823
824 composite = container_of(__clk_get_hw(clk_data->clks[i]),
825 struct clk_composite, hw);
826 kfree(container_of(composite->gate_hw, struct clk_gate, hw));
827 kfree(container_of(composite->rate_hw, struct clk_divider, hw));
828 kfree(container_of(composite->mux_hw, struct clk_mux, hw));
829 }
830
Stephen Boyd86665d22015-07-07 18:30:05 -0700831 kfree(clk_data->clks);
832err_alloc_clks:
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100833 kfree(clk_data);
Stephen Boyd86665d22015-07-07 18:30:05 -0700834err_alloc:
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100835 kfree(parents);
Stephen Boyd86665d22015-07-07 18:30:05 -0700836err_parents:
837 iounmap(reg);
Gabriel FERNANDEZ44993d32014-02-27 16:24:16 +0100838}
839CLK_OF_DECLARE(clkgen_vcc, "st,clkgen-vcc", st_of_clkgen_vcc_setup);