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gerrit-public.fairphone.software / kernel / msm-4.19 / 882a0644fd3427a17d80ad14d1ca3a6228a3860f / . / drivers / gpu / drm / exynos / exynos_hdmi.c
blob: f2e909de68feca844530db7e8490b692a5ef795f [file] [log] [blame]
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
David Howells760285e2012-10-02 18:01:07 +0100[diff] [blame]17#include <drm/drmP.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_crtc_helper.h>
Gustavo Padovan4ea95262015-06-01 12:04:44 -0300[diff] [blame]20#include <drm/drm_atomic_helper.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]21
22#include "regs-hdmi.h"
23
24#include <linux/kernel.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]25#include <linux/wait.h>
26#include <linux/i2c.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
33#include <linux/regulator/consumer.h>
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]34#include <linux/io.h>
Sachin Kamat3f1c7812013-08-14 16:38:01 +0530[diff] [blame]35#include <linux/of.h>
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]36#include <linux/of_address.h>
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]37#include <linux/of_gpio.h>
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]38#include <linux/hdmi.h>
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]39#include <linux/component.h>
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]40#include <linux/mfd/syscon.h>
41#include <linux/regmap.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]42
43#include <drm/exynos_drm.h>
44
45#include "exynos_drm_drv.h"
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]46#include "exynos_drm_crtc.h"
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]47#include "exynos_mixer.h"
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]48
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]49#include <linux/gpio.h>
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]50
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]51#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]52
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]53#define HOTPLUG_DEBOUNCE_MS 1100
54
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]55/* AVI header and aspect ratio */
56#define HDMI_AVI_VERSION 0x02
57#define HDMI_AVI_LENGTH 0x0D
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]58
59/* AUI header info */
60#define HDMI_AUI_VERSION 0x01
61#define HDMI_AUI_LENGTH 0x0A
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]62#define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
63#define AVI_4_3_CENTER_RATIO 0x9
64#define AVI_16_9_CENTER_RATIO 0xa
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]65
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]66enum hdmi_type {
67 HDMI_TYPE13,
68 HDMI_TYPE14,
69};
70
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]71struct hdmi_driver_data {
72 unsigned int type;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]73 const struct hdmiphy_config *phy_confs;
74 unsigned int phy_conf_count;
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]75 unsigned int is_apb_phy:1;
76};
77
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]78struct hdmi_resources {
79 struct clk *hdmi;
80 struct clk *sclk_hdmi;
81 struct clk *sclk_pixel;
82 struct clk *sclk_hdmiphy;
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]83 struct clk *mout_hdmi;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]84 struct regulator_bulk_data *regul_bulk;
Marek Szyprowski05fdf982014-07-01 10:10:06 +0200[diff] [blame]85 struct regulator *reg_hdmi_en;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]86 int regul_count;
87};
88
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]89struct hdmi_tg_regs {
90 u8 cmd[1];
91 u8 h_fsz[2];
92 u8 hact_st[2];
93 u8 hact_sz[2];
94 u8 v_fsz[2];
95 u8 vsync[2];
96 u8 vsync2[2];
97 u8 vact_st[2];
98 u8 vact_sz[2];
99 u8 field_chg[2];
100 u8 vact_st2[2];
101 u8 vact_st3[2];
102 u8 vact_st4[2];
103 u8 vsync_top_hdmi[2];
104 u8 vsync_bot_hdmi[2];
105 u8 field_top_hdmi[2];
106 u8 field_bot_hdmi[2];
107 u8 tg_3d[1];
108};
109
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]110struct hdmi_v13_core_regs {
111 u8 h_blank[2];
112 u8 v_blank[3];
113 u8 h_v_line[3];
114 u8 vsync_pol[1];
115 u8 int_pro_mode[1];
116 u8 v_blank_f[3];
117 u8 h_sync_gen[3];
118 u8 v_sync_gen1[3];
119 u8 v_sync_gen2[3];
120 u8 v_sync_gen3[3];
121};
122
123struct hdmi_v14_core_regs {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]124 u8 h_blank[2];
125 u8 v2_blank[2];
126 u8 v1_blank[2];
127 u8 v_line[2];
128 u8 h_line[2];
129 u8 hsync_pol[1];
130 u8 vsync_pol[1];
131 u8 int_pro_mode[1];
132 u8 v_blank_f0[2];
133 u8 v_blank_f1[2];
134 u8 h_sync_start[2];
135 u8 h_sync_end[2];
136 u8 v_sync_line_bef_2[2];
137 u8 v_sync_line_bef_1[2];
138 u8 v_sync_line_aft_2[2];
139 u8 v_sync_line_aft_1[2];
140 u8 v_sync_line_aft_pxl_2[2];
141 u8 v_sync_line_aft_pxl_1[2];
142 u8 v_blank_f2[2]; /* for 3D mode */
143 u8 v_blank_f3[2]; /* for 3D mode */
144 u8 v_blank_f4[2]; /* for 3D mode */
145 u8 v_blank_f5[2]; /* for 3D mode */
146 u8 v_sync_line_aft_3[2];
147 u8 v_sync_line_aft_4[2];
148 u8 v_sync_line_aft_5[2];
149 u8 v_sync_line_aft_6[2];
150 u8 v_sync_line_aft_pxl_3[2];
151 u8 v_sync_line_aft_pxl_4[2];
152 u8 v_sync_line_aft_pxl_5[2];
153 u8 v_sync_line_aft_pxl_6[2];
154 u8 vact_space_1[2];
155 u8 vact_space_2[2];
156 u8 vact_space_3[2];
157 u8 vact_space_4[2];
158 u8 vact_space_5[2];
159 u8 vact_space_6[2];
160};
161
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]162struct hdmi_v13_conf {
163 struct hdmi_v13_core_regs core;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]164 struct hdmi_tg_regs tg;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]165};
166
167struct hdmi_v14_conf {
168 struct hdmi_v14_core_regs core;
169 struct hdmi_tg_regs tg;
170};
171
172struct hdmi_conf_regs {
173 int pixel_clock;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]174 int cea_video_id;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]175 enum hdmi_picture_aspect aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]176 union {
177 struct hdmi_v13_conf v13_conf;
178 struct hdmi_v14_conf v14_conf;
179 } conf;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]180};
181
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]182struct hdmi_context {
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]183 struct exynos_drm_display display;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]184 struct device *dev;
185 struct drm_device *drm_dev;
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]186 struct drm_connector connector;
187 struct drm_encoder *encoder;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]188 bool powered;
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]189 bool dvi_mode;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]190
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]191 void __iomem *regs;
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]192 int irq;
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]193 struct delayed_work hotplug_work;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]194
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]195 struct i2c_adapter *ddc_adpt;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]196 struct i2c_client *hdmiphy_port;
197
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]198 /* current hdmiphy conf regs */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]199 struct drm_display_mode current_mode;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]200 struct hdmi_conf_regs mode_conf;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]201
202 struct hdmi_resources res;
Joonyoung Shim7ecd34e2012-04-23 19:35:47 +0900[diff] [blame]203
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]204 int hpd_gpio;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]205 void __iomem *regs_hdmiphy;
206 const struct hdmiphy_config *phy_confs;
207 unsigned int phy_conf_count;
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]208
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]209 struct regmap *pmureg;
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]210 enum hdmi_type type;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]211};
212
Andrzej Hajda0d8424f82014-11-17 09:54:21 +0100[diff] [blame]213static inline struct hdmi_context *display_to_hdmi(struct exynos_drm_display *d)
214{
215 return container_of(d, struct hdmi_context, display);
216}
217
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]218struct hdmiphy_config {
219 int pixel_clock;
220 u8 conf[32];
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]221};
222
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]223/* list of phy config settings */
224static const struct hdmiphy_config hdmiphy_v13_configs[] = {
225 {
226 .pixel_clock = 27000000,
227 .conf = {
228 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
229 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
230 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
231 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
232 },
233 },
234 {
235 .pixel_clock = 27027000,
236 .conf = {
237 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
238 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
239 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
240 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
241 },
242 },
243 {
244 .pixel_clock = 74176000,
245 .conf = {
246 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
247 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
248 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
249 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
250 },
251 },
252 {
253 .pixel_clock = 74250000,
254 .conf = {
255 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
256 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
257 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
258 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
259 },
260 },
261 {
262 .pixel_clock = 148500000,
263 .conf = {
264 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
265 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
266 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
267 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
268 },
269 },
270};
271
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]272static const struct hdmiphy_config hdmiphy_v14_configs[] = {
273 {
274 .pixel_clock = 25200000,
275 .conf = {
276 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
277 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
278 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
279 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
280 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]281 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]282 {
283 .pixel_clock = 27000000,
284 .conf = {
285 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
286 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
287 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
288 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
289 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]290 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]291 {
292 .pixel_clock = 27027000,
293 .conf = {
294 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
295 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
296 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
297 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
298 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]299 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]300 {
301 .pixel_clock = 36000000,
302 .conf = {
303 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
304 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
305 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
306 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
307 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]308 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]309 {
310 .pixel_clock = 40000000,
311 .conf = {
312 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
313 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
314 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
315 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
316 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]317 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]318 {
319 .pixel_clock = 65000000,
320 .conf = {
321 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
322 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
323 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
324 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
325 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]326 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]327 {
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]328 .pixel_clock = 71000000,
329 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]330 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
331 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
332 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]333 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
334 },
335 },
336 {
337 .pixel_clock = 73250000,
338 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]339 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
340 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
341 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]342 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
343 },
344 },
345 {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]346 .pixel_clock = 74176000,
347 .conf = {
348 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
349 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
350 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
351 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
352 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]353 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]354 {
355 .pixel_clock = 74250000,
356 .conf = {
357 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
358 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
359 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
360 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
361 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]362 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]363 {
364 .pixel_clock = 83500000,
365 .conf = {
366 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
367 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
368 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
369 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
370 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]371 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]372 {
373 .pixel_clock = 106500000,
374 .conf = {
375 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
376 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
377 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
378 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
379 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]380 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]381 {
382 .pixel_clock = 108000000,
383 .conf = {
384 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
385 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
386 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
387 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
388 },
Seung-Woo Kime540adf2012-04-24 17:55:06 +0900[diff] [blame]389 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]390 {
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]391 .pixel_clock = 115500000,
392 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]393 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
394 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
395 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]396 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
397 },
398 },
399 {
400 .pixel_clock = 119000000,
401 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]402 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
403 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
404 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]405 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
406 },
407 },
408 {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]409 .pixel_clock = 146250000,
410 .conf = {
411 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
412 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
413 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
414 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
415 },
Seung-Woo Kime540adf2012-04-24 17:55:06 +0900[diff] [blame]416 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]417 {
418 .pixel_clock = 148500000,
419 .conf = {
420 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
421 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
422 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
423 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
424 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]425 },
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]426};
427
Rahul Sharmaa18a2dd2014-04-20 15:51:17 +0530[diff] [blame]428static const struct hdmiphy_config hdmiphy_5420_configs[] = {
429 {
430 .pixel_clock = 25200000,
431 .conf = {
432 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
433 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
434 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
435 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
436 },
437 },
438 {
439 .pixel_clock = 27000000,
440 .conf = {
441 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
442 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
443 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
444 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
445 },
446 },
447 {
448 .pixel_clock = 27027000,
449 .conf = {
450 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
451 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
452 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
453 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
454 },
455 },
456 {
457 .pixel_clock = 36000000,
458 .conf = {
459 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
460 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
461 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
462 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
463 },
464 },
465 {
466 .pixel_clock = 40000000,
467 .conf = {
468 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
469 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
470 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
471 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
472 },
473 },
474 {
475 .pixel_clock = 65000000,
476 .conf = {
477 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
478 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
479 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
480 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
481 },
482 },
483 {
484 .pixel_clock = 71000000,
485 .conf = {
486 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
487 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
488 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
489 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
490 },
491 },
492 {
493 .pixel_clock = 73250000,
494 .conf = {
495 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
496 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
497 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
498 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
499 },
500 },
501 {
502 .pixel_clock = 74176000,
503 .conf = {
504 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
505 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
506 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
507 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
508 },
509 },
510 {
511 .pixel_clock = 74250000,
512 .conf = {
513 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
514 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
515 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
516 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
517 },
518 },
519 {
520 .pixel_clock = 83500000,
521 .conf = {
522 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
523 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
524 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
525 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
526 },
527 },
528 {
529 .pixel_clock = 88750000,
530 .conf = {
531 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
532 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
533 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
534 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
535 },
536 },
537 {
538 .pixel_clock = 106500000,
539 .conf = {
540 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
541 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
542 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
543 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
544 },
545 },
546 {
547 .pixel_clock = 108000000,
548 .conf = {
549 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
550 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
551 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
552 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
553 },
554 },
555 {
556 .pixel_clock = 115500000,
557 .conf = {
558 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
559 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
560 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
561 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
562 },
563 },
564 {
565 .pixel_clock = 146250000,
566 .conf = {
567 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
568 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
569 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
570 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
571 },
572 },
573 {
574 .pixel_clock = 148500000,
575 .conf = {
576 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
577 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
578 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
579 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
580 },
581 },
582};
583
Sachin Kamat16337072014-05-22 10:32:56 +0530[diff] [blame]584static struct hdmi_driver_data exynos5420_hdmi_driver_data = {
Rahul Sharmaa18a2dd2014-04-20 15:51:17 +0530[diff] [blame]585 .type = HDMI_TYPE14,
586 .phy_confs = hdmiphy_5420_configs,
587 .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs),
588 .is_apb_phy = 1,
589};
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]590
Sachin Kamat16337072014-05-22 10:32:56 +0530[diff] [blame]591static struct hdmi_driver_data exynos4212_hdmi_driver_data = {
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]592 .type = HDMI_TYPE14,
593 .phy_confs = hdmiphy_v14_configs,
594 .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
595 .is_apb_phy = 0,
596};
597
Marek Szyprowskiff830c92014-07-01 10:10:07 +0200[diff] [blame]598static struct hdmi_driver_data exynos4210_hdmi_driver_data = {
599 .type = HDMI_TYPE13,
600 .phy_confs = hdmiphy_v13_configs,
601 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
602 .is_apb_phy = 0,
603};
604
Sachin Kamat16337072014-05-22 10:32:56 +0530[diff] [blame]605static struct hdmi_driver_data exynos5_hdmi_driver_data = {
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]606 .type = HDMI_TYPE14,
607 .phy_confs = hdmiphy_v13_configs,
608 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
609 .is_apb_phy = 0,
610};
611
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]612static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
613{
614 return readl(hdata->regs + reg_id);
615}
616
617static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
618 u32 reg_id, u8 value)
619{
620 writeb(value, hdata->regs + reg_id);
621}
622
623static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
624 u32 reg_id, u32 value, u32 mask)
625{
626 u32 old = readl(hdata->regs + reg_id);
627 value = (value & mask) | (old & ~mask);
628 writel(value, hdata->regs + reg_id);
629}
630
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]631static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
632 u32 reg_offset, u8 value)
633{
634 if (hdata->hdmiphy_port) {
635 u8 buffer[2];
636 int ret;
637
638 buffer[0] = reg_offset;
639 buffer[1] = value;
640
641 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
642 if (ret == 2)
643 return 0;
644 return ret;
645 } else {
646 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
647 return 0;
648 }
649}
650
651static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
652 u32 reg_offset, const u8 *buf, u32 len)
653{
654 if ((reg_offset + len) > 32)
655 return -EINVAL;
656
657 if (hdata->hdmiphy_port) {
658 int ret;
659
660 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
661 if (ret == len)
662 return 0;
663 return ret;
664 } else {
665 int i;
666 for (i = 0; i < len; i++)
667 writeb(buf[i], hdata->regs_hdmiphy +
668 ((reg_offset + i)<<2));
669 return 0;
670 }
671}
672
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]673static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]674{
675#define DUMPREG(reg_id) \
676 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
677 readl(hdata->regs + reg_id))
678 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
679 DUMPREG(HDMI_INTC_FLAG);
680 DUMPREG(HDMI_INTC_CON);
681 DUMPREG(HDMI_HPD_STATUS);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]682 DUMPREG(HDMI_V13_PHY_RSTOUT);
683 DUMPREG(HDMI_V13_PHY_VPLL);
684 DUMPREG(HDMI_V13_PHY_CMU);
685 DUMPREG(HDMI_V13_CORE_RSTOUT);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]686
687 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
688 DUMPREG(HDMI_CON_0);
689 DUMPREG(HDMI_CON_1);
690 DUMPREG(HDMI_CON_2);
691 DUMPREG(HDMI_SYS_STATUS);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]692 DUMPREG(HDMI_V13_PHY_STATUS);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]693 DUMPREG(HDMI_STATUS_EN);
694 DUMPREG(HDMI_HPD);
695 DUMPREG(HDMI_MODE_SEL);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]696 DUMPREG(HDMI_V13_HPD_GEN);
697 DUMPREG(HDMI_V13_DC_CONTROL);
698 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]699
700 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
701 DUMPREG(HDMI_H_BLANK_0);
702 DUMPREG(HDMI_H_BLANK_1);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]703 DUMPREG(HDMI_V13_V_BLANK_0);
704 DUMPREG(HDMI_V13_V_BLANK_1);
705 DUMPREG(HDMI_V13_V_BLANK_2);
706 DUMPREG(HDMI_V13_H_V_LINE_0);
707 DUMPREG(HDMI_V13_H_V_LINE_1);
708 DUMPREG(HDMI_V13_H_V_LINE_2);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]709 DUMPREG(HDMI_VSYNC_POL);
710 DUMPREG(HDMI_INT_PRO_MODE);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]711 DUMPREG(HDMI_V13_V_BLANK_F_0);
712 DUMPREG(HDMI_V13_V_BLANK_F_1);
713 DUMPREG(HDMI_V13_V_BLANK_F_2);
714 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
715 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
716 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
717 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
718 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
719 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
720 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
721 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
722 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
723 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
724 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
725 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]726
727 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
728 DUMPREG(HDMI_TG_CMD);
729 DUMPREG(HDMI_TG_H_FSZ_L);
730 DUMPREG(HDMI_TG_H_FSZ_H);
731 DUMPREG(HDMI_TG_HACT_ST_L);
732 DUMPREG(HDMI_TG_HACT_ST_H);
733 DUMPREG(HDMI_TG_HACT_SZ_L);
734 DUMPREG(HDMI_TG_HACT_SZ_H);
735 DUMPREG(HDMI_TG_V_FSZ_L);
736 DUMPREG(HDMI_TG_V_FSZ_H);
737 DUMPREG(HDMI_TG_VSYNC_L);
738 DUMPREG(HDMI_TG_VSYNC_H);
739 DUMPREG(HDMI_TG_VSYNC2_L);
740 DUMPREG(HDMI_TG_VSYNC2_H);
741 DUMPREG(HDMI_TG_VACT_ST_L);
742 DUMPREG(HDMI_TG_VACT_ST_H);
743 DUMPREG(HDMI_TG_VACT_SZ_L);
744 DUMPREG(HDMI_TG_VACT_SZ_H);
745 DUMPREG(HDMI_TG_FIELD_CHG_L);
746 DUMPREG(HDMI_TG_FIELD_CHG_H);
747 DUMPREG(HDMI_TG_VACT_ST2_L);
748 DUMPREG(HDMI_TG_VACT_ST2_H);
749 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
750 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
751 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
752 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
753 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
754 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
755 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
756 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
757#undef DUMPREG
758}
759
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]760static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
761{
762 int i;
763
764#define DUMPREG(reg_id) \
765 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
766 readl(hdata->regs + reg_id))
767
768 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
769 DUMPREG(HDMI_INTC_CON);
770 DUMPREG(HDMI_INTC_FLAG);
771 DUMPREG(HDMI_HPD_STATUS);
772 DUMPREG(HDMI_INTC_CON_1);
773 DUMPREG(HDMI_INTC_FLAG_1);
774 DUMPREG(HDMI_PHY_STATUS_0);
775 DUMPREG(HDMI_PHY_STATUS_PLL);
776 DUMPREG(HDMI_PHY_CON_0);
777 DUMPREG(HDMI_PHY_RSTOUT);
778 DUMPREG(HDMI_PHY_VPLL);
779 DUMPREG(HDMI_PHY_CMU);
780 DUMPREG(HDMI_CORE_RSTOUT);
781
782 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
783 DUMPREG(HDMI_CON_0);
784 DUMPREG(HDMI_CON_1);
785 DUMPREG(HDMI_CON_2);
786 DUMPREG(HDMI_SYS_STATUS);
787 DUMPREG(HDMI_PHY_STATUS_0);
788 DUMPREG(HDMI_STATUS_EN);
789 DUMPREG(HDMI_HPD);
790 DUMPREG(HDMI_MODE_SEL);
791 DUMPREG(HDMI_ENC_EN);
792 DUMPREG(HDMI_DC_CONTROL);
793 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
794
795 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
796 DUMPREG(HDMI_H_BLANK_0);
797 DUMPREG(HDMI_H_BLANK_1);
798 DUMPREG(HDMI_V2_BLANK_0);
799 DUMPREG(HDMI_V2_BLANK_1);
800 DUMPREG(HDMI_V1_BLANK_0);
801 DUMPREG(HDMI_V1_BLANK_1);
802 DUMPREG(HDMI_V_LINE_0);
803 DUMPREG(HDMI_V_LINE_1);
804 DUMPREG(HDMI_H_LINE_0);
805 DUMPREG(HDMI_H_LINE_1);
806 DUMPREG(HDMI_HSYNC_POL);
807
808 DUMPREG(HDMI_VSYNC_POL);
809 DUMPREG(HDMI_INT_PRO_MODE);
810 DUMPREG(HDMI_V_BLANK_F0_0);
811 DUMPREG(HDMI_V_BLANK_F0_1);
812 DUMPREG(HDMI_V_BLANK_F1_0);
813 DUMPREG(HDMI_V_BLANK_F1_1);
814
815 DUMPREG(HDMI_H_SYNC_START_0);
816 DUMPREG(HDMI_H_SYNC_START_1);
817 DUMPREG(HDMI_H_SYNC_END_0);
818 DUMPREG(HDMI_H_SYNC_END_1);
819
820 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
821 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
822 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
823 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
824
825 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
826 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
827 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
828 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
829
830 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
831 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
832 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
833 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
834
835 DUMPREG(HDMI_V_BLANK_F2_0);
836 DUMPREG(HDMI_V_BLANK_F2_1);
837 DUMPREG(HDMI_V_BLANK_F3_0);
838 DUMPREG(HDMI_V_BLANK_F3_1);
839 DUMPREG(HDMI_V_BLANK_F4_0);
840 DUMPREG(HDMI_V_BLANK_F4_1);
841 DUMPREG(HDMI_V_BLANK_F5_0);
842 DUMPREG(HDMI_V_BLANK_F5_1);
843
844 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
845 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
846 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
847 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
848 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
849 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
850 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
851 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
852
853 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
854 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
855 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
856 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
857 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
858 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
859 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
860 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
861
862 DUMPREG(HDMI_VACT_SPACE_1_0);
863 DUMPREG(HDMI_VACT_SPACE_1_1);
864 DUMPREG(HDMI_VACT_SPACE_2_0);
865 DUMPREG(HDMI_VACT_SPACE_2_1);
866 DUMPREG(HDMI_VACT_SPACE_3_0);
867 DUMPREG(HDMI_VACT_SPACE_3_1);
868 DUMPREG(HDMI_VACT_SPACE_4_0);
869 DUMPREG(HDMI_VACT_SPACE_4_1);
870 DUMPREG(HDMI_VACT_SPACE_5_0);
871 DUMPREG(HDMI_VACT_SPACE_5_1);
872 DUMPREG(HDMI_VACT_SPACE_6_0);
873 DUMPREG(HDMI_VACT_SPACE_6_1);
874
875 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
876 DUMPREG(HDMI_TG_CMD);
877 DUMPREG(HDMI_TG_H_FSZ_L);
878 DUMPREG(HDMI_TG_H_FSZ_H);
879 DUMPREG(HDMI_TG_HACT_ST_L);
880 DUMPREG(HDMI_TG_HACT_ST_H);
881 DUMPREG(HDMI_TG_HACT_SZ_L);
882 DUMPREG(HDMI_TG_HACT_SZ_H);
883 DUMPREG(HDMI_TG_V_FSZ_L);
884 DUMPREG(HDMI_TG_V_FSZ_H);
885 DUMPREG(HDMI_TG_VSYNC_L);
886 DUMPREG(HDMI_TG_VSYNC_H);
887 DUMPREG(HDMI_TG_VSYNC2_L);
888 DUMPREG(HDMI_TG_VSYNC2_H);
889 DUMPREG(HDMI_TG_VACT_ST_L);
890 DUMPREG(HDMI_TG_VACT_ST_H);
891 DUMPREG(HDMI_TG_VACT_SZ_L);
892 DUMPREG(HDMI_TG_VACT_SZ_H);
893 DUMPREG(HDMI_TG_FIELD_CHG_L);
894 DUMPREG(HDMI_TG_FIELD_CHG_H);
895 DUMPREG(HDMI_TG_VACT_ST2_L);
896 DUMPREG(HDMI_TG_VACT_ST2_H);
897 DUMPREG(HDMI_TG_VACT_ST3_L);
898 DUMPREG(HDMI_TG_VACT_ST3_H);
899 DUMPREG(HDMI_TG_VACT_ST4_L);
900 DUMPREG(HDMI_TG_VACT_ST4_H);
901 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
902 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
903 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
904 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
905 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
906 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
907 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
908 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
909 DUMPREG(HDMI_TG_3D);
910
911 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
912 DUMPREG(HDMI_AVI_CON);
913 DUMPREG(HDMI_AVI_HEADER0);
914 DUMPREG(HDMI_AVI_HEADER1);
915 DUMPREG(HDMI_AVI_HEADER2);
916 DUMPREG(HDMI_AVI_CHECK_SUM);
917 DUMPREG(HDMI_VSI_CON);
918 DUMPREG(HDMI_VSI_HEADER0);
919 DUMPREG(HDMI_VSI_HEADER1);
920 DUMPREG(HDMI_VSI_HEADER2);
921 for (i = 0; i < 7; ++i)
922 DUMPREG(HDMI_VSI_DATA(i));
923
924#undef DUMPREG
925}
926
927static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
928{
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]929 if (hdata->type == HDMI_TYPE13)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]930 hdmi_v13_regs_dump(hdata, prefix);
931 else
932 hdmi_v14_regs_dump(hdata, prefix);
933}
934
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]935static u8 hdmi_chksum(struct hdmi_context *hdata,
936 u32 start, u8 len, u32 hdr_sum)
937{
938 int i;
939
940 /* hdr_sum : header0 + header1 + header2
941 * start : start address of packet byte1
942 * len : packet bytes - 1 */
943 for (i = 0; i < len; ++i)
944 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
945
946 /* return 2's complement of 8 bit hdr_sum */
947 return (u8)(~(hdr_sum & 0xff) + 1);
948}
949
950static void hdmi_reg_infoframe(struct hdmi_context *hdata,
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]951 union hdmi_infoframe *infoframe)
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]952{
953 u32 hdr_sum;
954 u8 chksum;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]955 u32 mod;
956 u32 vic;
957
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]958 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
959 if (hdata->dvi_mode) {
960 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
961 HDMI_VSI_CON_DO_NOT_TRANSMIT);
962 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
963 HDMI_AVI_CON_DO_NOT_TRANSMIT);
964 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
965 return;
966 }
967
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]968 switch (infoframe->any.type) {
969 case HDMI_INFOFRAME_TYPE_AVI:
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]970 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]971 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
972 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
973 infoframe->any.version);
974 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
975 hdr_sum = infoframe->any.type + infoframe->any.version +
976 infoframe->any.length;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]977
978 /* Output format zero hardcoded ,RGB YBCR selection */
979 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
980 AVI_ACTIVE_FORMAT_VALID |
981 AVI_UNDERSCANNED_DISPLAY_VALID);
982
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]983 /*
984 * Set the aspect ratio as per the mode, mentioned in
985 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
986 */
987 switch (hdata->mode_conf.aspect_ratio) {
988 case HDMI_PICTURE_ASPECT_4_3:
989 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
990 hdata->mode_conf.aspect_ratio |
991 AVI_4_3_CENTER_RATIO);
992 break;
993 case HDMI_PICTURE_ASPECT_16_9:
994 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
995 hdata->mode_conf.aspect_ratio |
996 AVI_16_9_CENTER_RATIO);
997 break;
998 case HDMI_PICTURE_ASPECT_NONE:
999 default:
1000 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
1001 hdata->mode_conf.aspect_ratio |
1002 AVI_SAME_AS_PIC_ASPECT_RATIO);
1003 break;
1004 }
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1005
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1006 vic = hdata->mode_conf.cea_video_id;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1007 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
1008
1009 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1010 infoframe->any.length, hdr_sum);
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1011 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1012 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1013 break;
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1014 case HDMI_INFOFRAME_TYPE_AUDIO:
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1015 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1016 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
1017 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
1018 infoframe->any.version);
1019 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
1020 hdr_sum = infoframe->any.type + infoframe->any.version +
1021 infoframe->any.length;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1022 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1023 infoframe->any.length, hdr_sum);
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1024 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1025 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1026 break;
1027 default:
1028 break;
1029 }
1030}
1031
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1032static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
1033 bool force)
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1034{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1035 struct hdmi_context *hdata = ctx_from_connector(connector);
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1036
Andrzej Hajdaef6ce282015-07-09 16:28:07 +0200[diff] [blame]1037 if (gpio_get_value(hdata->hpd_gpio))
1038 return connector_status_connected;
Sean Paul5137c8c2014-04-03 20:41:03 +0530[diff] [blame]1039
Andrzej Hajdaef6ce282015-07-09 16:28:07 +0200[diff] [blame]1040 return connector_status_disconnected;
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1041}
1042
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1043static void hdmi_connector_destroy(struct drm_connector *connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1044{
Andrzej Hajdaad279312014-09-09 15:16:13 +0200[diff] [blame]1045 drm_connector_unregister(connector);
1046 drm_connector_cleanup(connector);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1047}
1048
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1049static struct drm_connector_funcs hdmi_connector_funcs = {
Gustavo Padovan63498e32015-06-01 12:04:53 -0300[diff] [blame]1050 .dpms = drm_atomic_helper_connector_dpms,
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1051 .fill_modes = drm_helper_probe_single_connector_modes,
1052 .detect = hdmi_detect,
1053 .destroy = hdmi_connector_destroy,
Gustavo Padovan4ea95262015-06-01 12:04:44 -0300[diff] [blame]1054 .reset = drm_atomic_helper_connector_reset,
1055 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1056 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1057};
1058
1059static int hdmi_get_modes(struct drm_connector *connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1060{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1061 struct hdmi_context *hdata = ctx_from_connector(connector);
1062 struct edid *edid;
Andrzej Hajda64ebd892015-07-09 08:25:38 +0200[diff] [blame]1063 int ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1064
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]1065 if (!hdata->ddc_adpt)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1066 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1067
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]1068 edid = drm_get_edid(connector, hdata->ddc_adpt);
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1069 if (!edid)
1070 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1071
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1072 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
Rahul Sharma9c08e4b2013-01-04 07:59:11 -0500[diff] [blame]1073 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
1074 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1075 edid->width_cm, edid->height_cm);
Rahul Sharma9c08e4b2013-01-04 07:59:11 -0500[diff] [blame]1076
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1077 drm_mode_connector_update_edid_property(connector, edid);
1078
Andrzej Hajda64ebd892015-07-09 08:25:38 +0200[diff] [blame]1079 ret = drm_add_edid_modes(connector, edid);
1080
1081 kfree(edid);
1082
1083 return ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1084}
1085
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1086static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1087{
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1088 int i;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1089
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1090 for (i = 0; i < hdata->phy_conf_count; i++)
1091 if (hdata->phy_confs[i].pixel_clock == pixel_clock)
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1092 return i;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1093
1094 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1095 return -EINVAL;
1096}
1097
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1098static int hdmi_mode_valid(struct drm_connector *connector,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1099 struct drm_display_mode *mode)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1100{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1101 struct hdmi_context *hdata = ctx_from_connector(connector);
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1102 int ret;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1103
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1104 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1105 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1106 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1107 false, mode->clock * 1000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1108
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1109 ret = mixer_check_mode(mode);
1110 if (ret)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1111 return MODE_BAD;
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1112
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1113 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1114 if (ret < 0)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1115 return MODE_BAD;
1116
1117 return MODE_OK;
1118}
1119
1120static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1121{
1122 struct hdmi_context *hdata = ctx_from_connector(connector);
1123
1124 return hdata->encoder;
1125}
1126
1127static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1128 .get_modes = hdmi_get_modes,
1129 .mode_valid = hdmi_mode_valid,
1130 .best_encoder = hdmi_best_encoder,
1131};
1132
1133static int hdmi_create_connector(struct exynos_drm_display *display,
1134 struct drm_encoder *encoder)
1135{
Andrzej Hajda0d8424f82014-11-17 09:54:21 +0100[diff] [blame]1136 struct hdmi_context *hdata = display_to_hdmi(display);
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1137 struct drm_connector *connector = &hdata->connector;
1138 int ret;
1139
1140 hdata->encoder = encoder;
1141 connector->interlace_allowed = true;
1142 connector->polled = DRM_CONNECTOR_POLL_HPD;
1143
1144 ret = drm_connector_init(hdata->drm_dev, connector,
1145 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1146 if (ret) {
1147 DRM_ERROR("Failed to initialize connector with drm\n");
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1148 return ret;
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1149 }
1150
1151 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
Thomas Wood34ea3d32014-05-29 16:57:41 +0100[diff] [blame]1152 drm_connector_register(connector);
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1153 drm_mode_connector_attach_encoder(connector, encoder);
1154
1155 return 0;
1156}
1157
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1158static void hdmi_mode_fixup(struct exynos_drm_display *display,
1159 struct drm_connector *connector,
1160 const struct drm_display_mode *mode,
1161 struct drm_display_mode *adjusted_mode)
1162{
1163 struct drm_display_mode *m;
1164 int mode_ok;
1165
1166 DRM_DEBUG_KMS("%s\n", __FILE__);
1167
1168 drm_mode_set_crtcinfo(adjusted_mode, 0);
1169
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1170 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1171
1172 /* just return if user desired mode exists. */
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1173 if (mode_ok == MODE_OK)
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1174 return;
1175
1176 /*
1177 * otherwise, find the most suitable mode among modes and change it
1178 * to adjusted_mode.
1179 */
1180 list_for_each_entry(m, &connector->modes, head) {
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1181 mode_ok = hdmi_mode_valid(connector, m);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1182
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1183 if (mode_ok == MODE_OK) {
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1184 DRM_INFO("desired mode doesn't exist so\n");
1185 DRM_INFO("use the most suitable mode among modes.\n");
1186
1187 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1188 m->hdisplay, m->vdisplay, m->vrefresh);
1189
Sean Paul75626852014-01-30 16:19:16 -0500[diff] [blame]1190 drm_mode_copy(adjusted_mode, m);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1191 break;
1192 }
1193 }
1194}
1195
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1196static void hdmi_set_acr(u32 freq, u8 *acr)
1197{
1198 u32 n, cts;
1199
1200 switch (freq) {
1201 case 32000:
1202 n = 4096;
1203 cts = 27000;
1204 break;
1205 case 44100:
1206 n = 6272;
1207 cts = 30000;
1208 break;
1209 case 88200:
1210 n = 12544;
1211 cts = 30000;
1212 break;
1213 case 176400:
1214 n = 25088;
1215 cts = 30000;
1216 break;
1217 case 48000:
1218 n = 6144;
1219 cts = 27000;
1220 break;
1221 case 96000:
1222 n = 12288;
1223 cts = 27000;
1224 break;
1225 case 192000:
1226 n = 24576;
1227 cts = 27000;
1228 break;
1229 default:
1230 n = 0;
1231 cts = 0;
1232 break;
1233 }
1234
1235 acr[1] = cts >> 16;
1236 acr[2] = cts >> 8 & 0xff;
1237 acr[3] = cts & 0xff;
1238
1239 acr[4] = n >> 16;
1240 acr[5] = n >> 8 & 0xff;
1241 acr[6] = n & 0xff;
1242}
1243
1244static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1245{
1246 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1247 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1248 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1249 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1250 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1251 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1252 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1253 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1254 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1255
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1256 if (hdata->type == HDMI_TYPE13)
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1257 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1258 else
1259 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1260}
1261
1262static void hdmi_audio_init(struct hdmi_context *hdata)
1263{
Sachin Kamat7a9bf6e2014-07-02 09:33:07 +0530[diff] [blame]1264 u32 sample_rate, bits_per_sample;
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1265 u32 data_num, bit_ch, sample_frq;
1266 u32 val;
1267 u8 acr[7];
1268
1269 sample_rate = 44100;
1270 bits_per_sample = 16;
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1271
1272 switch (bits_per_sample) {
1273 case 20:
1274 data_num = 2;
1275 bit_ch = 1;
1276 break;
1277 case 24:
1278 data_num = 3;
1279 bit_ch = 1;
1280 break;
1281 default:
1282 data_num = 1;
1283 bit_ch = 0;
1284 break;
1285 }
1286
1287 hdmi_set_acr(sample_rate, acr);
1288 hdmi_reg_acr(hdata, acr);
1289
1290 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1291 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1292 | HDMI_I2S_MUX_ENABLE);
1293
1294 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1295 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1296
1297 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1298
1299 sample_frq = (sample_rate == 44100) ? 0 :
1300 (sample_rate == 48000) ? 2 :
1301 (sample_rate == 32000) ? 3 :
1302 (sample_rate == 96000) ? 0xa : 0x0;
1303
1304 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1305 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1306
1307 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1308 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1309
1310 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1311 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1312 | HDMI_I2S_SEL_LRCK(6));
1313 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1314 | HDMI_I2S_SEL_SDATA2(4));
1315 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1316 | HDMI_I2S_SEL_SDATA2(2));
1317 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1318
1319 /* I2S_CON_1 & 2 */
1320 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1321 | HDMI_I2S_L_CH_LOW_POL);
1322 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1323 | HDMI_I2S_SET_BIT_CH(bit_ch)
1324 | HDMI_I2S_SET_SDATA_BIT(data_num)
1325 | HDMI_I2S_BASIC_FORMAT);
1326
1327 /* Configure register related to CUV information */
1328 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1329 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1330 | HDMI_I2S_COPYRIGHT
1331 | HDMI_I2S_LINEAR_PCM
1332 | HDMI_I2S_CONSUMER_FORMAT);
1333 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1334 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1335 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1336 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1337 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1338 HDMI_I2S_ORG_SMP_FREQ_44_1
1339 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1340 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1341
1342 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1343}
1344
1345static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1346{
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]1347 if (hdata->dvi_mode)
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1348 return;
1349
1350 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1351 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1352 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1353}
1354
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1355static void hdmi_start(struct hdmi_context *hdata, bool start)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1356{
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1357 u32 val = start ? HDMI_TG_EN : 0;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1358
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1359 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1360 val |= HDMI_FIELD_EN;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1361
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1362 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1363 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1364}
1365
1366static void hdmi_conf_init(struct hdmi_context *hdata)
1367{
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1368 union hdmi_infoframe infoframe;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1369
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]1370 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1371 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1372 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1373
1374 /* choose HDMI mode */
1375 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1376 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
Shirish S9a8e1cb2014-02-14 13:04:57 +0530[diff] [blame]1377 /* Apply Video preable and Guard band in HDMI mode only */
1378 hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1379 /* disable bluescreen */
1380 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1381
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]1382 if (hdata->dvi_mode) {
1383 /* choose DVI mode */
1384 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1385 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1386 hdmi_reg_writeb(hdata, HDMI_CON_2,
1387 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1388 }
1389
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1390 if (hdata->type == HDMI_TYPE13) {
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1391 /* choose bluescreen (fecal) color */
1392 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1393 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1394 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1395
1396 /* enable AVI packet every vsync, fixes purple line problem */
1397 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1398 /* force RGB, look to CEA-861-D, table 7 for more detail */
1399 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1400 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1401
1402 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1403 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1404 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1405 } else {
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1406 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1407 infoframe.any.version = HDMI_AVI_VERSION;
1408 infoframe.any.length = HDMI_AVI_LENGTH;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1409 hdmi_reg_infoframe(hdata, &infoframe);
1410
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1411 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1412 infoframe.any.version = HDMI_AUI_VERSION;
1413 infoframe.any.length = HDMI_AUI_LENGTH;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1414 hdmi_reg_infoframe(hdata, &infoframe);
1415
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1416 /* enable AVI packet every vsync, fixes purple line problem */
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1417 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1418 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1419}
1420
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1421static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1422{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1423 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1424 const struct hdmi_v13_core_regs *core =
1425 &hdata->mode_conf.conf.v13_conf.core;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1426 int tries;
1427
1428 /* setting core registers */
1429 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1430 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1431 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1432 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1433 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1434 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1435 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1436 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1437 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1438 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1439 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1440 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1441 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1442 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1443 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1444 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1445 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1446 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1447 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1448 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1449 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1450 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1451 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1452 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1453 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1454 /* Timing generator registers */
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1455 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1456 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1457 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1458 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1459 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1460 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1461 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1462 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1463 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1464 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1465 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1466 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1467 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1468 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1469 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1470 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1471 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1472 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1473 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1474 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1475 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1476 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1477 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1478 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1479 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1480 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1481 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1482 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1483
1484 /* waiting for HDMIPHY's PLL to get to steady state */
1485 for (tries = 100; tries; --tries) {
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1486 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1487 if (val & HDMI_PHY_STATUS_READY)
1488 break;
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1489 usleep_range(1000, 2000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1490 }
1491 /* steady state not achieved */
1492 if (tries == 0) {
1493 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1494 hdmi_regs_dump(hdata, "timing apply");
1495 }
1496
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1497 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1498 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1499 clk_prepare_enable(hdata->res.sclk_hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1500
1501 /* enable HDMI and timing generator */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1502 hdmi_start(hdata, true);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1503}
1504
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1505static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1506{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1507 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1508 const struct hdmi_v14_core_regs *core =
1509 &hdata->mode_conf.conf.v14_conf.core;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1510 int tries;
1511
1512 /* setting core registers */
1513 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1514 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1515 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1516 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1517 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1518 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1519 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1520 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1521 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1522 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1523 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1524 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1525 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1526 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1527 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1528 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1529 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1530 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1531 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1532 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1533 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1534 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1535 core->v_sync_line_bef_2[0]);
1536 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1537 core->v_sync_line_bef_2[1]);
1538 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1539 core->v_sync_line_bef_1[0]);
1540 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1541 core->v_sync_line_bef_1[1]);
1542 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1543 core->v_sync_line_aft_2[0]);
1544 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1545 core->v_sync_line_aft_2[1]);
1546 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1547 core->v_sync_line_aft_1[0]);
1548 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1549 core->v_sync_line_aft_1[1]);
1550 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1551 core->v_sync_line_aft_pxl_2[0]);
1552 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1553 core->v_sync_line_aft_pxl_2[1]);
1554 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1555 core->v_sync_line_aft_pxl_1[0]);
1556 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1557 core->v_sync_line_aft_pxl_1[1]);
1558 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1559 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1560 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1561 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1562 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1563 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1564 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1565 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1566 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1567 core->v_sync_line_aft_3[0]);
1568 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1569 core->v_sync_line_aft_3[1]);
1570 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1571 core->v_sync_line_aft_4[0]);
1572 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1573 core->v_sync_line_aft_4[1]);
1574 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1575 core->v_sync_line_aft_5[0]);
1576 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1577 core->v_sync_line_aft_5[1]);
1578 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1579 core->v_sync_line_aft_6[0]);
1580 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1581 core->v_sync_line_aft_6[1]);
1582 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1583 core->v_sync_line_aft_pxl_3[0]);
1584 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1585 core->v_sync_line_aft_pxl_3[1]);
1586 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1587 core->v_sync_line_aft_pxl_4[0]);
1588 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1589 core->v_sync_line_aft_pxl_4[1]);
1590 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1591 core->v_sync_line_aft_pxl_5[0]);
1592 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1593 core->v_sync_line_aft_pxl_5[1]);
1594 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1595 core->v_sync_line_aft_pxl_6[0]);
1596 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1597 core->v_sync_line_aft_pxl_6[1]);
1598 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1599 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1600 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1601 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1602 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1603 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1604 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1605 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1606 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1607 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1608 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1609 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1610
1611 /* Timing generator registers */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1612 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1613 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1614 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1615 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1616 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1617 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1618 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1619 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1620 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1621 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1622 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1623 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1624 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1625 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1626 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1627 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1628 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1629 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1630 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1631 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1632 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1633 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1634 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1635 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1636 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1637 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1638 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1639 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1640 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1641 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1642 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1643 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1644 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1645
1646 /* waiting for HDMIPHY's PLL to get to steady state */
1647 for (tries = 100; tries; --tries) {
1648 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1649 if (val & HDMI_PHY_STATUS_READY)
1650 break;
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1651 usleep_range(1000, 2000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1652 }
1653 /* steady state not achieved */
1654 if (tries == 0) {
1655 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1656 hdmi_regs_dump(hdata, "timing apply");
1657 }
1658
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1659 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1660 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1661 clk_prepare_enable(hdata->res.sclk_hdmi);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1662
1663 /* enable HDMI and timing generator */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1664 hdmi_start(hdata, true);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1665}
1666
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1667static void hdmi_mode_apply(struct hdmi_context *hdata)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1668{
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1669 if (hdata->type == HDMI_TYPE13)
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1670 hdmi_v13_mode_apply(hdata);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1671 else
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1672 hdmi_v14_mode_apply(hdata);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1673}
1674
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1675static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1676{
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1677 u32 reg;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1678
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1679 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1680 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1681 clk_prepare_enable(hdata->res.sclk_hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1682
1683 /* operation mode */
Joonyoung Shim265134a2015-01-12 14:35:16 +0900[diff] [blame]1684 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1685 HDMI_PHY_ENABLE_MODE_SET);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1686
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1687 if (hdata->type == HDMI_TYPE13)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1688 reg = HDMI_V13_PHY_RSTOUT;
1689 else
1690 reg = HDMI_PHY_RSTOUT;
1691
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1692 /* reset hdmiphy */
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1693 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1694 usleep_range(10000, 12000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1695 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1696 usleep_range(10000, 12000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1697}
1698
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1699static void hdmiphy_poweron(struct hdmi_context *hdata)
1700{
Shirish S6a296e22014-04-03 20:41:02 +0530[diff] [blame]1701 if (hdata->type != HDMI_TYPE14)
1702 return;
1703
1704 DRM_DEBUG_KMS("\n");
1705
1706 /* For PHY Mode Setting */
1707 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1708 HDMI_PHY_ENABLE_MODE_SET);
1709 /* Phy Power On */
1710 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1711 HDMI_PHY_POWER_ON);
1712 /* For PHY Mode Setting */
1713 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1714 HDMI_PHY_DISABLE_MODE_SET);
1715 /* PHY SW Reset */
1716 hdmiphy_conf_reset(hdata);
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1717}
1718
1719static void hdmiphy_poweroff(struct hdmi_context *hdata)
1720{
Shirish S6a296e22014-04-03 20:41:02 +0530[diff] [blame]1721 if (hdata->type != HDMI_TYPE14)
1722 return;
1723
1724 DRM_DEBUG_KMS("\n");
1725
1726 /* PHY SW Reset */
1727 hdmiphy_conf_reset(hdata);
1728 /* For PHY Mode Setting */
1729 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1730 HDMI_PHY_ENABLE_MODE_SET);
1731
1732 /* PHY Power Off */
1733 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1734 HDMI_PHY_POWER_OFF);
1735
1736 /* For PHY Mode Setting */
1737 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1738 HDMI_PHY_DISABLE_MODE_SET);
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1739}
1740
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1741static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1742{
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1743 int ret;
1744 int i;
1745
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1746 /* pixel clock */
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1747 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1748 if (i < 0) {
1749 DRM_ERROR("failed to find hdmiphy conf\n");
1750 return;
1751 }
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1752
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1753 ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32);
1754 if (ret) {
1755 DRM_ERROR("failed to configure hdmiphy\n");
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1756 return;
1757 }
1758
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1759 usleep_range(10000, 12000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1760
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1761 ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1762 HDMI_PHY_DISABLE_MODE_SET);
1763 if (ret) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1764 DRM_ERROR("failed to enable hdmiphy\n");
1765 return;
1766 }
1767
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1768}
1769
1770static void hdmi_conf_apply(struct hdmi_context *hdata)
1771{
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1772 hdmiphy_conf_reset(hdata);
1773 hdmiphy_conf_apply(hdata);
1774
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1775 hdmi_start(hdata, false);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1776 hdmi_conf_init(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]1777
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1778 hdmi_audio_init(hdata);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1779
1780 /* setting core registers */
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1781 hdmi_mode_apply(hdata);
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1782 hdmi_audio_control(hdata, true);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1783
1784 hdmi_regs_dump(hdata, "start");
1785}
1786
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1787static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1788{
1789 int i;
1790 BUG_ON(num_bytes > 4);
1791 for (i = 0; i < num_bytes; i++)
1792 reg_pair[i] = (value >> (8 * i)) & 0xff;
1793}
1794
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1795static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1796 struct drm_display_mode *m)
1797{
1798 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1799 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1800 unsigned int val;
1801
1802 hdata->mode_conf.cea_video_id =
1803 drm_match_cea_mode((struct drm_display_mode *)m);
1804 hdata->mode_conf.pixel_clock = m->clock * 1000;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]1805 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1806
1807 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1808 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1809
1810 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1811 hdmi_set_reg(core->vsync_pol, 1, val);
1812
1813 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1814 hdmi_set_reg(core->int_pro_mode, 1, val);
1815
1816 val = (m->hsync_start - m->hdisplay - 2);
1817 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1818 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1819 hdmi_set_reg(core->h_sync_gen, 3, val);
1820
1821 /*
1822 * Quirk requirement for exynos HDMI IP design,
1823 * 2 pixels less than the actual calculation for hsync_start
1824 * and end.
1825 */
1826
1827 /* Following values & calculations differ for different type of modes */
1828 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1829 /* Interlaced Mode */
1830 val = ((m->vsync_end - m->vdisplay) / 2);
1831 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1832 hdmi_set_reg(core->v_sync_gen1, 3, val);
1833
1834 val = m->vtotal / 2;
1835 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1836 hdmi_set_reg(core->v_blank, 3, val);
1837
1838 val = (m->vtotal +
1839 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1840 val |= m->vtotal << 11;
1841 hdmi_set_reg(core->v_blank_f, 3, val);
1842
1843 val = ((m->vtotal / 2) + 7);
1844 val |= ((m->vtotal / 2) + 2) << 12;
1845 hdmi_set_reg(core->v_sync_gen2, 3, val);
1846
1847 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1848 val |= ((m->htotal / 2) +
1849 (m->hsync_start - m->hdisplay)) << 12;
1850 hdmi_set_reg(core->v_sync_gen3, 3, val);
1851
1852 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1853 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1854
1855 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1856 } else {
1857 /* Progressive Mode */
1858
1859 val = m->vtotal;
1860 val |= (m->vtotal - m->vdisplay) << 11;
1861 hdmi_set_reg(core->v_blank, 3, val);
1862
1863 hdmi_set_reg(core->v_blank_f, 3, 0);
1864
1865 val = (m->vsync_end - m->vdisplay);
1866 val |= ((m->vsync_start - m->vdisplay) << 12);
1867 hdmi_set_reg(core->v_sync_gen1, 3, val);
1868
1869 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1870 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1871 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1872 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1873 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1874 }
1875
1876 /* Timing generator registers */
1877 hdmi_set_reg(tg->cmd, 1, 0x0);
1878 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1879 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1880 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1881 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1882 hdmi_set_reg(tg->vsync, 2, 0x1);
1883 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1884 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1885 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1886 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1887 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1888 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1889 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1890}
1891
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1892static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1893 struct drm_display_mode *m)
1894{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1895 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1896 struct hdmi_v14_core_regs *core =
1897 &hdata->mode_conf.conf.v14_conf.core;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1898
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1899 hdata->mode_conf.cea_video_id =
1900 drm_match_cea_mode((struct drm_display_mode *)m);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1901 hdata->mode_conf.pixel_clock = m->clock * 1000;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]1902 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1903
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1904 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1905 hdmi_set_reg(core->v_line, 2, m->vtotal);
1906 hdmi_set_reg(core->h_line, 2, m->htotal);
1907 hdmi_set_reg(core->hsync_pol, 1,
1908 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1909 hdmi_set_reg(core->vsync_pol, 1,
1910 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1911 hdmi_set_reg(core->int_pro_mode, 1,
1912 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1913
1914 /*
1915 * Quirk requirement for exynos 5 HDMI IP design,
1916 * 2 pixels less than the actual calculation for hsync_start
1917 * and end.
1918 */
1919
1920 /* Following values & calculations differ for different type of modes */
1921 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1922 /* Interlaced Mode */
1923 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1924 (m->vsync_end - m->vdisplay) / 2);
1925 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1926 (m->vsync_start - m->vdisplay) / 2);
1927 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1928 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1929 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1930 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1931 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1932 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1933 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1934 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1935 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1936 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1937 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1938 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1939 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1940 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1941 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1942 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1943 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1944 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1945 } else {
1946 /* Progressive Mode */
1947 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1948 m->vsync_end - m->vdisplay);
1949 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1950 m->vsync_start - m->vdisplay);
1951 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1952 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1953 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1954 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1955 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1956 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1957 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1958 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1959 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1960 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1961 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1962 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1963 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1964 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1965 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1966 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1967 }
1968
1969 /* Following values & calculations are same irrespective of mode type */
1970 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1971 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1972 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1973 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1974 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1975 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1976 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1977 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1978 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1979 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1980 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1981 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1982 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1983 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1984 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1985 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1986 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1987 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1988 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1989 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1990
1991 /* Timing generator registers */
1992 hdmi_set_reg(tg->cmd, 1, 0x0);
1993 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1994 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1995 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1996 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1997 hdmi_set_reg(tg->vsync, 2, 0x1);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1998 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1999 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]2000 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]2001 hdmi_set_reg(tg->tg_3d, 1, 0x0);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]2002}
2003
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2004static void hdmi_mode_set(struct exynos_drm_display *display,
2005 struct drm_display_mode *mode)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2006{
Andrzej Hajda0d8424f82014-11-17 09:54:21 +0100[diff] [blame]2007 struct hdmi_context *hdata = display_to_hdmi(display);
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]2008 struct drm_display_mode *m = mode;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2009
YoungJun Chocbc4c332013-06-12 10:44:40 +0900[diff] [blame]2010 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
2011 m->hdisplay, m->vdisplay,
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]2012 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
Tobias Jakobi1e6d4592015-04-07 01:14:50 +0200[diff] [blame]2013 "INTERLACED" : "PROGRESSIVE");
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2014
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]2015 /* preserve mode information for later use. */
2016 drm_mode_copy(&hdata->current_mode, mode);
2017
Sachin Kamat5f46c332013-04-26 11:29:00 +0530[diff] [blame]2018 if (hdata->type == HDMI_TYPE13)
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]2019 hdmi_v13_mode_set(hdata, mode);
Sachin Kamat5f46c332013-04-26 11:29:00 +0530[diff] [blame]2020 else
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]2021 hdmi_v14_mode_set(hdata, mode);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2022}
2023
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2024static void hdmi_commit(struct exynos_drm_display *display)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2025{
Andrzej Hajda0d8424f82014-11-17 09:54:21 +0100[diff] [blame]2026 struct hdmi_context *hdata = display_to_hdmi(display);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2027
Andrzej Hajda882a0642015-07-09 16:28:08 +0200[diff] [blame^]2028 if (!hdata->powered)
Shirish Sdda90122013-01-23 22:03:18 -0500[diff] [blame]2029 return;
Shirish Sdda90122013-01-23 22:03:18 -0500[diff] [blame]2030
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2031 hdmi_conf_apply(hdata);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2032}
2033
Joonyoung Shim92dc7a02015-01-30 16:43:02 +0900[diff] [blame]2034static void hdmi_poweron(struct hdmi_context *hdata)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2035{
2036 struct hdmi_resources *res = &hdata->res;
2037
Andrzej Hajda882a0642015-07-09 16:28:08 +0200[diff] [blame^]2038 if (hdata->powered)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2039 return;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2040
2041 hdata->powered = true;
2042
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2043 pm_runtime_get_sync(hdata->dev);
2044
Seung-Woo Kimad079452013-06-05 14:34:38 +0900[diff] [blame]2045 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
2046 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
2047
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]2048 /* set pmu hdmiphy control bit to enable hdmiphy */
2049 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2050 PMU_HDMI_PHY_ENABLE_BIT, 1);
2051
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]2052 clk_prepare_enable(res->hdmi);
2053 clk_prepare_enable(res->sclk_hdmi);
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]2054
2055 hdmiphy_poweron(hdata);
Joonyoung Shim92dc7a02015-01-30 16:43:02 +0900[diff] [blame]2056 hdmi_commit(&hdata->display);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2057}
2058
Joonyoung Shim92dc7a02015-01-30 16:43:02 +0900[diff] [blame]2059static void hdmi_poweroff(struct hdmi_context *hdata)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2060{
2061 struct hdmi_resources *res = &hdata->res;
2062
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2063 if (!hdata->powered)
Andrzej Hajda882a0642015-07-09 16:28:08 +0200[diff] [blame^]2064 return;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2065
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]2066 /* HDMI System Disable */
2067 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
2068
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]2069 hdmiphy_poweroff(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2070
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2071 cancel_delayed_work(&hdata->hotplug_work);
2072
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]2073 clk_disable_unprepare(res->sclk_hdmi);
2074 clk_disable_unprepare(res->hdmi);
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]2075
2076 /* reset pmu hdmiphy control bit to disable hdmiphy */
2077 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2078 PMU_HDMI_PHY_ENABLE_BIT, 0);
2079
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2080 regulator_bulk_disable(res->regul_count, res->regul_bulk);
2081
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2082 pm_runtime_put_sync(hdata->dev);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2083
2084 hdata->powered = false;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2085}
2086
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2087static void hdmi_dpms(struct exynos_drm_display *display, int mode)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2088{
Andrzej Hajda0d8424f82014-11-17 09:54:21 +0100[diff] [blame]2089 struct hdmi_context *hdata = display_to_hdmi(display);
Inki Dae245f98f2014-06-13 17:44:40 +0900[diff] [blame]2090 struct drm_encoder *encoder = hdata->encoder;
2091 struct drm_crtc *crtc = encoder->crtc;
Jani Nikulab0f87782015-03-11 11:50:59 +0200[diff] [blame]2092 const struct drm_crtc_helper_funcs *funcs = NULL;
Inki Dae245f98f2014-06-13 17:44:40 +0900[diff] [blame]2093
YoungJun Chocbc4c332013-06-12 10:44:40 +0900[diff] [blame]2094 DRM_DEBUG_KMS("mode %d\n", mode);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2095
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2096 switch (mode) {
2097 case DRM_MODE_DPMS_ON:
Joonyoung Shim92dc7a02015-01-30 16:43:02 +0900[diff] [blame]2098 hdmi_poweron(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2099 break;
2100 case DRM_MODE_DPMS_STANDBY:
2101 case DRM_MODE_DPMS_SUSPEND:
2102 case DRM_MODE_DPMS_OFF:
Inki Dae245f98f2014-06-13 17:44:40 +0900[diff] [blame]2103 /*
2104 * The SFRs of VP and Mixer are updated by Vertical Sync of
2105 * Timing generator which is a part of HDMI so the sequence
2106 * to disable TV Subsystem should be as following,
2107 * VP -> Mixer -> HDMI
2108 *
2109 * Below codes will try to disable Mixer and VP(if used)
2110 * prior to disabling HDMI.
2111 */
2112 if (crtc)
2113 funcs = crtc->helper_private;
Gustavo Padovan63498e32015-06-01 12:04:53 -0300[diff] [blame]2114 if (funcs && funcs->disable)
2115 (*funcs->disable)(crtc);
Inki Dae245f98f2014-06-13 17:44:40 +0900[diff] [blame]2116
Joonyoung Shim92dc7a02015-01-30 16:43:02 +0900[diff] [blame]2117 hdmi_poweroff(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2118 break;
2119 default:
2120 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2121 break;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2122 }
2123}
2124
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2125static struct exynos_drm_display_ops hdmi_display_ops = {
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]2126 .create_connector = hdmi_create_connector,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2127 .mode_fixup = hdmi_mode_fixup,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2128 .mode_set = hdmi_mode_set,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2129 .dpms = hdmi_dpms,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2130 .commit = hdmi_commit,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2131};
2132
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2133static void hdmi_hotplug_work_func(struct work_struct *work)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2134{
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2135 struct hdmi_context *hdata;
2136
2137 hdata = container_of(work, struct hdmi_context, hotplug_work.work);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2138
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]2139 if (hdata->drm_dev)
2140 drm_helper_hpd_irq_event(hdata->drm_dev);
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2141}
2142
2143static irqreturn_t hdmi_irq_thread(int irq, void *arg)
2144{
2145 struct hdmi_context *hdata = arg;
2146
2147 mod_delayed_work(system_wq, &hdata->hotplug_work,
2148 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2149
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2150 return IRQ_HANDLED;
2151}
2152
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2153static int hdmi_resources_init(struct hdmi_context *hdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2154{
2155 struct device *dev = hdata->dev;
2156 struct hdmi_resources *res = &hdata->res;
2157 static char *supply[] = {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2158 "vdd",
2159 "vdd_osc",
2160 "vdd_pll",
2161 };
2162 int i, ret;
2163
2164 DRM_DEBUG_KMS("HDMI resource init\n");
2165
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2166 /* get clocks, power */
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2167 res->hdmi = devm_clk_get(dev, "hdmi");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2168 if (IS_ERR(res->hdmi)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2169 DRM_ERROR("failed to get clock 'hdmi'\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2170 ret = PTR_ERR(res->hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2171 goto fail;
2172 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2173 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2174 if (IS_ERR(res->sclk_hdmi)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2175 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2176 ret = PTR_ERR(res->sclk_hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2177 goto fail;
2178 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2179 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2180 if (IS_ERR(res->sclk_pixel)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2181 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2182 ret = PTR_ERR(res->sclk_pixel);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2183 goto fail;
2184 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2185 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2186 if (IS_ERR(res->sclk_hdmiphy)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2187 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2188 ret = PTR_ERR(res->sclk_hdmiphy);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2189 goto fail;
2190 }
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]2191 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
2192 if (IS_ERR(res->mout_hdmi)) {
2193 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2194 ret = PTR_ERR(res->mout_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]2195 goto fail;
2196 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2197
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]2198 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2199
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2200 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
Sachin Kamatadc837a2012-08-31 15:50:47 +0530[diff] [blame]2201 sizeof(res->regul_bulk[0]), GFP_KERNEL);
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2202 if (!res->regul_bulk) {
2203 ret = -ENOMEM;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2204 goto fail;
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2205 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2206 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2207 res->regul_bulk[i].supply = supply[i];
2208 res->regul_bulk[i].consumer = NULL;
2209 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2210 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2211 if (ret) {
2212 DRM_ERROR("failed to get regulators\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2213 return ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2214 }
2215 res->regul_count = ARRAY_SIZE(supply);
2216
Marek Szyprowski05fdf982014-07-01 10:10:06 +0200[diff] [blame]2217 res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en");
2218 if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) {
2219 DRM_ERROR("failed to get hdmi-en regulator\n");
2220 return PTR_ERR(res->reg_hdmi_en);
2221 }
2222 if (!IS_ERR(res->reg_hdmi_en)) {
2223 ret = regulator_enable(res->reg_hdmi_en);
2224 if (ret) {
2225 DRM_ERROR("failed to enable hdmi-en regulator\n");
2226 return ret;
2227 }
2228 } else
2229 res->reg_hdmi_en = NULL;
2230
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2231 return ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2232fail:
2233 DRM_ERROR("HDMI resource init - failed\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2234 return ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2235}
2236
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2237static struct of_device_id hdmi_match_types[] = {
2238 {
2239 .compatible = "samsung,exynos5-hdmi",
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2240 .data = &exynos5_hdmi_driver_data,
Tomasz Stanislawskic119ed02012-10-04 20:48:44 +0530[diff] [blame]2241 }, {
Marek Szyprowskiff830c92014-07-01 10:10:07 +0200[diff] [blame]2242 .compatible = "samsung,exynos4210-hdmi",
2243 .data = &exynos4210_hdmi_driver_data,
2244 }, {
Rahul Sharmacc57caf2013-06-19 18:21:07 +0530[diff] [blame]2245 .compatible = "samsung,exynos4212-hdmi",
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2246 .data = &exynos4212_hdmi_driver_data,
Rahul Sharmacc57caf2013-06-19 18:21:07 +0530[diff] [blame]2247 }, {
Rahul Sharmaa18a2dd2014-04-20 15:51:17 +0530[diff] [blame]2248 .compatible = "samsung,exynos5420-hdmi",
2249 .data = &exynos5420_hdmi_driver_data,
2250 }, {
Tomasz Stanislawskic119ed02012-10-04 20:48:44 +0530[diff] [blame]2251 /* end node */
2252 }
2253};
Sjoerd Simons39b58a32014-07-18 22:36:41 +0200[diff] [blame]2254MODULE_DEVICE_TABLE (of, hdmi_match_types);
Tomasz Stanislawskic119ed02012-10-04 20:48:44 +0530[diff] [blame]2255
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2256static int hdmi_bind(struct device *dev, struct device *master, void *data)
2257{
2258 struct drm_device *drm_dev = data;
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2259 struct hdmi_context *hdata = dev_get_drvdata(dev);
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2260
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2261 hdata->drm_dev = drm_dev;
2262
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2263 return exynos_drm_create_enc_conn(drm_dev, &hdata->display);
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2264}
2265
2266static void hdmi_unbind(struct device *dev, struct device *master, void *data)
2267{
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2268}
2269
2270static const struct component_ops hdmi_component_ops = {
2271 .bind = hdmi_bind,
2272 .unbind = hdmi_unbind,
2273};
2274
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2275static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
2276{
2277 const char *compatible_str = "samsung,exynos4210-hdmiddc";
2278 struct device_node *np;
2279
2280 np = of_find_compatible_node(NULL, NULL, compatible_str);
2281 if (np)
2282 return of_get_next_parent(np);
2283
2284 return NULL;
2285}
2286
2287static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
2288{
2289 const char *compatible_str = "samsung,exynos4212-hdmiphy";
2290
2291 return of_find_compatible_node(NULL, NULL, compatible_str);
2292}
2293
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2294static int hdmi_probe(struct platform_device *pdev)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2295{
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2296 struct device_node *ddc_node, *phy_node;
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2297 struct hdmi_driver_data *drv_data;
2298 const struct of_device_id *match;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2299 struct device *dev = &pdev->dev;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2300 struct hdmi_context *hdata;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2301 struct resource *res;
2302 int ret;
2303
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2304 if (!dev->of_node)
2305 return -ENODEV;
2306
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2307 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2308 if (!hdata)
2309 return -ENOMEM;
2310
2311 hdata->display.type = EXYNOS_DISPLAY_TYPE_HDMI;
2312 hdata->display.ops = &hdmi_display_ops;
2313
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2314 platform_set_drvdata(pdev, hdata);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2315
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2316 match = of_match_node(hdmi_match_types, dev->of_node);
Andrzej Hajda86650402015-06-11 23:23:37 +0900[diff] [blame]2317 if (!match)
2318 return -ENODEV;
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2319
2320 drv_data = (struct hdmi_driver_data *)match->data;
2321 hdata->type = drv_data->type;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2322 hdata->phy_confs = drv_data->phy_confs;
2323 hdata->phy_conf_count = drv_data->phy_conf_count;
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2324
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2325 hdata->dev = dev;
Andrzej Hajdad36b3002015-07-09 16:28:06 +0200[diff] [blame]2326 hdata->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpio", 0);
2327 if (hdata->hpd_gpio < 0) {
2328 DRM_ERROR("cannot get hpd gpio property\n");
2329 return hdata->hpd_gpio;
2330 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2331
2332 ret = hdmi_resources_init(hdata);
2333 if (ret) {
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2334 DRM_ERROR("hdmi_resources_init failed\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2335 return ret;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2336 }
2337
2338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Seung-Woo Kimd873ab92013-05-22 21:14:14 +0900[diff] [blame]2339 hdata->regs = devm_ioremap_resource(dev, res);
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2340 if (IS_ERR(hdata->regs)) {
2341 ret = PTR_ERR(hdata->regs);
Andrzej Hajda86650402015-06-11 23:23:37 +0900[diff] [blame]2342 return ret;
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2343 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2344
Seung-Woo Kimd873ab92013-05-22 21:14:14 +0900[diff] [blame]2345 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2346 if (ret) {
2347 DRM_ERROR("failed to request HPD gpio\n");
Andrzej Hajda86650402015-06-11 23:23:37 +0900[diff] [blame]2348 return ret;
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2349 }
2350
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2351 ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2352 if (ddc_node)
2353 goto out_get_ddc_adpt;
2354
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2355 /* DDC i2c driver */
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2356 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2357 if (!ddc_node) {
2358 DRM_ERROR("Failed to find ddc node in device tree\n");
Andrzej Hajda86650402015-06-11 23:23:37 +0900[diff] [blame]2359 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2360 }
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2361
2362out_get_ddc_adpt:
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2363 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2364 if (!hdata->ddc_adpt) {
2365 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2366 return -EPROBE_DEFER;
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2367 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2368
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2369 phy_node = hdmi_legacy_phy_dt_binding(dev);
2370 if (phy_node)
2371 goto out_get_phy_port;
2372
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2373 /* hdmiphy i2c driver */
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2374 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2375 if (!phy_node) {
2376 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2377 ret = -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2378 goto err_ddc;
2379 }
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2380
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2381out_get_phy_port:
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2382 if (drv_data->is_apb_phy) {
2383 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2384 if (!hdata->regs_hdmiphy) {
2385 DRM_ERROR("failed to ioremap hdmi phy\n");
2386 ret = -ENOMEM;
2387 goto err_ddc;
2388 }
2389 } else {
2390 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2391 if (!hdata->hdmiphy_port) {
2392 DRM_ERROR("Failed to get hdmi phy i2c client\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2393 ret = -EPROBE_DEFER;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2394 goto err_ddc;
2395 }
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2396 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2397
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2398 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2399 if (hdata->irq < 0) {
2400 DRM_ERROR("failed to get GPIO irq\n");
2401 ret = hdata->irq;
Joonyoung Shim66265a22012-04-23 19:35:49 +0900[diff] [blame]2402 goto err_hdmiphy;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2403 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2404
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2405 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2406
Seung-Woo Kimdcb9a7c2013-05-22 21:14:17 +0900[diff] [blame]2407 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2408 hdmi_irq_thread, IRQF_TRIGGER_RISING |
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2409 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2410 "hdmi", hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2411 if (ret) {
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2412 DRM_ERROR("failed to register hdmi interrupt\n");
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2413 goto err_hdmiphy;
2414 }
2415
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]2416 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2417 "samsung,syscon-phandle");
2418 if (IS_ERR(hdata->pmureg)) {
2419 DRM_ERROR("syscon regmap lookup failed.\n");
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2420 ret = -EPROBE_DEFER;
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame]2421 goto err_hdmiphy;
2422 }
2423
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2424 pm_runtime_enable(dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2425
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2426 ret = component_add(&pdev->dev, &hdmi_component_ops);
2427 if (ret)
2428 goto err_disable_pm_runtime;
2429
2430 return ret;
2431
2432err_disable_pm_runtime:
2433 pm_runtime_disable(dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2434
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2435err_hdmiphy:
Paul Taysomb21a3bf2014-05-09 15:06:28 +0900[diff] [blame]2436 if (hdata->hdmiphy_port)
2437 put_device(&hdata->hdmiphy_port->dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2438err_ddc:
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2439 put_device(&hdata->ddc_adpt->dev);
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2440
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2441 return ret;
2442}
2443
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2444static int hdmi_remove(struct platform_device *pdev)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2445{
Andrzej Hajda930865f2014-11-17 09:54:20 +0100[diff] [blame]2446 struct hdmi_context *hdata = platform_get_drvdata(pdev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2447
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2448 cancel_delayed_work_sync(&hdata->hotplug_work);
2449
Marek Szyprowski05fdf982014-07-01 10:10:06 +0200[diff] [blame]2450 if (hdata->res.reg_hdmi_en)
2451 regulator_disable(hdata->res.reg_hdmi_en);
2452
Seung-Woo Kim9d1e25c2014-07-28 17:15:22 +0900[diff] [blame]2453 if (hdata->hdmiphy_port)
2454 put_device(&hdata->hdmiphy_port->dev);
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2455 put_device(&hdata->ddc_adpt->dev);
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2456
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2457 pm_runtime_disable(&pdev->dev);
Inki Daedf5225b2014-05-29 18:28:02 +0900[diff] [blame]2458 component_del(&pdev->dev, &hdmi_component_ops);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2459
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2460 return 0;
2461}
2462
2463struct platform_driver hdmi_driver = {
2464 .probe = hdmi_probe,
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2465 .remove = hdmi_remove,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2466 .driver = {
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2467 .name = "exynos-hdmi",
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2468 .owner = THIS_MODULE,
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2469 .of_match_table = hdmi_match_types,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2470 },
2471};