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gerrit-public.fairphone.software / kernel / msm-4.19 / 8c038e7e14b1c5f156745e3c4df0a3aa46173dd9 / . / arch / arm / boot / dts / spear320.dtsi
blob: ffea342aeec99575612c38224f05aeaa70594640 [file] [log] [blame]
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]1/*
2 * DTS file for SPEAr320 SoC
3 *
Viresh Kumar10d89352012-06-20 12:53:02 -0700[diff] [blame]4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]21 ranges = <0x40000000 0x40000000 0x80000000
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]22 0xd0000000 0xd0000000 0x30000000>;
23
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]24 pinmux: pinmux@b3000000 {
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
Haojian Zhuang86853c82013-02-17 19:42:47 +0800[diff] [blame]27 #gpio-range-cells = <3>;
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]28 };
29
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]30 clcd@90000000 {
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800[diff] [blame]31 compatible = "arm,pl110", "arm,primecell";
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]32 reg = <0x90000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]35 status = "disabled";
36 };
37
38 fsmc: flash@4c000000 {
39 compatible = "st,spear600-fsmc-nand";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x4c000000 0x1000 /* FSMC Register */
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200[diff] [blame]43 0x50000000 0x0010 /* NAND Base DATA */
44 0x50020000 0x0010 /* NAND Base ADDR */
45 0x50010000 0x0010>; /* NAND Base CMD */
46 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]47 status = "disabled";
48 };
49
50 sdhci@70000000 {
51 compatible = "st,sdhci-spear";
52 reg = <0x70000000 0x100>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]55 status = "disabled";
56 };
57
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]66 spi1: spi@a5000000 {
67 compatible = "arm,pl022", "arm,primecell";
68 reg = <0xa5000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]71 #address-cells = <1>;
72 #size-cells = <0>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]73 status = "disabled";
74 };
75
76 spi2: spi@a6000000 {
77 compatible = "arm,pl022", "arm,primecell";
78 reg = <0xa6000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]81 #address-cells = <1>;
82 #size-cells = <0>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]83 status = "disabled";
84 };
85
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]86 pwm: pwm@a8000000 {
87 compatible ="st,spear-pwm";
88 reg = <0xa8000000 0x1000>;
89 #pwm-cells = <2>;
90 status = "disabled";
91 };
92
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]93 apb {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "simple-bus";
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800[diff] [blame]97 ranges = <0xa0000000 0xa0000000 0x20000000
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]98 0xd0000000 0xd0000000 0x30000000>;
99
100 i2c1: i2c@a7000000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "snps,designware-i2c";
104 reg = <0xa7000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]107 status = "disabled";
108 };
109
110 serial@a3000000 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0xa3000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]115 status = "disabled";
116 };
117
118 serial@a4000000 {
119 compatible = "arm,pl011", "arm,primecell";
120 reg = <0xa4000000 0x1000>;
Shiraz Hashim86edd7b2012-08-03 16:00:18 +0530[diff] [blame]121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]123 status = "disabled";
124 };
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]125
126 gpiopinctrl: gpio@b3000000 {
127 compatible = "st,spear-plgpio";
128 reg = <0xb3000000 0x1000>;
129 #interrupt-cells = <1>;
130 interrupt-controller;
131 gpio-controller;
132 #gpio-cells = <2>;
Haojian Zhuang86853c82013-02-17 19:42:47 +0800[diff] [blame]133 gpio-ranges = <&pinmux 0 0 102>;
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]134 status = "disabled";
135
136 st-plgpio,ngpio = <102>;
137 st-plgpio,enb-reg = <0x24>;
138 st-plgpio,wdata-reg = <0x34>;
139 st-plgpio,dir-reg = <0x44>;
140 st-plgpio,ie-reg = <0x64>;
141 st-plgpio,rdata-reg = <0x54>;
142 st-plgpio,mis-reg = <0x84>;
143 st-plgpio,eit-reg = <0x94>;
144 };
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]145 };
146 };
147};