blob: ab8d901b5ab6c83593efb541f00e9aca87e7cf64 [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +02001/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
10 reg = < 0x80000000 0x40000000 >;
11 };
12
Stephen Warrene5cbeef2012-03-13 13:28:02 -060013 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
Stephen Warren8c6a3852012-03-27 12:41:37 -060054 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -060063 };
64 };
65
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020066 serial@70006000 {
67 clock-frequency = < 408000000 >;
68 };
69
Stephen Warren8c690fd2012-02-02 12:24:19 -070070 serial@70006040 {
71 status = "disable";
72 };
73
74 serial@70006200 {
75 status = "disable";
76 };
77
78 serial@70006300 {
79 status = "disable";
80 };
81
82 serial@70006400 {
83 status = "disable";
84 };
85
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020086 i2c@7000c000 {
87 clock-frequency = <100000>;
88 };
89
90 i2c@7000c400 {
91 clock-frequency = <100000>;
92 };
93
94 i2c@7000c500 {
95 clock-frequency = <100000>;
96 };
97
98 i2c@7000c700 {
99 clock-frequency = <100000>;
100 };
101
102 i2c@7000d000 {
103 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600104
105 wm8903: wm8903@1a {
106 compatible = "wlf,wm8903";
107 reg = <0x1a>;
108 interrupt-parent = <&gpio>;
109 interrupts = <179 0x04>; /* gpio PW3 */
110
111 gpio-controller;
112 #gpio-cells = <2>;
113
114 micdet-cfg = <0>;
115 micdet-delay = <100>;
116 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
117 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200118 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700119
120 sdhci@78000000 {
121 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
122 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
123 power-gpios = <&gpio 31 0>; /* gpio PD7 */
124 };
125
126 sdhci@78000200 {
127 status = "disable";
128 };
129
130 sdhci@78000400 {
131 status = "disable";
132 };
133
134 sdhci@78000400 {
135 support-8bit;
136 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600137
138 ahub@70080000 {
139 i2s@70080300 {
140 status = "disable";
141 };
142
143 i2s@70080500 {
144 status = "disable";
145 };
146
147 i2s@70080600 {
148 status = "disable";
149 };
150
151 i2s@70080700 {
152 status = "disable";
153 };
154 };
155
156 sound {
157 compatible = "nvidia,tegra-audio-wm8903-cardhu",
158 "nvidia,tegra-audio-wm8903";
159 nvidia,model = "NVIDIA Tegra Cardhu";
160
161 nvidia,audio-routing =
162 "Headphone Jack", "HPOUTR",
163 "Headphone Jack", "HPOUTL",
164 "Int Spk", "ROP",
165 "Int Spk", "RON",
166 "Int Spk", "LOP",
167 "Int Spk", "LON",
168 "Mic Jack", "MICBIAS",
169 "IN1L", "Mic Jack";
170
171 nvidia,i2s-controller = <&tegra_i2s1>;
172 nvidia,audio-codec = <&wm8903>;
173
174 nvidia,spkr-en-gpios = <&wm8903 2 0>;
175 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
176 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200177};