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gerrit-public.fairphone.software / kernel / msm-4.19 / 8d69043d9950d276bb8553eb57a9b2c24833cf76 / . / arch / arm / boot / dts / imx25-karo-tx25.dts
blob: c84d5c932a99ebc4b2783caf0630ccc988d836f5 [file] [log] [blame]
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "imx25.dtsi"
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]14
15/ {
16 model = "Ka-Ro TX25";
17 compatible = "karo,imx25-tx25", "fsl,imx25";
18
Sascha Hauer48f51962014-05-07 15:19:00 +0200[diff] [blame]19 chosen {
20 stdout-path = &uart1;
21 };
22
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]23 memory {
24 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
25 };
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]26};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]27
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame^]28&iomuxc {
29 pinctrl_uart1: uart1grp {
30 fsl,pins = <
31 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
32 MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
33 MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
34 MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
35 >;
36 };
37
38 pinctrl_fec: fecgrp {
39 fsl,pins = <
40 MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
41 MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
42 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
43 MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
44 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
45 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
46 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
47 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
48 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
49 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
50 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
51 >;
52 };
53
54 pinctrl_nfc: nfcgrp {
55 fsl,pins = <
56 MX25_PAD_NF_CE0__NF_CE0 0x80000000
57 MX25_PAD_NFWE_B__NFWE_B 0x80000000
58 MX25_PAD_NFRE_B__NFRE_B 0x80000000
59 MX25_PAD_NFALE__NFALE 0x80000000
60 MX25_PAD_NFCLE__NFCLE 0x80000000
61 MX25_PAD_NFWP_B__NFWP_B 0x80000000
62 MX25_PAD_NFRB__NFRB 0x80000000
63 MX25_PAD_D7__D7 0x80000000
64 MX25_PAD_D6__D6 0x80000000
65 MX25_PAD_D5__D5 0x80000000
66 MX25_PAD_D4__D4 0x80000000
67 MX25_PAD_D3__D3 0x80000000
68 MX25_PAD_D2__D2 0x80000000
69 MX25_PAD_D1__D1 0x80000000
70 MX25_PAD_D0__D0 0x80000000
71 >;
72 };
73};
74
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]75&uart1 {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame^]76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]78 status = "okay";
79};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]80
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]81&fec {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame^]82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_fec>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]84 phy-mode = "rmii";
Fabio Estevam152fab62013-01-04 10:29:09 -0200[diff] [blame]85 status = "okay";
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]86};
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]87
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]88&nfc {
Sascha Hauer8d690432014-05-09 08:11:17 +0200[diff] [blame^]89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_nfc>;
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]91 nand-on-flash-bbt;
92 status = "okay";
Sascha Hauer62300cb2012-11-12 11:58:51 +0100[diff] [blame]93};